MAPPING LOGICAL AND PHYSICAL PROCESSORS AND LOGICAL AND PHYSICAL MEMORY

FIELD OF THE INVENTION

The present invention relates to system configuration, and more particularly to mapping logical processors to physical processors and mapping logical memory to physical memory.

BACKGROUND

Current high-performance computing (HPC) and graphics are capable of utilizing more memory bandwidth than can currently be provided given modern system memory implementations. For example, many HPC applications have a byte to FLOP (B:F) ratio between 8:1 and 1:1—that is, they require from one to eight bytes from main memory for every floating-point operation performed. In another example, the High-Performance Conjugate Gradient (HPCG) Benchmark, has a B:F ratio greater than four. Modern graphics processing units (GPUs) that provide 10 FLOPS per B/s of memory bandwidth create a significant memory limitation for such applications.

There is therefore a need for an improved high-performance memory implementation within a processing environment, as well as a means to reconfigure the memory implementation around faulty processors and faulty memory channels while preserving locality.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an exemplary one-level data storage sub-system, in accordance with an embodiment.

FIG. 2 illustrates an exemplary one-level memory system, in accordance with an embodiment.

FIG. 3 illustrates a flowchart of a method for mapping an array of physical processors to an array of logical processors, in accordance with an embodiment.

FIG. 4 illustrates a flowchart of a method for mapping logical memory channels to functional physical memory channels, in accordance with an embodiment.

FIG. 5 illustrates a parallel processing unit, in accordance with an embodiment.

FIG. 6A illustrates a general processing cluster within the parallel processing unit of FIG. 5, in accordance with an embodiment.

FIG. 6B illustrates a memory partition unit of the parallel processing unit of FIG. 5, in accordance with an embodiment.

FIG. 7A illustrates the streaming multi-processor of FIG. 6A, in accordance with an embodiment.

FIG. 7B is a conceptual diagram of a processing system implemented using the PPU of FIG. 5, in accordance with an embodiment.

FIG. 7C illustrates an exemplary system in which the various architecture and/or functionality of the various previous embodiments may be implemented.

DETAILED DESCRIPTION

A single-level memory system is provided with the main memory of the system consisting of a number of memory banks located near each streaming multiprocessor (SM). In one embodiment, the memory banks may be stacked on top of the GPU chip. Such an arrangement can provide a significantly improved B:F ratio when compared to contemporary GPUs (e.g., a B:F ratio of −4:1) as well as a much lower transfer energy per bit (e.g., 1000/bit vs 5pJ/bit).

Additionally, a mapping may be made between an array of physical processors and an array of functional logical processors. Also, a mapping may be made between logical memory channels (associated with the logical processors) and functional physical memory channels (associated with the physical processors). These mappings may be stored within one or more tables, which may then be used to bypass faulty processors and memory channels when implementing memory accesses, while optimizing locality (e.g., by minimizing the distance of memory channels to processors).

FIG. 1 illustrates an exemplary one-level data storage sub-system 100, according to one exemplary embodiment. As shown, a processor 102, mapper 104, and data storage entity 106 are all co-located within the data storage sub-system 100. For example, the processor 102, mapper 104, and data storage entity 106 may or may not be integrated within the data storage sub-system 100. In one embodiment, a plurality of data storage sub-systems 100 may be implemented within a larger data storage system (e.g., a one-level memory system, etc.).

Additionally, in one embodiment, the processor 102 may include a streaming multiprocessor (SM). For example, the processor 102 may include a graphics processing unit (GPU) streaming multiprocessor. In another embodiment, the processor 102 may include a central processing unit (CPU).

Further, in one embodiment, the data storage entity 106 may include any hardware utilized to store digital data. For example, the data storage entity may include an individual memory block such as an individual memory sub-array that is located in a stacked configuration on top of the processor 102. Of course, however, the data storage entity 106 may include any hardware for storing data, such as flash memory, a storage disk, a solid-state drive, etc. In another embodiment, the data storage entity 106 may include a frame-buffer bank in a GPU, a memory channel in a CPU, etc.

Further still, in one embodiment, the mapper 104 may include computing hardware that facilitates the retrieval of data from the data storage entity 106. For example, the mapper 104 may receive a read or write request from the processor 102. In another example, the mapper 104 may receive a read or write request from another data storage sub-system via a network connection 108. In another embodiment, the network connection 108 may forward a request directly to the data storage entity 106 without passing the request through the mapper 104. In yet another embodiment, the mapper 104 may include a circuit in communication with processor 102 and the data storage entity 106. This communication may be direct or indirect. In another embodiment, the mapper 104 may include a specialized circuit. For example, the mapper 104 may include a specialized circuit on the same die as the processor 102 and the network connection 108. In yet another embodiment, the mapper 104 may include a general processor.

Also, in one embodiment, the mapper 104 may identify a virtual address included within the read or write request. In another embodiment, the mapper 104 may identify a portion of the virtual address as the segment number, and may locate a segment descriptor in a lookup table, utilizing the segment number. In yet another embodiment, using the segment descriptor, the mapper 104 may identify the data storage entity 106 (or another data storage entity of another sub-system) and a starting location within the data storage entity 106 (e.g., a location where the data read or write is to be performed). In another example, the mapper 104 may identify the data storage sub-system 100 containing the data storage entity 106, as well as the starting location within the data storage entity 106. In still another embodiment, the mapper 104 may implement the read or write request utilizing the identified data storage entity and starting location within the data storage entity.

In addition, in one embodiment, the mapper 104 may include computing hardware that facilitates the storage of data to the data storage entity 106. For example, given an N-dimensional array to be stored within the system, the mapper 104 may map the N-dimensional array such that one N-dimensional sub-array of the N-dimensional array is stored within the data storage entity 106. In another example, the N-dimensional sub-arrays of the N-dimensional array may be stored within a predetermined segment (portion) of the data storage entity 106.

Further, in one embodiment, the mapper 104 may perform a predetermined function (e.g., a shuffle operation) on bits of an address field for stored data (e.g., an N-dimensional array) to form a data storage entity address for the data (e.g., that indicates the data storage entity 106 storing the data or the data storage sub-system 100 containing the data storage entity 106) and an offset location within the data storage entity 106 for the data (e.g., where the data is located within the data storage entity 106).

Further still, in one embodiment, the mapper 104 may store a segment descriptor (e.g., in a lookup table) that is associated with a predetermined segment (portion) of the virtual address space where the N-dimensional array is stored. In another embodiment, the segment descriptor may indicate how to use the bits of a virtual address to identify the data storage entity 106 where the data is stored or the data storage sub-system 100 containing the data storage entity 106 where the data is stored, as well as the offset location within the data storage entity 106 where the data is located. In yet another embodiment, the mapper may store a plurality of segment descriptors, where each segment descriptor is associated with an N-dimensional matrix stored within a data storage entity in communication with the mapper 104.

Also, in one embodiment, given an N-dimensional array to be stored within the system, the mapper 104 may map the N-dimensional array such that N-dimensional sub-arrays of the N-dimensional array are stored across a plurality of different data storage entities. For example, the N-dimensional sub-arrays of the N-dimensional array may be interleaved by dimension at a predetermined granularity across the plurality of different data storage entities. In another embodiment, the N-dimensional sub-arrays of the N-dimensional array may be mapped to a predetermined subset of the plurality of data storage entities.

In this way, the mapper 104 may facilitate memory localization to reduce the energy and latency of memory accesses within a data storage system.

FIG. 2 illustrates an exemplary one-level memory system 200, according to one exemplary embodiment. As shown, the system 200 includes a plurality of interposers 206A-N, where each of the plurality of interposers 206A-N include a plurality of chip stacks 204A-N, and each of the plurality of chip stacks 204A-N include a plurality of tiles 202A-N.

Additionally, on each tile 202A-N, a streaming multiprocessor (SM) 208A-N(or small group of SMs) is co-located with a block of main memory 210A-N. A portion of this block of main memory 210A-N may be mapped into the address space so that the state of one partition of a problem (e.g., a sub-volume of a 3D physics simulation, or a sub-matrix of a matrix calculation) resides entirely within this block of main memory 210A-N. Other portions of the block of main memory 210A-N can be mapped as a cache, or as interleaved memory to hold global state shared by all partitions, or to hold a sub-matrix of a different matrix.

Further, memory requests by an SM 208A-N are translated by a corresponding mapper 212A-N that maintains mappings for each memory segment. Segments may be mapped entirely to one block of main memory 210A-N, or interleaved by dimension at a specified granularity across multiple blocks of main memory 210A-N. Local requests are forwarded directly to the corresponding local block of main memory 210A-N(e.g., through the network component 214A-N). Remote requests are directed to the destination block of main memory 210A-N via a network component 214A-N.

In this way, bandwidth between each SM 208A-N(or group) and its local block of main memory 210A-N may be increased. Remote blocks of main memory 210A-N are accessed via an interconnection network using network components 214A-N. In one embodiment, the interconnection network may use a bandwidth taper providing higher bandwidth to other blocks of main memory 210A-N on the same chip stack 204A-N, lower bandwidth to blocks on other chip stacks 204A-N on the same interposer 206A-N, and yet lower bandwidth to blocks on other packages. Communication between chip stacks 204A-N may be implemented via gateways (GWs) 216A-N(e.g., where each gateway may include a network unit that shifts between channels of different bandwidth, etc.).

In yet another embodiment, the exemplary one-level memory system 200 may be implemented utilizing a parallel processing unit (PPU) such as the PPU 500 illustrated in FIG. 5.

In another embodiment, once a functional physical SM and functional physical memory channel have been assigned to each logical memory channel, a floorsweeping table (described hereinbelow) may be used to hold the mapping from logical unit (1 (layer), r (row), c (column)) to physical unit (lp (layer physical), rp (row physical), cp (column physical)). In one example, with 128 logical tiles and 9 logical layers (one SM layer and 8 DRAM layers) the table will have 1,152 entries. Each entry consists of 13 bits: 1p (4 bits), rp (5 bits), and cp (4 bits). The floorsweeping table may be distributed and stored by each of the streaming multiprocessors (SMs) 208A-N.

In one example, when accessing memory, a streaming multiprocessor (SM) 208A generates a virtual address. The corresponding mapper 212A converts the virtual address into a logical tile address and an offset (which includes a logical layer). The floorsweeping table then converts the logical tile and logical layer to a physical tile and physical layer. If the physical tile matches a current corresponding physical tile 202A, the request is routed directly to the memory channel for the physical layer. If not, the request is forwarded to the network component 214A (such as a network on a chip (NoC)) which routes to the correct physical tile.

In one embodiment, memory request messages (read and write requests) come from a physical processor, so the memory reply messages (read and write replies) may be sent directly to the requesting physical processor and no logical to physical translation may be required. In another embodiment, a processor layer of the floorsweeping table is used for sending messages directly to a logical processor—for message-driven computing.

FIG. 3 illustrates a flowchart of a method 300 for mapping an array of physical processors to an array of logical processors, in accordance with an embodiment. Although method 300 is described in the context of a processing unit, the method 300 may also be performed by a program, custom circuitry, or by a combination of custom circuitry and a program. For example, the method 300 may be executed by a GPU (graphics processing unit), CPU (central processing unit), or any processing element. Furthermore, persons of ordinary skill in the art will understand that any system that performs method 300 is within the scope and spirit of embodiments of the present invention. Further, the method 300 may be performed by the exemplary one-level data storage sub-system 100 of FIG. 1, the exemplary one-level memory system 200 of FIG. 2, etc.

As shown in operation 302, an array of physical processors is identified. In one embodiment, the plurality of physical processors may be configured in a grid formation. In another embodiment, each of the array of physical processors may include a streaming multiprocessor (SM). For example, the streaming multiprocessors may be included within one or more graphics processing unit (GPU) die.

Additionally, in one embodiment, each of the array of physical processors may include a central processing unit (CPU). In another embodiment, the array of physical processors may include a plurality of rows of physical processors. In another embodiment, the array of physical processors may be situated at a wafer level.

Further, as shown in operation 304, the array of logical processors is mapped to an array of physical processors, where faulty physical processors are bypassed during the mapping. In one embodiment, the mapping may include performing one or more floorsweeping operations that identify and bypass faulty physical processors. In another embodiment, the array of logical processors may be configured in a grid formation.

For example, the array of logical processors may have smaller dimensions (e.g., fewer rows and/or columns, etc.) than the array of physical processors. In another example, the array of logical processors may include an 8×16 unit grid, whereas the array of physical processors may include a 9×16 unit grid.

Further still, in one embodiment, each logical processor within the array of logical processors may be mapped to a functional (e.g., non-faulty) physical processor within the array of physical processors. In another embodiment, the array of physical processors may be analyzed by row.

Also, in one embodiment, in response to determining that each physical processor within the row is functional (e.g., not faulty), the logical processors within a corresponding row of the logical processor array may be mapped to corresponding physical processors within the row of the physical processor array. In another embodiment, one or more physical processors within the row may be labeled as spare functional physical processors in response to determining that a length of the corresponding row of the logical processor array is less than the length of the row of the physical processor array.

In addition, in one embodiment, in response to determining that one or more physical processors within the row are faulty (e.g., not functional), the logical processors within the corresponding row of the logical processor array may be mapped to only the physical processors within the row of the physical processor array that are determined to be functional. In another embodiment, any logical processors within the corresponding row of the logical processor array that are not mapped to a physical processor may be mapped to an available spare functional physical processor within the row, or a functional physical processor within an adjacent row of the physical processor array. In yet another embodiment, the mapping may be modified utilizing one or more optimization algorithms (e.g., simulated annealing).

In this way, the mapping may effectively bypass faulty physical processors within a row of the physical processor array and may map each of the logical processors within a corresponding row of the logical processor array to a functional physical processor within the row of the physical processor array, a spare functional physical processor within the row of the physical processor array, or a functional physical processor within an adjacent row of the physical processor array. This may eliminate faulty physical processors while maximizing locality within the computing system, which may improve a performance of hardware implementing memory requests within the computing system.

Furthermore, in one embodiment, the logical/physical processor mapping may be stored within a table (e.g., a floorsweeping table). For example, the table may store mappings from each logical processor to its corresponding functional physical processor.

In yet another embodiment, the aforementioned functionality may be performed utilizing a parallel processing unit (PPU) such as the PPU 500 illustrated in FIG. 5.

FIG. 4 illustrates a flowchart of a method 400 for mapping logical memory channels to functional physical memory channels, in accordance with an embodiment. Although method 400 is described in the context of a processing unit, the method 400 may also be performed by a program, custom circuitry, or by a combination of custom circuitry and a program. For example, the method 400 may be executed by a GPU (graphics processing unit), CPU (central processing unit), or any processing element. Furthermore, persons of ordinary skill in the art will understand that any system that performs method 400 is within the scope and spirit of embodiments of the present invention. Further, the method 400 may be performed by the exemplary one-level data storage sub-system 100 of FIG. 1, the exemplary one-level memory system 200 of FIG. 2, etc.

As shown in operation 402, a predetermined number of logical memory channels are identified. In one embodiment, the predetermined number of logical memory channels may correspond to a plurality of logical processors. In another embodiment, each logical processor within an array of logical processors may have a corresponding predetermined number of logical memory channels. In yet another embodiment, each logical processor within the array of logical processors may be mapped to a functional physical processor within an array of physical processors.

Additionally, as shown in operation 404, each of the predetermined number of logical memory channels is mapped to a corresponding functional physical memory channel. In one embodiment, a physical memory channel may include a means of communication between a processor and an instance of memory (e.g., dynamic random-access memory (DRAM), etc.).

Further, in one embodiment, for each logical processor within an array of logical processors, a corresponding physical processor may be identified (e.g., within an array of physical processors) that is mapped to the logical processor. For example, an earlier mapping between the array of physical processors and the array of logical processors may ensure that this physical processor is a functional (e.g., non-faulty) physical processor. In another embodiment, a predetermined number of functional physical memory channels may then be determined for the physical processor and mapped to logical memory channels for the corresponding logical processor.

For example, the physical processor may be included within an array of physical processors. In another example, an array of physical memory (e.g., DRAM) may be physically stacked on top of an array of physical processors, such that one or more instances of physical memory are physically located above each physical processor. For instance, a stack of DRAM dies may be disposed on top of a processor die. In yet another example, each instance of physical memory may have an associated plurality of physical memory channels by which the memory is accessed by one or more processors.

Further still, in one embodiment, each physical memory location within the array of physical memory may be physically located above a corresponding physical processor within the array of physical processors. In another embodiment, this physical memory location may have a predetermined number of physical memory channels. In yet another embodiment, for a given physical processor mapped to a corresponding logical processor, each of the physical memory channels within the physical memory location above the physical processor may be tested.

Also, in one embodiment, physical memory channels that are determined to be functional may be mapped to logical memory channels for the logical processor that is mapped to the physical processor. In another embodiment, in response to determining that the number of functional memory channels within the physical memory location above the physical processor is less than the predetermined number of functional physical memory channels to be mapped, additional functional physical memory channels within neighboring physical memory locations may be mapped to remaining logical memory channels for the logical processor that is mapped to the physical processor.

In addition, in one embodiment, functional physical memory channels within neighboring physical memory locations that are not currently mapped to other logical memory channels (for other logical processors) may be mapped before functional physical memory channels within neighboring physical memory locations that are currently mapped to other logical memory channels. In another embodiment, mapping of functional physical memory channels that are currently mapped to other logical memory channels may be performed in a distributed/randomized manner.

In this way, the mapping may effectively bypass faulty physical memory channels and may map physical memory channels close to corresponding mapped physical processors. This may eliminate faulty physical memory channels while maximizing locality for memory access within the computing system, which may improve a performance of hardware implementing memory requests within the computing system.

Furthermore, in one embodiment, the logical/physical memory channel mapping may be stored within a table (e.g., a floorsweeping table). For example, the table may store mappings from each logical memory channel to its corresponding functional physical memory channel. In another embodiment, a single floorsweeping table may store all logical/physical unit mappings. For example, the table may store mappings from each logical processor to its corresponding functional physical processor, and mappings from each logical memory channel to its corresponding functional physical memory channel. In yet another embodiment, the single floorsweeping table may be distributed to (and stored at) each of a plurality of processors within a system (e.g., a one-level memory system, etc.).

Further still, in one embodiment, in response to receiving a virtual address included within a request, a mapper may identify a portion of the virtual address as the segment number, locate a segment descriptor in a lookup table, utilizing the segment number, and identify, using the segment descriptor, a logical data storage entity address and an offset (which includes a logical layer address). For example, logical data storage entity address and the logical layer address may then be converted to a physical data storage entity address and a physical layer address, utilizing the floorsweeping table.

In yet another embodiment, the aforementioned functionality may be performed utilizing a parallel processing unit (PPU) such as the PPU 500 illustrated in FIG. 5.

More illustrative information will now be set forth regarding various optional architectures and features with which the foregoing framework may be implemented, per the desires of the user. It should be strongly noted that the following information is set forth for illustrative purposes and should not be construed as limiting in any manner. Any of the following features may be optionally incorporated with or without the exclusion of other features described.

OLM Redundancy

In one embodiment, an OLM system may include a stack of DRAM dies stacked on top of a GPU die. The GPU die may contain several SMs some of which will be floorswept (e.g., some SMs may be bad and will be mapped out), and the DRAM die may have several DRAM channels per SM. Some entire DRAM channels may be bad while other DRAM channels may need repair—substituting spare rows and columns to replace bad bits. In particular, a stacked system is assembled using wafer-to-wafer bonding, “known good die” may not be available for selection during assembly, and this may result in a number of bad DRAM channels. In response, a novel approach may provide redundancy while preserving as much locality as possible.

In one exemplary embodiment, an array of 144 SMs may be arranged in a 9×16 grid. This grid may be floorswept down to 128 SMs in a logical 8×16 grid. In another embodiment, each SM may be associated with eight DRAM channels (one from each layer). The channels associated with SMs that are floorswept may still be accessible via the NoC. It one example, it may be assumed that a predetermined percentage (e.g., 10%) of the channels are “bad” and the remaining channels have four spare rows and four spare columns in each bank.

Floorsweeping Processors

One exemplary approach to configure the SMs around bad SMs is as follows:

- For r=0:15 (for each row)
  - If there are no bad SMs in this row,
    - Configure SM (r, 0:7) to be themselves SM(r, 8) is a spare.
  - If there is one bad SM in this row at column c
    - Configure SM(r, 0:c−1) to be themselves and SM(r, c+1:8) to be SM(r,c:7).
  - If there are two bad SMs in this row at c1 and c2 and there is a spare in row r−1
  - Configure SM(r, 1:c1−1) to be themselves, SM(r, c1+1:c2−1) to be (c1:c2−2), SM(r−1, c2+1) to be (r, c2), and SM(r,c2+1:9) to be (r,c2:8). Shift over the mappings in row r−1 to accommodate the stolen SM.
- If there are two or more bad SMs in this row at c1 and c2 . . . and there is no spare in r−1
  - Configure around c1 as above and steal c2 . . . from row r+1 (this propagates bad SMs to row r+1 but will fail if there isn't a good SM to steal).
- If there are three or more bad SMs in this row at c1, c2, and c3 . . . and there is a spare in r−1
  - Configure around c1 and c2 as above and steal c3 . . . from the row above.

This approach may keep logical SMs within one position in x and y of their error-free locations and may therefore keep an amount of network hops needed to reach neighbors to at most two.

Another exemplary approach may start with a naïve mapping of logical to physical SMs that avoids bad SMs, which may be improved using an optimization algorithm like simulated annealing. Here the objective function for optimization may include a function of the total distance between logical neighbors and the maximum distance between logical neighbors. This may configure around more bad SMs than the simple algorithm and may result in less distance.

Floorsweeping DRAM Channels

In one embodiment, every configured SM may need to be assigned a predetermined number of DRAM channels (e.g., eight DRAM channels, etc.). Ideally these channels should be as close to the SM as possible. The following exemplary algorithm makes a reasonable assignment:

For each logical SM (r, c) which has been mapped to physical coordinates (rp, cp).

- Assign all “good” unassigned channels at (rp, cp) to this SM.
  - These become logical channels (r, c, i) for i=0:7
- If fewer than 8 channels are assigned
  - Assign channels from neighboring physical coordinates with no mapped SM
    - Do this evenly over the available coordinates (a bad SM may have good DRAM channels on top of it)
  - If fewer than 8 channels still assigned
    - Assign channels from unassigned neighboring physical coordinates with mapped SMs
      - Do this evenly over such neighbors
      - This will cause these SMs to need to borrow from their neighbors
  - If fewer than 8 channels still assigned
    - Look at neighbors of neighbors

In one embodiment, an optimization algorithm (such as simulated annealing) may also be applied to this algorithm.

Spare Rows and Columns

In one embodiment, to simplify DRAM logic, the GPU may keep the map of bad rows and bit cells in the DRAM and perform the row and column repair using spares. For up to NC bad bit cells in a row, the GPU makes a spare column repair entry for that row consisting of the channel address, bank address, row address, and up to NC columns to be replaced by spare columns. The memory controller associated with the channel keeps these entries for each channel. On a read, the GPU may read the requested word and the spare columns and makes substitutions as necessary. On a write, the GPU may write the specified word and may write any spare columns mapped into that word.

If the entire row is bad or if the row has more than NC bad bits (and hence can't be repaired with spare columns), the GPU may replace the entire row with a spare row. For up to NR bad rows in a bank, the GPU may maintain a spare row entry that contains the channel address, bank address, row address, and spare row number. Reads and writes to the bad row may be directed to the spare row. The spare row itself may have bad bits that get replaced by spare columns as described above.

Parallel Processing Architecture

FIG. 5 illustrates a parallel processing unit (PPU) 500, in accordance with an embodiment. In an embodiment, the PPU 500 is a multi-threaded processor that is implemented on one or more integrated circuit devices. The PPU 500 is a latency hiding architecture designed to process many threads in parallel. A thread (i.e., a thread of execution) is an instantiation of a set of instructions configured to be executed by the PPU 500. In an embodiment, the PPU 500 is a graphics processing unit (GPU) configured to implement a graphics rendering pipeline for processing three-dimensional (3D) graphics data in order to generate two-dimensional (2D) image data for display on a display device such as a liquid crystal display (LCD) device. In other embodiments, the PPU 500 may be utilized for performing general-purpose computations. While one exemplary parallel processor is provided herein for illustrative purposes, it should be strongly noted that such processor is set forth for illustrative purposes only, and that any processor may be employed to supplement and/or substitute for the same.

One or more PPUs 500 may be configured to accelerate thousands of High Performance Computing (HPC), data center, and machine learning applications. The PPU 500 may be configured to accelerate numerous deep learning systems and applications including autonomous vehicle platforms, deep learning, high-accuracy speech, image, and text recognition systems, intelligent video analytics, molecular simulations, drug discovery, disease diagnosis, weather forecasting, big data analytics, astronomy, molecular dynamics simulation, financial modeling, robotics, factory automation, real-time language translation, online search optimizations, and personalized user recommendations, and the like.

As shown in FIG. 5, the PPU 500 includes an Input/Output (I/O) unit 505, a front end unit 515, a scheduler unit 520, a work distribution unit 525, a hub 530, a crossbar (Xbar) 570, one or more general processing clusters (GPCs) 550, and one or more partition units 580. The PPU 500 may be connected to a host processor or other PPUs 500 via one or more high-speed NVLink 510 interconnect. The PPU 500 may be connected to a host processor or other peripheral devices via an interconnect 502. The PPU 500 may also be connected to a local memory comprising a number of memory devices 504. In an embodiment, the local memory may comprise a number of dynamic random access memory (DRAM) devices. The DRAM devices may be configured as a high-bandwidth memory (HBM) subsystem, with multiple DRAM dies stacked within each device.

The NVLink 510 interconnect enables systems to scale and include one or more PPUs 500 combined with one or more CPUs, supports cache coherence between the PPUs 500 and CPUs, and CPU mastering. Data and/or commands may be transmitted by the NVLink 510 through the hub 530 to/from other units of the PPU 500 such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. (not explicitly shown). The NVLink 510 is described in more detail in conjunction with FIG. 7B.

The I/O unit 505 is configured to transmit and receive communications (i.e., commands, data, etc.) from a host processor (not shown) over the interconnect 502. The I/O unit 505 may communicate with the host processor directly via the interconnect 502 or through one or more intermediate devices such as a memory bridge. In an embodiment, the I/O unit 505 may communicate with one or more other processors, such as one or more the PPUs 500 via the interconnect 502. In an embodiment, the I/O unit 505 implements a Peripheral Component Interconnect Express (PCIe) interface for communications over a PCIe bus and the interconnect 502 is a PCIe bus. In alternative embodiments, the I/O unit 505 may implement other types of well-known interfaces for communicating with external devices.

The I/O unit 505 decodes packets received via the interconnect 502. In an embodiment, the packets represent commands configured to cause the PPU 500 to perform various operations. The I/O unit 505 transmits the decoded commands to various other units of the PPU 500 as the commands may specify. For example, some commands may be transmitted to the front end unit 515. Other commands may be transmitted to the hub 530 or other units of the PPU 500 such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. (not explicitly shown). In other words, the I/O unit 505 is configured to route communications between and among the various logical units of the PPU 500.

In an embodiment, a program executed by the host processor encodes a command stream in a buffer that provides workloads to the PPU 500 for processing. A workload may comprise several instructions and data to be processed by those instructions. The buffer is a region in a memory that is accessible (i.e., read/write) by both the host processor and the PPU 500. For example, the I/O unit 505 may be configured to access the buffer in a system memory connected to the interconnect 502 via memory requests transmitted over the interconnect 502. In an embodiment, the host processor writes the command stream to the buffer and then transmits a pointer to the start of the command stream to the PPU 500. The front end unit 515 receives pointers to one or more command streams. The front end unit 515 manages the one or more streams, reading commands from the streams and forwarding commands to the various units of the PPU 500.

The front end unit 515 is coupled to a scheduler unit 520 that configures the various GPCs 550 to process tasks defined by the one or more streams. The scheduler unit 520 is configured to track state information related to the various tasks managed by the scheduler unit 520. The state may indicate which GPC 550 a task is assigned to, whether the task is active or inactive, a priority level associated with the task, and so forth. The scheduler unit 520 manages the execution of a plurality of tasks on the one or more GPCs 550.

The scheduler unit 520 is coupled to a work distribution unit 525 that is configured to dispatch tasks for execution on the GPCs 550. The work distribution unit 525 may track a number of scheduled tasks received from the scheduler unit 520. In an embodiment, the work distribution unit 525 manages a pending task pool and an active task pool for each of the GPCs 550. The pending task pool may comprise a number of slots (e.g., 32 slots) that contain tasks assigned to be processed by a particular GPC 550. The active task pool may comprise a number of slots (e.g., 4 slots) for tasks that are actively being processed by the GPCs 550. As a GPC 550 finishes the execution of a task, that task is evicted from the active task pool for the GPC 550 and one of the other tasks from the pending task pool is selected and scheduled for execution on the GPC 550. If an active task has been idle on the GPC 550, such as while waiting for a data dependency to be resolved, then the active task may be evicted from the GPC 550 and returned to the pending task pool while another task in the pending task pool is selected and scheduled for execution on the GPC 550.

The work distribution unit 525 communicates with the one or more GPCs 550 via XBar 570. The XBar 570 is an interconnect network that couples many of the units of the PPU 500 to other units of the PPU 500. For example, the XBar 570 may be configured to couple the work distribution unit 525 to a particular GPC 550. Although not shown explicitly, one or more other units of the PPU 500 may also be connected to the XBar 570 via the hub 530.

The tasks are managed by the scheduler unit 520 and dispatched to a GPC 550 by the work distribution unit 525. The GPC 550 is configured to process the task and generate results. The results may be consumed by other tasks within the GPC 550, routed to a different GPC 550 via the XBar 570, or stored in the memory 504. The results can be written to the memory 504 via the partition units 580, which implement a memory interface for reading and writing data to/from the memory 504. The results can be transmitted to another PPU 500 or CPU via the NVLink 510. In an embodiment, the PPU 500 includes a number U of partition units 580 that is equal to the number of separate and distinct memory devices 504 coupled to the PPU 500. A partition unit 580 will be described in more detail below in conjunction with FIG. 6B.

In an embodiment, a host processor executes a driver kernel that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU 500. In an embodiment, multiple compute applications are simultaneously executed by the PPU 500 and the PPU 500 provides isolation, quality of service (QoS), and independent address spaces for the multiple compute applications. An application may generate instructions (i.e., API calls) that cause the driver kernel to generate one or more tasks for execution by the PPU 500. The driver kernel outputs tasks to one or more streams being processed by the PPU 500. Each task may comprise one or more groups of related threads, referred to herein as a warp. In an embodiment, a warp comprises 32 related threads that may be executed in parallel. Cooperating threads may refer to a plurality of threads including instructions to perform the task and that may exchange data through shared memory. Threads and cooperating threads are described in more detail in conjunction with FIG. 7A.

FIG. 6A illustrates a GPC 550 of the PPU 500 of FIG. 5, in accordance with an embodiment. As shown in FIG. 6A, each GPC 550 includes a number of hardware units for processing tasks. In an embodiment, each GPC 550 includes a pipeline manager 610, a pre-raster operations unit (PROP) 615, a raster engine 625, a work distribution crossbar (WDX) 680, a memory management unit (MMU) 690, and one or more Data Processing Clusters (DPCs) 620. It will be appreciated that the GPC 550 of FIG. 6A may include other hardware units in lieu of or in addition to the units shown in FIG. 6A.

In an embodiment, the operation of the GPC 550 is controlled by the pipeline manager 610. The pipeline manager 610 manages the configuration of the one or more DPCs 620 for processing tasks allocated to the GPC 550. In an embodiment, the pipeline manager 610 may configure at least one of the one or more DPCs 620 to implement at least a portion of a graphics rendering pipeline. For example, a DPC 620 may be configured to execute a vertex shader program on the programmable streaming multiprocessor (SM) 640. The pipeline manager 610 may also be configured to route packets received from the work distribution unit 525 to the appropriate logical units within the GPC 550. For example, some packets may be routed to fixed function hardware units in the PROP 615 and/or raster engine 625 while other packets may be routed to the DPCs 620 for processing by the primitive engine 635 or the SM 640. In an embodiment, the pipeline manager 610 may configure at least one of the one or more DPCs 620 to implement a neural network model and/or a computing pipeline.

The PROP unit 615 is configured to route data generated by the raster engine 625 and the DPCs 620 to a Raster Operations (ROP) unit, described in more detail in conjunction with FIG. 6B. The PROP unit 615 may also be configured to perform optimizations for color blending, organize pixel data, perform address translations, and the like.

The raster engine 625 includes a number of fixed function hardware units configured to perform various raster operations. In an embodiment, the raster engine 625 includes a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, and a tile coalescing engine. The setup engine receives transformed vertices and generates plane equations associated with the geometric primitive defined by the vertices. The plane equations are transmitted to the coarse raster engine to generate coverage information (e.g., an x,y coverage mask for a tile) for the primitive. The output of the coarse raster engine is transmitted to the culling engine where fragments associated with the primitive that fail a z-test are culled, and transmitted to a clipping engine where fragments lying outside a viewing frustum are clipped. Those fragments that survive clipping and culling may be passed to the fine raster engine to generate attributes for the pixel fragments based on the plane equations generated by the setup engine. The output of the raster engine 625 comprises fragments to be processed, for example, by a fragment shader implemented within a DPC 620.

Each DPC 620 included in the GPC 550 includes an M-Pipe Controller (MPC) 630, a primitive engine 635, and one or more SMs 640. The MPC 630 controls the operation of the DPC 620, routing packets received from the pipeline manager 610 to the appropriate units in the DPC 620. For example, packets associated with a vertex may be routed to the primitive engine 635, which is configured to fetch vertex attributes associated with the vertex from the memory 504. In contrast, packets associated with a shader program may be transmitted to the SM 640.

The SM 640 comprises a programmable streaming processor that is configured to process tasks represented by a number of threads. Each SM 640 is multi-threaded and configured to execute a plurality of threads (e.g., 32 threads) from a particular group of threads concurrently. In an embodiment, the SM 640 implements a SIMD (Single-Instruction, Multiple-Data) architecture where each thread in a group of threads (i.e., a warp) is configured to process a different set of data based on the same set of instructions. All threads in the group of threads execute the same instructions. In another embodiment, the SM 640 implements a SIMT (Single-Instruction, Multiple Thread) architecture where each thread in a group of threads is configured to process a different set of data based on the same set of instructions, but where individual threads in the group of threads are allowed to diverge during execution. In an embodiment, a program counter, call stack, and execution state is maintained for each warp, enabling concurrency between warps and serial execution within warps when threads within the warp diverge. In another embodiment, a program counter, call stack, and execution state is maintained for each individual thread, enabling equal concurrency between all threads, within and between warps. When execution state is maintained for each individual thread, threads executing the same instructions may be converged and executed in parallel for maximum efficiency. The SM 640 will be described in more detail below in conjunction with FIG. 7A.

The MMU 690 provides an interface between the GPC 550 and the partition unit 580. The MMU 690 may provide translation of virtual addresses into physical addresses, memory protection, and arbitration of memory requests. In an embodiment, the MMU 690 provides one or more translation lookaside buffers (TLBs) for performing translation of virtual addresses into physical addresses in the memory 504.

FIG. 6B illustrates a memory partition unit 580 of the PPU 500 of FIG. 5, in accordance with an embodiment. As shown in FIG. 6B, the memory partition unit 580 includes a Raster Operations (ROP) unit 650, a level two (L2) cache 660, and a memory interface 670. The memory interface 670 is coupled to the memory 504. Memory interface 670 may implement 32, 64, 128, 1024-bit data buses, or the like, for high-speed data transfer. In an embodiment, the PPU 500 incorporates U memory interfaces 670, one memory interface 670 per pair of partition units 580, where each pair of partition units 580 is connected to a corresponding memory device 504. For example, PPU 500 may be connected to up to Y memory devices 504, such as high bandwidth memory stacks or graphics double-data-rate, version 5, synchronous dynamic random access memory, or other types of persistent storage.

FIG. 7A illustrates the streaming multiprocessor 640 of FIG. 6A, in accordance with an embodiment. As shown in FIG. 7A, the SM 640 includes an instruction cache 705, one or more scheduler units 710(K), a register file 720, one or more processing cores 750, one or more special function units (SFUs) 752, one or more load/store units (LSUs) 754, an interconnect network 780, a shared memory/L1 cache 770.

As described above, the work distribution unit 525 dispatches tasks for execution on the GPCs 550 of the PPU 500. The tasks are allocated to a particular DPC 620 within a GPC 550 and, if the task is associated with a shader program, the task may be allocated to an SM 640. The scheduler unit 710(K) receives the tasks from the work distribution unit 525 and manages instruction scheduling for one or more thread blocks assigned to the SM 640. The scheduler unit 710(K) schedules thread blocks for execution as warps of parallel threads, where each thread block is allocated at least one warp. In an embodiment, each warp executes 32 threads. The scheduler unit 710(K) may manage a plurality of different thread blocks, allocating the warps to the different thread blocks and then dispatching instructions from the plurality of different cooperative groups to the various functional units (i.e., cores 750, SFUs 752, and LSUs 754) during each clock cycle.

Cooperative Groups is a programming model for organizing groups of communicating threads that allows developers to express the granularity at which threads are communicating, enabling the expression of richer, more efficient parallel decompositions. Cooperative launch APIs support synchronization amongst thread blocks for the execution of parallel algorithms. Conventional programming models provide a single, simple construct for synchronizing cooperating threads: a barrier across all threads of a thread block (i.e., the syncthreads( )function). However, programmers would often like to define groups of threads at smaller than thread block granularities and synchronize within the defined groups to enable greater performance, design flexibility, and software reuse in the form of collective group-wide function interfaces.

Cooperative Groups enables programmers to define groups of threads explicitly at sub-block (i.e., as small as a single thread) and multi-block granularities, and to perform collective operations such as synchronization on the threads in a cooperative group. The programming model supports clean composition across software boundaries, so that libraries and utility functions can synchronize safely within their local context without having to make assumptions about convergence. Cooperative Groups primitives enable new patterns of cooperative parallelism, including producer-consumer parallelism, opportunistic parallelism, and global synchronization across an entire grid of thread blocks.

A dispatch unit 715 is configured to transmit instructions to one or more of the functional units. In the embodiment, the scheduler unit 710(K) includes two dispatch units 715 that enable two different instructions from the same warp to be dispatched during each clock cycle. In alternative embodiments, each scheduler unit 710(K) may include a single dispatch unit 715 or additional dispatch units 715.

Each SM 640 includes a register file 720 that provides a set of registers for the functional units of the SM 640. In an embodiment, the register file 720 is divided between each of the functional units such that each functional unit is allocated a dedicated portion of the register file 720. In another embodiment, the register file 720 is divided between the different warps being executed by the SM 640. The register file 720 provides temporary storage for operands connected to the data paths of the functional units.

Each SM 640 comprises L processing cores 750. In an embodiment, the SM 640 includes a large number (e.g., 128, etc.) of distinct processing cores 750. Each core 750 may include a fully-pipelined, single-precision, double-precision, and/or mixed precision processing unit that includes a floating point arithmetic logic unit and an integer arithmetic logic unit. In an embodiment, the floating point arithmetic logic units implement the IEEE 754-2008 standard for floating point arithmetic. In an embodiment, the cores 750 include 64 single-precision (32-bit) floating point cores, 64 integer cores, 32 double-precision (64-bit) floating point cores, and 8 tensor cores.

Tensor cores configured to perform matrix operations, and, in an embodiment, one or more tensor cores are included in the cores 750. In particular, the tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inferencing. In an embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiply and accumulate operation D=A×B+C, where A, B, C, and D are 4×4 matrices.

In an embodiment, the matrix multiply inputs A and B are 16-bit floating point matrices, while the accumulation matrices C and D may be 16-bit floating point or 32-bit floating point matrices. Tensor Cores operate on 16-bit floating point input data with 32-bit floating point accumulation. The 16-bit floating point multiply requires 64 operations and results in a full precision product that is then accumulated using 32-bit floating point addition with the other intermediate products for a 4×4×4 matrix multiply. In practice, Tensor Cores are used to perform much larger two-dimensional or higher dimensional matrix operations, built up from these smaller elements. An API, such as CUDA 9 C++ API, exposes specialized matrix load, matrix multiply and accumulate, and matrix store operations to efficiently use Tensor Cores from a CUDA-C++ program. At the CUDA level, the warp-level interface assumes 16×16 size matrices spanning all 32 threads of the warp.

Each SM 640 also comprises M SFUs 752 that perform special functions (e.g., attribute evaluation, reciprocal square root, and the like). In an embodiment, the SFUs 752 may include a tree traversal unit configured to traverse a hierarchical tree data structure. In an embodiment, the SFUs 752 may include texture unit configured to perform texture map filtering operations. In an embodiment, the texture units are configured to load texture maps (e.g., a 2D array of texels) from the memory 504 and sample the texture maps to produce sampled texture values for use in shader programs executed by the SM 640. In an embodiment, the texture maps are stored in the shared memory/L1 cache 670. The texture units implement texture operations such as filtering operations using mip-maps (i.e., texture maps of varying levels of detail). In an embodiment, each SM 540 includes two texture units.

Each SM 640 also comprises N LSUs 754 that implement load and store operations between the shared memory/L1 cache 770 and the register file 720. Each SM 640 includes an interconnect network 780 that connects each of the functional units to the register file 720 and the LSU 754 to the register file 720, shared memory/L1 cache 770. In an embodiment, the interconnect network 780 is a crossbar that can be configured to connect any of the functional units to any of the registers in the register file 720 and connect the LSUs 754 to the register file and memory locations in shared memory/L1 cache 770.

The shared memory/L1 cache 770 is an array of on-chip memory that allows for data storage and communication between the SM 640 and the primitive engine 635 and between threads in the SM 640. In an embodiment, the shared memory/L1 cache 770 comprises 128 KB of storage capacity and is in the path from the SM 640 to the partition unit 580. The shared memory/L1 cache 770 can be used to cache reads and writes. One or more of the shared memory/L1 cache 770, L2 cache 660, and memory 504 are backing stores.

Combining data cache and shared memory functionality into a single memory block provides the best overall performance for both types of memory accesses. The capacity is usable as a cache by programs that do not use shared memory. For example, if shared memory is configured to use half of the capacity, texture and load/store operations can use the remaining capacity. Integration within the shared memory/L1 cache 770 enables the shared memory/L1 cache 770 to function as a high-throughput conduit for streaming data while simultaneously providing high-bandwidth and low-latency access to frequently reused data.

When configured for general purpose parallel computation, a simpler configuration can be used compared with graphics processing. Specifically, the fixed function graphics processing units shown in FIG. 5, are bypassed, creating a much simpler programming model. In the general purpose parallel computation configuration, the work distribution unit 525 assigns and distributes blocks of threads directly to the DPCs 620. The threads in a block execute the same program, using a unique thread ID in the calculation to ensure each thread generates unique results, using the SM 640 to execute the program and perform calculations, shared memory/L1 cache 770 to communicate between threads, and the LSU 754 to read and write global memory through the shared memory/L1 cache 770 and the memory partition unit 580. When configured for general purpose parallel computation, the SM 640 can also write commands that the scheduler unit 520 can use to launch new work on the DPCs 620.

The PPU 500 may be included in a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smart-phone (e.g., a wireless, hand-held device), personal digital assistant (PDA), a digital camera, a vehicle, a head mounted display, a hand-held electronic device, and the like. In an embodiment, the PPU 500 is embodied on a single semiconductor substrate. In another embodiment, the PPU 500 is included in a system-on-a-chip (SoC) along with one or more other devices such as additional PPUs 500, the memory 504, a reduced instruction set computer (RISC) CPU, a memory management unit (MMU), a digital-to-analog converter (DAC), and the like.

In an embodiment, the PPU 500 may be included on a graphics card that includes one or more memory devices 504. The graphics card may be configured to interface with a PCIe slot on a motherboard of a desktop computer. In yet another embodiment, the PPU 500 may be an integrated graphics processing unit (iGPU) or parallel processor included in the chipset of the motherboard.

Exemplary Computing System

Systems with multiple GPUs and CPUs are used in a variety of industries as developers expose and leverage more parallelism in applications such as artificial intelligence computing. High-performance GPU-accelerated systems with tens to many thousands of compute nodes are deployed in data centers, research facilities, and supercomputers to solve ever larger problems. As the number of processing devices within the high-performance systems increases, the communication and data transfer mechanisms need to scale to support the increased bandwidth.

FIG. 7B is a conceptual diagram of a processing system 700 implemented using the PPU 500 of FIG. 5, in accordance with an embodiment. The exemplary system 765 may be configured to implement the method 300 shown in FIG. 3. The processing system 700 includes a CPU 730, switch 710, and multiple PPUs 500 each and respective memories 504. The NVLink 510 provides high-speed communication links between each of the PPUs 500. Although a particular number of NVLink 510 and interconnect 502 connections are illustrated in FIG. 7B, the number of connections to each PPU 500 and the CPU 730 may vary. The switch 710 interfaces between the interconnect 502 and the CPU 730. The PPUs 500, memories 504, and NVLinks 510 may be situated on a single semiconductor platform to form a parallel processing module 725. In an embodiment, the switch 710 supports two or more protocols to interface between various different connections and/or links.

In another embodiment (not shown), the NVLink 510 provides one or more high-speed communication links between each of the PPUs 500 and the CPU 730 and the switch 710 interfaces between the interconnect 502 and each of the PPUs 500. The PPUs 500, memories 504, and interconnect 502 may be situated on a single semiconductor platform to form a parallel processing module 725. In yet another embodiment (not shown), the interconnect 502 provides one or more communication links between each of the PPUs 500 and the CPU 730 and the switch 710 interfaces between each of the PPUs 500 using the NVLink 510 to provide one or more high-speed communication links between the PPUs 500. In another embodiment (not shown), the NVLink 510 provides one or more high-speed communication links between the PPUs 500 and the CPU 730 through the switch 710. In yet another embodiment (not shown), the interconnect 502 provides one or more communication links between each of the PPUs 500 directly. One or more of the NVLink 510 high-speed communication links may be implemented as a physical NVLink interconnect or either an on-chip or on-die interconnect using the same protocol as the NVLink 510.

In the context of the present description, a single semiconductor platform may refer to a sole unitary semiconductor-based integrated circuit fabricated on a die or chip. It should be noted that the term single semiconductor platform may also refer to multi-chip modules with increased connectivity which simulate on-chip operation and make substantial improvements over utilizing a conventional bus implementation. Of course, the various circuits or devices may also be situated separately or in various combinations of semiconductor platforms per the desires of the user. Alternately, the parallel processing module 725 may be implemented as a circuit board substrate and each of the PPUs 500 and/or memories 504 may be packaged devices. In an embodiment, the CPU 730, switch 710, and the parallel processing module 725 are situated on a single semiconductor platform.

In an embodiment, the signaling rate of each NVLink 510 is 20 to 25 Gigabits/second and each PPU 500 includes six NVLink 510 interfaces (as shown in FIG. 7B, five NVLink 510 interfaces are included for each PPU 500). Each NVLink 510 provides a data transfer rate of 25 Gigabytes/second in each direction, with six links providing 300 Gigabytes/second. The NVLinks 510 can be used exclusively for PPU-to-PPU communication as shown in FIG. 7B, or some combination of PPU-to-PPU and PPU-to-CPU, when the CPU 730 also includes one or more NVLink 510 interfaces.

In an embodiment, the NVLink 510 allows direct load/store/atomic access from the CPU 730 to each PPU's 500 memory 504. In an embodiment, the NVLink 510 supports coherency operations, allowing data read from the memories 504 to be stored in the cache hierarchy of the CPU 730, reducing cache access latency for the CPU 730. In an embodiment, the NVLink 510 includes support for Address Translation Services (ATS), allowing the PPU 500 to directly access page tables within the CPU 730. One or more of the NVLinks 510 may also be configured to operate in a low-power mode.

FIG. 7C illustrates an exemplary system 765 in which the various architecture and/or functionality of the various previous embodiments may be implemented. The exemplary system 765 may be configured to implement the method 300 shown in FIG. 3.

As shown, a system 765 is provided including at least one central processing unit 730 that is connected to a communication bus 775. The communication bus 775 may be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect), PCI-Express, AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol(s). The system 765 also includes a main memory 740. Control logic (software) and data are stored in the main memory 740 which may take the form of random access memory (RAM).

The system 765 also includes input devices 760, the parallel processing system 725, and display devices 745, i.e. a conventional CRT (cathode ray tube), LCD (liquid crystal display), LED (light emitting diode), plasma display or the like. User input may be received from the input devices 760, e.g., keyboard, mouse, touchpad, microphone, and the like. Each of the foregoing modules and/or devices may even be situated on a single semiconductor platform to form the system 765. Alternately, the various modules may also be situated separately or in various combinations of semiconductor platforms per the desires of the user.

Further, the system 765 may be coupled to a network (e.g., a telecommunications network, local area network (LAN), wireless network, wide area network (WAN) such as the Internet, peer-to-peer network, cable network, or the like) through a network interface 735 for communication purposes.

The system 765 may also include a secondary storage (not shown). The secondary storage includes, for example, a hard disk drive and/or a removable storage drive, representing a floppy disk drive, a magnetic tape drive, a compact disk drive, digital versatile disk (DVD) drive, recording device, universal serial bus (USB) flash memory. The removable storage drive reads from and/or writes to a removable storage unit in a well-known manner.

Computer programs, or computer control logic algorithms, may be stored in the main memory 740 and/or the secondary storage. Such computer programs, when executed, enable the system 765 to perform various functions. The memory 740, the storage, and/or any other storage are possible examples of computer-readable media.

The architecture and/or functionality of the various previous figures may be implemented in the context of a general computer system, a circuit board system, a game console system dedicated for entertainment purposes, an application-specific system, and/or any other desired system. For example, the system 765 may take the form of a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smart-phone (e.g., a wireless, hand-held device), personal digital assistant (PDA), a digital camera, a vehicle, a head mounted display, a hand-held electronic device, a mobile phone device, a television, workstation, game consoles, embedded system, and/or any other type of logic.

While various embodiments have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of a preferred embodiment should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Machine Learning

Deep neural networks (DNNs) developed on processors, such as the PPU 500 have been used for diverse use cases, from self-driving cars to faster drug development, from automatic image captioning in online image databases to smart real-time language translation in video chat applications. Deep learning is a technique that models the neural learning process of the human brain, continually learning, continually getting smarter, and delivering more accurate results more quickly over time. A child is initially taught by an adult to correctly identify and classify various shapes, eventually being able to identify shapes without any coaching. Similarly, a deep learning or neural learning system needs to be trained in object recognition and classification for it get smarter and more efficient at identifying basic objects, occluded objects, etc., while also assigning context to objects.

At the simplest level, neurons in the human brain look at various inputs that are received, importance levels are assigned to each of these inputs, and output is passed on to other neurons to act upon. An artificial neuron or perceptron is the most basic model of a neural network. In one example, a perceptron may receive one or more inputs that represent various features of an object that the perceptron is being trained to recognize and classify, and each of these features is assigned a certain weight based on the importance of that feature in defining the shape of an object.

A deep neural network (DNN) model includes multiple layers of many connected perceptrons (e.g., nodes) that can be trained with enormous amounts of input data to quickly solve complex problems with high accuracy. In one example, a first layer of the DLL model breaks down an input image of an automobile into various sections and looks for basic patterns such as lines and angles. The second layer assembles the lines to look for higher level patterns such as wheels, windshields, and mirrors. The next layer identifies the type of vehicle, and the final few layers generate a label for the input image, identifying the model of a specific automobile brand.

Once the DNN is trained, the DNN can be deployed and used to identify and classify objects or patterns in a process known as inference. Examples of inference (the process through which a DNN extracts useful information from a given input) include identifying handwritten numbers on checks deposited into ATM machines, identifying images of friends in photos, delivering movie recommendations to over fifty million users, identifying and classifying different types of automobiles, pedestrians, and road hazards in driverless cars, or translating human speech in real-time.

During training, data flows through the DNN in a forward propagation phase until a prediction is produced that indicates a label corresponding to the input. If the neural network does not correctly label the input, then errors between the correct label and the predicted label are analyzed, and the weights are adjusted for each feature during a backward propagation phase until the DNN correctly labels the input and other inputs in a training dataset. Training complex neural networks requires massive amounts of parallel computing performance, including floating-point multiplications and additions that are supported by the PPU 500. Inferencing is less compute-intensive than training, being a latency-sensitive process where a trained neural network is applied to new inputs it has not seen before to classify images, translate speech, and generally infer new information.

Neural networks rely heavily on matrix math operations, and complex multi-layered networks require tremendous amounts of floating-point performance and bandwidth for both efficiency and speed. With thousands of processing cores, optimized for matrix math operations, and delivering tens to hundreds of TFLOPS of performance, the PPU 500 is a computing platform capable of delivering performance required for deep neural network-based artificial intelligence and machine learning applications.

The disclosure may be described in the general context of computer code or machine-useable instructions, including computer-executable instructions such as program modules, being executed by a computer or other machine, such as a personal data assistant or other handheld device. Generally, program modules including routines, programs, objects, components, data structures, etc., refer to code that perform particular tasks or implement particular abstract data types. The disclosure may be practiced in a variety of system configurations, including hand-held devices, consumer electronics, general-purpose computers, more specialty computing devices, etc. The disclosure may also be practiced in distributed computing environments where tasks are performed by remote-processing devices that are linked through a communications network.

As used herein, a recitation of “and/or” with respect to two or more elements should be interpreted to mean only one element, or a combination of elements. For example, “element A, element B, and/or element C” may include only element A, only element B, only element C, element A and element B, element A and element C, element B and element C, or elements A, B, and C. In addition, “at least one of element A or element B” may include at least one of element A, at least one of element B, or at least one of element A and at least one of element B. Further, “at least one of element A and element B” may include at least one of element A, at least one of element B, or at least one of element A and at least one of element B.

The subject matter of the present disclosure is described with specificity herein to meet statutory requirements. However, the description itself is not intended to limit the scope of this disclosure. Rather, the inventors have contemplated that the claimed subject matter might also be embodied in other ways, to include different steps or combinations of steps similar to the ones described in this document, in conjunction with other present or future technologies. Moreover, although the terms “step” and/or “block” may be used herein to connote different elements of methods employed, the terms should not be interpreted as implying any particular order among or between various steps herein disclosed unless and except when the order of individual steps is explicitly described.

	Number	Date	Country
Parent	17581734	Jan 2022	US
Child	18227241		US

MAPPING LOGICAL AND PHYSICAL PROCESSORS AND LOGICAL AND PHYSICAL MEMORY

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