comprising an array of processing units with common control

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F15/00Digital computers in general Data processing equipment in general

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G06F15/80comprising an array of processing units with common control

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Patents Grantslast 30 patents

Information Patent Grant
Instruction set architecture (ISA) format for multiple instruction...
- Patent number 12,169,719
- Issue date Dec 17, 2024
- MARVELL ASIA PTE. LTD.
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data transfer for non-dot product computations on neural network in...
- Patent number 12,165,043
- Issue date Dec 10, 2024
- Amazon Technologies, Inc.
- Jung Ko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffer splitting
- Patent number 12,164,463
- Issue date Dec 10, 2024
- SambaNova Systems, Inc.
- David Alan Koeplinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accelerated processing via a physically based rendering engine
- Patent number 12,159,344
- Issue date Dec 3, 2024
- NVIDIA Corporation
- Robert A. Alfieri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable logic platform with reconfigurable processing circuitry
- Patent number 12,153,964
- Issue date Nov 26, 2024
- ThroughPuter, Inc.
- Mark Henrik Sandstrom
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for array processor with program packets and associated m...
- Patent number 12,153,542
- Issue date Nov 26, 2024
- Silicon Laboratories Inc.
- Matthew Brandon Gately
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quantum hybrid computation
- Patent number 12,154,002
- Issue date Nov 26, 2024
- IONQ, INC.
- Andrew Maps Ducore
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtualized multicore systems with extended instruction heterogeneity
- Patent number 12,153,540
- Issue date Nov 26, 2024
- Google LLC
- Russell C. McKown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache structure and utilization
- Patent number 12,153,541
- Issue date Nov 26, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for read-modify-write support in multi-banked...
- Patent number 12,147,353
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computational memory with cooperation among rows of processing elem...
- Patent number 12,147,380
- Issue date Nov 19, 2024
- UNTETHER AI CORPORATION
- William Martin Snelgrove
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Schedule-aware dynamically reconfigurable adder tree architecture f...
- Patent number 12,147,836
- Issue date Nov 19, 2024
- Intel Corporation
- Debabrata Mohapatra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cluster-based placement and routing of memory units and compute uni...
- Patent number 12,147,381
- Issue date Nov 19, 2024
- SambaNova Systems, Inc.
- Kin Hing Leung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Operating a multi-dimensional array of qubit devices
- Patent number 12,141,664
- Issue date Nov 12, 2024
- Rigetti & Co, LLC
- Chad Tyler Rigetti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with dynamic allocation of entries
- Patent number 12,141,078
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction set
- Patent number 12,141,092
- Issue date Nov 12, 2024
- GRAPHCORE LIMTIED
- Simon Christian Knowles
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systolic disaggregation within a matrix accelerator architecture
- Patent number 12,141,094
- Issue date Nov 12, 2024
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Calculation circuit and deep learning system including the same
- Patent number 12,141,545
- Issue date Nov 12, 2024
- SK Hynix Inc.
- Ji Hoon Nam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic operations and histogram operations in a cache pipeline
- Patent number 12,141,079
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systolic array, systolic array system, computation method, device,...
- Patent number 12,141,095
- Issue date Nov 12, 2024
- Nanjing SemiDrive Technology LTD.
- Yu Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Avoiding use of a subarray of configurable units having a defect
- Patent number 12,135,971
- Issue date Nov 5, 2024
- SambaNova Systems, Inc.
- Gregory Frederick Grohoski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic processor architecture control
- Patent number 12,135,680
- Issue date Nov 5, 2024
- VSORA
- Khaled Maalej
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coprocessors with bypass optimization, variable grid architecture,...
- Patent number 12,135,681
- Issue date Nov 5, 2024
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fine-grained multithreaded cores executing fused operations in mult...
- Patent number 12,130,744
- Issue date Oct 29, 2024
- Mobileye Vision Technologies Ltd.
- Yosef Kreinin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device and method for accelerating matrix multiply operations
- Patent number 12,124,531
- Issue date Oct 22, 2024
- Advanced Micro Devices, Inc.
- Shaizeen Aga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quick clearing of registers
- Patent number 12,124,728
- Issue date Oct 22, 2024
- Texas Instruments Incorporated
- Timothy David Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
SOC for operating plural NPUS according to plural clock signals hav...
- Patent number 12,117,866
- Issue date Oct 15, 2024
- DEEPX CO., LTD.
- Lok Won Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalar core integration
- Patent number 12,117,962
- Issue date Oct 15, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Networks on chip (NOC) for many-core neural network accelerator
- Patent number 12,117,961
- Issue date Oct 15, 2024
- MOFFETT INTERNATIONAL CO., LIMITED
- Xiaoqian Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
One-dimensional zero padding in a stream of matrix elements
- Patent number 12,118,358
- Issue date Oct 15, 2024
- Texas Instruments Incorporated
- Son Hung Tran
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DIGITAL SIGNAL PROCESSOR (DSP) AND ELECTRONIC DEVICE USING THE SAME
- Publication number 20240419628
- Publication date Dec 19, 2024
- Samsung Electronics Co., Ltd.
- Hyungwoo LEE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLEXIBLE, SCALABLE GRAPH-PROCESSING ACCELERATOR
- Publication number 20240419735
- Publication date Dec 19, 2024
- ADVANCED MICRO DEVICES, INC.
- Ganesh Dasika
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...
- Publication number 20240419607
- Publication date Dec 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SOC AND SYSTEM INCLUDING TWO OR MORE NPUS BEING DISTRIBUTEDLY OPERA...
- Publication number 20240419210
- Publication date Dec 19, 2024
- DEEPX CO., LTD.
- Lok Won KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS FOR ACCELERATING NEURAL NETWORKS
- Publication number 20240419494
- Publication date Dec 19, 2024
- University-Industry Foundation, Yonsei University
- Youngsok KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL EXECUTION OF SELF-ATTENTION-BASED AI MODELS
- Publication number 20240419516
- Publication date Dec 19, 2024
- Etched.ai, Inc.
- Gavin UBERTI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE STRUCTURE AND UTILIZATION
- Publication number 20240411717
- Publication date Dec 12, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE-BASED IMAGE/VIDEO PROCESSING IN MACHINE LEARNING-ACCELERAT...
- Publication number 20240411718
- Publication date Dec 12, 2024
- QUALCOMM Incorporated
- Sandeep PANDE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSION TECHNIQUES
- Publication number 20240403259
- Publication date Dec 5, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM OF TRAINING DEEP LEARNING MODEL, DEVICE, AND MEDIUM
- Publication number 20240394190
- Publication date Nov 28, 2024
- BEIJING BAIDU NETCOM SCIENCE TECHNOLOGY CO., LTD.
- Minxu ZHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE MULTITHREADED PROCESSORS WITH SHARED DATA CACHE
- Publication number 20240394191
- Publication date Nov 28, 2024
- MOBILEYE VISION TECHNOLOGIES LTD.
- Yosef Kreinin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD TO RESET CONFIGURABLE UNITS IN A RECONFIGURABLE PROCESSOR
- Publication number 20240385929
- Publication date Nov 21, 2024
- SambaNova Systems, Inc.
- Manish K. SHAH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
A computer-implemented or hardware-implemented method, a computer p...
- Publication number 20240385987
- Publication date Nov 21, 2024
- IntuiCell AB
- Henrik Jörntell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-CHIP SYSTOLIC ARRAYS
- Publication number 20240378175
- Publication date Nov 14, 2024
- Etched.ai, Inc.
- Gavin UBERTI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Configuration Data Store in a Reconfigurable Data Processor Having...
- Publication number 20240370402
- Publication date Nov 7, 2024
- SambaNova Systems, Inc.
- Manish K. SHAH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...
- Publication number 20240370380
- Publication date Nov 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC PROCESSING MEMORY CORE ON A SINGLE MEMORY CHIP
- Publication number 20240370401
- Publication date Nov 7, 2024
- X-Silicon, Inc.
- Atif Zafar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES TO CONTROL SYSTEM UPDATES AND CONFIGURATION CHANGES VIA...
- Publication number 20240372792
- Publication date Nov 7, 2024
- Intel Corporation
- MURUGASAMY K. NACHIMUTHU
- B25 - HAND TOOLS PORTABLE POWER-DRIVEN TOOLS MANIPULATORS
Information Patent Application
Systolic Memory Access
- Publication number 20240370403
- Publication date Nov 7, 2024
- Micron Technology, Inc.
- Febin Sunny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COLLECTIVE COMMUNICATION METHOD AND APPARATUS
- Publication number 20240362082
- Publication date Oct 31, 2024
- Huawei Technologies Co., Ltd
- Tianchi HU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...
- Publication number 20240362180
- Publication date Oct 31, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTOLIC ARRAY INCLUDING FUSED MULTIPLY ACCUMULATE WITH EFFICIENT P...
- Publication number 20240361986
- Publication date Oct 31, 2024
- AMAZON TECHNOLOGIES, INC.
- Thomas Elmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW LATENCY MATRIX MULTIPLY UNIT
- Publication number 20240362298
- Publication date Oct 31, 2024
- Google LLC
- Andrew Everett Phelps
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTING ARRAY USING GLOBAL NODE PROCESSING
- Publication number 20240354280
- Publication date Oct 24, 2024
- International Microsystems Inc.
- Peter Arthur Schade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-tile Memory Management for Detecting Cross Tile Access Provid...
- Publication number 20240345990
- Publication date Oct 17, 2024
- Intel Corporation
- Lakshminarayanan Striramassarma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FREQUENCY PATTERN FOR REDUCING PARASITIC INTERACTIONS IN A QUBIT GRID
- Publication number 20240346359
- Publication date Oct 17, 2024
- Google LLC
- John Martinis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NETWORKS ON CHIP (NOC) FOR MANY-CORE NEURAL NETWORK ACCELERATOR
- Publication number 20240338338
- Publication date Oct 10, 2024
- MOFFETT INTERNATIONAL CO., LIMITED
- Xiaoqian ZHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTELLIGENT GRAPH EXECUTION AND ORCHESTRATION ENGINE FOR A RECONFIG...
- Publication number 20240338340
- Publication date Oct 10, 2024
- SambaNova Systems, Inc.
- Arnav GOEL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTEXT LOAD MECHANISM IN A COARSE-GRAINED RECONFIGURABLE ARRAY PRO...
- Publication number 20240330237
- Publication date Oct 3, 2024
- Micron Technology, Inc.
- Bryan Hornung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UTILIZING STRUCTURED SPARSITY IN SYSTOLIC ARRAYS
- Publication number 20240320000
- Publication date Sep 26, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING

comprising an array of processing units with common control

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Instruction set architecture (ISA) format for multiple instruction...

Data transfer for non-dot product computations on neural network in...

Buffer splitting

Accelerated processing via a physically based rendering engine

Configurable logic platform with reconfigurable processing circuitry

Apparatus for array processor with program packets and associated m...

Quantum hybrid computation

Virtualized multicore systems with extended instruction heterogeneity

Cache structure and utilization

Methods and apparatus for read-modify-write support in multi-banked...

Computational memory with cooperation among rows of processing elem...

Schedule-aware dynamically reconfigurable adder tree architecture f...

Cluster-based placement and routing of memory units and compute uni...

Operating a multi-dimensional array of qubit devices

Victim cache with dynamic allocation of entries

Instruction set

Systolic disaggregation within a matrix accelerator architecture

Calculation circuit and deep learning system including the same

Atomic operations and histogram operations in a cache pipeline

Systolic array, systolic array system, computation method, device,...

Avoiding use of a subarray of configurable units having a defect

Dynamic processor architecture control

Coprocessors with bypass optimization, variable grid architecture,...

Fine-grained multithreaded cores executing fused operations in mult...

Device and method for accelerating matrix multiply operations

Quick clearing of registers

SOC for operating plural NPUS according to plural clock signals hav...

Scalar core integration

Networks on chip (NOC) for many-core neural network accelerator

One-dimensional zero padding in a stream of matrix elements

Patents Applicationslast 30 patents

DIGITAL SIGNAL PROCESSOR (DSP) AND ELECTRONIC DEVICE USING THE SAME

FLEXIBLE, SCALABLE GRAPH-PROCESSING ACCELERATOR

METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...

SOC AND SYSTEM INCLUDING TWO OR MORE NPUS BEING DISTRIBUTEDLY OPERA...

APPARATUS FOR ACCELERATING NEURAL NETWORKS

PARALLEL EXECUTION OF SELF-ATTENTION-BASED AI MODELS

CACHE STRUCTURE AND UTILIZATION

HARDWARE-BASED IMAGE/VIDEO PROCESSING IN MACHINE LEARNING-ACCELERAT...

COMPRESSION TECHNIQUES

METHOD AND SYSTEM OF TRAINING DEEP LEARNING MODEL, DEVICE, AND MEDIUM

MULTIPLE MULTITHREADED PROCESSORS WITH SHARED DATA CACHE

METHOD TO RESET CONFIGURABLE UNITS IN A RECONFIGURABLE PROCESSOR

A computer-implemented or hardware-implemented method, a computer p...

MULTI-CHIP SYSTOLIC ARRAYS

Configuration Data Store in a Reconfigurable Data Processor Having...

METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...

DYNAMIC PROCESSING MEMORY CORE ON A SINGLE MEMORY CHIP

TECHNIQUES TO CONTROL SYSTEM UPDATES AND CONFIGURATION CHANGES VIA...

Systolic Memory Access

COLLECTIVE COMMUNICATION METHOD AND APPARATUS

GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...

SYSTOLIC ARRAY INCLUDING FUSED MULTIPLY ACCUMULATE WITH EFFICIENT P...

LOW LATENCY MATRIX MULTIPLY UNIT

COMPUTING ARRAY USING GLOBAL NODE PROCESSING

Multi-tile Memory Management for Detecting Cross Tile Access Provid...

FREQUENCY PATTERN FOR REDUCING PARASITIC INTERACTIONS IN A QUBIT GRID

NETWORKS ON CHIP (NOC) FOR MANY-CORE NEURAL NETWORK ACCELERATOR

INTELLIGENT GRAPH EXECUTION AND ORCHESTRATION ENGINE FOR A RECONFIG...

CONTEXT LOAD MECHANISM IN A COARSE-GRAINED RECONFIGURABLE ARRAY PRO...

UTILIZING STRUCTURED SPARSITY IN SYSTOLIC ARRAYS