comprising an array of processing units with common control

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G06F15/80

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F15/00Digital computers in general Data processing equipment in general

Current Industry

G06F15/80comprising an array of processing units with common control

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Hybrid victim cache and write miss buffer with fence operation
- Patent number 12,265,477
- Issue date Apr 1, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Forming constant extensions in the same execute packet in a VLIW pr...
- Patent number 12,265,827
- Issue date Apr 1, 2025
- Texas Instruments Incorporated
- Timothy David Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for multi-banked victim cache with dual datapath
- Patent number 12,259,826
- Issue date Mar 25, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technologies for offloading acceleration task scheduling operations...
- Patent number 12,260,257
- Issue date Mar 25, 2025
- Intel Corporation
- Susanne M. Balle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for performing multiplication of one or more ma...
- Patent number 12,260,248
- Issue date Mar 25, 2025
- Huawei Technologies Co., Ltd.
- Tal Horowitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout-based data transfer between synchronized, interconnected pro...
- Patent number 12,260,253
- Issue date Mar 25, 2025
- SiMa Technologies, Inc.
- Gwangho Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Game engine on a chip
- Patent number 12,249,018
- Issue date Mar 11, 2025
- TMRW FOUNDATION IP S.ÀR.L.
- Cevat Yerli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible, scalable graph-processing accelerator
- Patent number 12,248,516
- Issue date Mar 11, 2025
- Advanced Micro Devices, Inc.
- Ganesh Dasika
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systolic neural CPU processor
- Patent number 12,242,416
- Issue date Mar 4, 2025
- Northwestern University
- Jie Gu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data initialization techniques
- Patent number 12,242,414
- Issue date Mar 4, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-core processor, multi-core processor processing method, and r...
- Patent number 12,242,415
- Issue date Mar 4, 2025
- Huawei Technologies Co., Ltd.
- Guozhu Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing apparatus with selectively delayed transmission of...
- Patent number 12,236,241
- Issue date Feb 25, 2025
- ARM Limited
- Xiaoyang Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable spatial array for matrix decomposition
- Patent number 12,235,793
- Issue date Feb 25, 2025
- Intel Corporation
- Long Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Block data load with transpose into memory
- Patent number 12,229,570
- Issue date Feb 18, 2025
- Advanced Micro Devices, Inc.
- Bin He
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for deep learning network execution pipeline...
- Patent number 12,229,569
- Issue date Feb 18, 2025
- Intel Corporation
- Liu Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processor with non-blocking concurrent architecture
- Patent number 12,229,865
- Issue date Feb 18, 2025
- Imagination Technologies Limited
- Luke T Peterson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for synchronization of multi-thread lanes
- Patent number 12,223,353
- Issue date Feb 11, 2025
- Intel Corporation
- Valentin Andrei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computational array microprocessor system using non-consecutive dat...
- Patent number 12,216,610
- Issue date Feb 4, 2025
- Tesla, Inc.
- Emil Talpes
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Application specific integrated circuit accelerators
- Patent number 12,218,666
- Issue date Feb 4, 2025
- Google LLC
- Michial Allen Gunter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-power, high-performance artificial neural network training acce...
- Patent number 12,217,184
- Issue date Feb 4, 2025
- Korea Advanced Institute of Science and Technology
- Hoi Jun Yoo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic compare and swap in a coherent cache system
- Patent number 12,216,591
- Issue date Feb 4, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for improving cache efficiency and utilization
- Patent number 12,210,477
- Issue date Jan 28, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Aggressive write flush scheme for a victim cache
- Patent number 12,210,463
- Issue date Jan 28, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems configured to specify resources for hyperdimens...
- Patent number 12,210,945
- Issue date Jan 28, 2025
- The Regents of the University of California
- Sahand Salamat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processor data access and sharing
- Patent number 12,204,487
- Issue date Jan 21, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System having a hybrid threading processor, a hybrid threading fabr...
- Patent number 12,204,363
- Issue date Jan 21, 2025
- Micron Technology, Inc.
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiplier and adder in systolic array
- Patent number 12,197,890
- Issue date Jan 14, 2025
- Google LLC
- Doe Hyun Yoon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to reduce bank pressure using aggressive writ...
- Patent number 12,197,347
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing system with interspersed processors DMA-FIFO
- Patent number 12,197,970
- Issue date Jan 14, 2025
- HyperX Logic, Inc.
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture for block sparse operations on a systolic array
- Patent number 12,198,222
- Issue date Jan 14, 2025
- Intel Corporation
- Abhishek Appu
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DUAL PIPELINE PARALLEL SYSTOLIC ARRAY
- Publication number 20250117359
- Publication date Apr 10, 2025
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTOLIC ARRAY OF ARBITRARY PHYSICAL AND LOGICAL DEPTH
- Publication number 20250117360
- Publication date Apr 10, 2025
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS DMA-FIFO
- Publication number 20250117271
- Publication date Apr 10, 2025
- HyperX Logic, Inc.
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECONFIGURABLE ARITHMETIC ENGINE CIRCUIT
- Publication number 20250117357
- Publication date Apr 10, 2025
- Cornami, Inc.
- Raymond J. Andraka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM
- Publication number 20250117340
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE MEMORY MANAGEMENT
- Publication number 20250117356
- Publication date Apr 10, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM
- Publication number 20250117341
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Heterogenous Acceleration of Workloads using xPUs and FPGAs
- Publication number 20250117358
- Publication date Apr 10, 2025
- Nicolas Tausanovitch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONVOLUTION OPERATIONS WITH IN-MEMORY COMPUTING
- Publication number 20250117441
- Publication date Apr 10, 2025
- Rain Neuromorphics Inc.
- Nawab Ali
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR HAVING MULTIPLE CORES, SHARED CORE EXTENSION LOGIC, AND S...
- Publication number 20250110737
- Publication date Apr 3, 2025
- Intel Corporation
- Eran SHIFER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION
- Publication number 20250103548
- Publication date Mar 27, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interleave Execution Circuit
- Publication number 20250103551
- Publication date Mar 27, 2025
- Apple Inc.
- Kanghong Yan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE STRUCTURE AND UTILIZATION
- Publication number 20250103546
- Publication date Mar 27, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY
- Publication number 20250104180
- Publication date Mar 27, 2025
- Intel Corporation
- Abhishek Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE
- Publication number 20250103547
- Publication date Mar 27, 2025
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUS FOR TRANSPORTING OUTPUT VALUES OF NEURAL NETWORK LAYER
- Publication number 20250103341
- Publication date Mar 27, 2025
- AMAZON TECHNOLOGIES, INC.
- Kenneth Duong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXECUTION UNIT SHARING BETWEEN PROCESSING CORES IN A CLUSTER OF A S...
- Publication number 20250103545
- Publication date Mar 27, 2025
- QUALCOMM Incorporated
- Hithesh Hassan LEPAKSHA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR INSTRUCTION DISPATCH CONFIGURATION
- Publication number 20250094220
- Publication date Mar 20, 2025
- Groq, Inc.
- Brian Lee Kurtz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FULLY PIPELINED READ-MODIFY-WRITE SUPPORT
- Publication number 20250094359
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPER SYSTEM ON CHIP
- Publication number 20250094380
- Publication date Mar 20, 2025
- Mohammad A. Mazed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...
- Publication number 20250094358
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Coprocessors with Bypass Optimization, Variable Grid Architecture,...
- Publication number 20250094381
- Publication date Mar 20, 2025
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NEURAL NETWORK PROCESSOR CAPABLE OF REUSING MEMORY ADDRESS VALUE
- Publication number 20250077277
- Publication date Mar 6, 2025
- DEEPX CO., LTD.
- Lok Won KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Buffer Splitting Based on Cost
- Publication number 20250068587
- Publication date Feb 27, 2025
- SambaNova Systems, Inc.
- David Alan KOEPLINGER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT PROCESSING ON A DUAL CORE PROCESSING SYSTEM
- Publication number 20250068585
- Publication date Feb 27, 2025
- Cirrus Logic International Semiconductor Ltd.
- Trenton HENRY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NPU, SOC AND ELECTRONIC DEVICE FOR CONTROLLING PEAK POWER BY DIVIDI...
- Publication number 20250068586
- Publication date Feb 27, 2025
- DEEPX CO., LTD.
- Lok Won KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALAR CORE INTEGRATION
- Publication number 20250068588
- Publication date Feb 27, 2025
- Intel Corporation
- JOYDEEP RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TASK EXECUTION IN A SIMD PROCESSING UNIT WITH PARALLEL GROUPS OF PR...
- Publication number 20250061536
- Publication date Feb 20, 2025
- Imagination Technologies Limited
- John Howson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RANDOM SPARSITY HANDLING IN A SYSTOLIC ARRAY
- Publication number 20250053613
- Publication date Feb 13, 2025
- Intel Corporation
- Chunhui Mei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MESSAGE CHANNELS
- Publication number 20250053465
- Publication date Feb 13, 2025
- ARM Limited
- Jonathan Curtis BEARD
- G06 - COMPUTING CALCULATING COUNTING

comprising an array of processing units with common control

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Hybrid victim cache and write miss buffer with fence operation

Forming constant extensions in the same execute packet in a VLIW pr...

Methods and apparatus for multi-banked victim cache with dual datapath

Technologies for offloading acceleration task scheduling operations...

Systems and methods for performing multiplication of one or more ma...

Layout-based data transfer between synchronized, interconnected pro...

Game engine on a chip

Flexible, scalable graph-processing accelerator

Systolic neural CPU processor

Data initialization techniques

Multi-core processor, multi-core processor processing method, and r...

Data processing apparatus with selectively delayed transmission of...

Programmable spatial array for matrix decomposition

Block data load with transpose into memory

Methods and apparatus for deep learning network execution pipeline...

Graphics processor with non-blocking concurrent architecture

Systems and methods for synchronization of multi-thread lanes

Computational array microprocessor system using non-consecutive dat...

Application specific integrated circuit accelerators

Low-power, high-performance artificial neural network training acce...

Atomic compare and swap in a coherent cache system

Systems and methods for improving cache efficiency and utilization

Aggressive write flush scheme for a victim cache

Methods and systems configured to specify resources for hyperdimens...

Graphics processor data access and sharing

System having a hybrid threading processor, a hybrid threading fabr...

Multiplier and adder in systolic array

Methods and apparatus to reduce bank pressure using aggressive writ...

Processing system with interspersed processors DMA-FIFO

Architecture for block sparse operations on a systolic array

Patents Applicationslast 30 patents

DUAL PIPELINE PARALLEL SYSTOLIC ARRAY

SYSTOLIC ARRAY OF ARBITRARY PHYSICAL AND LOGICAL DEPTH

PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS DMA-FIFO

RECONFIGURABLE ARITHMETIC ENGINE CIRCUIT

ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM

MULTI-TILE MEMORY MANAGEMENT

METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM

Heterogenous Acceleration of Workloads using xPUs and FPGAs

CONVOLUTION OPERATIONS WITH IN-MEMORY COMPUTING

PROCESSOR HAVING MULTIPLE CORES, SHARED CORE EXTENSION LOGIC, AND S...

SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION

Interleave Execution Circuit

CACHE STRUCTURE AND UTILIZATION

ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY

SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE

BUS FOR TRANSPORTING OUTPUT VALUES OF NEURAL NETWORK LAYER

EXECUTION UNIT SHARING BETWEEN PROCESSING CORES IN A CLUSTER OF A S...

PROCESSOR INSTRUCTION DISPATCH CONFIGURATION

FULLY PIPELINED READ-MODIFY-WRITE SUPPORT

SUPER SYSTEM ON CHIP

METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...

Coprocessors with Bypass Optimization, Variable Grid Architecture,...

NEURAL NETWORK PROCESSOR CAPABLE OF REUSING MEMORY ADDRESS VALUE

Buffer Splitting Based on Cost

EFFICIENT PROCESSING ON A DUAL CORE PROCESSING SYSTEM

NPU, SOC AND ELECTRONIC DEVICE FOR CONTROLLING PEAK POWER BY DIVIDI...

SCALAR CORE INTEGRATION

TASK EXECUTION IN A SIMD PROCESSING UNIT WITH PARALLEL GROUPS OF PR...

RANDOM SPARSITY HANDLING IN A SYSTOLIC ARRAY

MESSAGE CHANNELS