comprising an array of processing units with common control

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G06F15/80

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F15/00Digital computers in general Data processing equipment in general

Current Industry

G06F15/80comprising an array of processing units with common control

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Systems and methods for synchronization of multi-thread lanes
- Patent number 12,223,353
- Issue date Feb 11, 2025
- Intel Corporation
- Valentin Andrei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computational array microprocessor system using non-consecutive dat...
- Patent number 12,216,610
- Issue date Feb 4, 2025
- Tesla, Inc.
- Emil Talpes
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Application specific integrated circuit accelerators
- Patent number 12,218,666
- Issue date Feb 4, 2025
- Google LLC
- Michial Allen Gunter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic compare and swap in a coherent cache system
- Patent number 12,216,591
- Issue date Feb 4, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-power, high-performance artificial neural network training acce...
- Patent number 12,217,184
- Issue date Feb 4, 2025
- Korea Advanced Institute of Science and Technology
- Hoi Jun Yoo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for improving cache efficiency and utilization
- Patent number 12,210,477
- Issue date Jan 28, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Aggressive write flush scheme for a victim cache
- Patent number 12,210,463
- Issue date Jan 28, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems configured to specify resources for hyperdimens...
- Patent number 12,210,945
- Issue date Jan 28, 2025
- The Regents of the University of California
- Sahand Salamat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processor data access and sharing
- Patent number 12,204,487
- Issue date Jan 21, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System having a hybrid threading processor, a hybrid threading fabr...
- Patent number 12,204,363
- Issue date Jan 21, 2025
- Micron Technology, Inc.
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiplier and adder in systolic array
- Patent number 12,197,890
- Issue date Jan 14, 2025
- Google LLC
- Doe Hyun Yoon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to reduce bank pressure using aggressive writ...
- Patent number 12,197,347
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing system with interspersed processors DMA-FIFO
- Patent number 12,197,970
- Issue date Jan 14, 2025
- HyperX Logic, Inc.
- Carl S. Dobbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for multiplying matrices using a plurality of chiplets
- Patent number 12,197,534
- Issue date Jan 14, 2025
- Persimmons, Inc.
- James Michael Bodwin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-circuit utilization monitoring for a systolic array
- Patent number 12,197,308
- Issue date Jan 14, 2025
- Amazon Technologies, Inc.
- Thomas A Volpe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture for block sparse operations on a systolic array
- Patent number 12,198,222
- Issue date Jan 14, 2025
- Intel Corporation
- Abhishek Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual pipeline parallel systolic array
- Patent number 12,189,571
- Issue date Jan 7, 2025
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing elements array that includes delay queues between proces...
- Patent number 12,190,224
- Issue date Jan 7, 2025
- Industrial Technology Research Institute
- Yao-Hua Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error checking for systolic array computation
- Patent number 12,189,472
- Issue date Jan 7, 2025
- Google LLC
- Doe Hyun Yoon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fracturable data path in a reconfigurable data processor
- Patent number 12,190,084
- Issue date Jan 7, 2025
- SambaNova Systems, Inc.
- Raghu Prabhakar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using sparsity metadata to reduce systolic array power consumption
- Patent number 12,190,158
- Issue date Jan 7, 2025
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fully pipelined read-modify-write support
- Patent number 12,189,540
- Issue date Jan 7, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technologies for dynamically managing resources in disaggregated ac...
- Patent number 12,191,987
- Issue date Jan 7, 2025
- Intel Corporation
- Francesc Guim Bernat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile memory management
- Patent number 12,182,062
- Issue date Dec 31, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for allocation in a victim cache system
- Patent number 12,182,038
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Neural-processing unit tile for shuffling queued nibbles for multip...
- Patent number 12,182,577
- Issue date Dec 31, 2024
- Samsung Electronics Co., Ltd.
- Ilia Ovsiannikov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfigurable arithmetic engine circuit
- Patent number 12,182,063
- Issue date Dec 31, 2024
- Cornami, Inc.
- Raymond J. Andraka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple accumulate busses in a systolic array
- Patent number 12,182,064
- Issue date Dec 31, 2024
- Amazon Technologies, Inc.
- Thomas A Volpe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus, and computer-readable medium for parallelization...
- Patent number 12,174,784
- Issue date Dec 24, 2024
- Cornami, Inc.
- Solomon Harsha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor instruction dispatch configuration
- Patent number 12,175,287
- Issue date Dec 24, 2024
- Groq, Inc.
- Brian Lee Kurtz
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
RANDOM SPARSITY HANDLING IN A SYSTOLIC ARRAY
- Publication number 20250053613
- Publication date Feb 13, 2025
- Intel Corporation
- Chunhui Mei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MESSAGE CHANNELS
- Publication number 20250053465
- Publication date Feb 13, 2025
- ARM Limited
- Jonathan Curtis BEARD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and Processes for Data Reshape and Transport Using Matrix P...
- Publication number 20250053614
- Publication date Feb 13, 2025
- Expedera, Inc.
- Ramteja Tadishetti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QUICK CLEARING OF REGISTERS
- Publication number 20250044975
- Publication date Feb 6, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Timothy David ANDERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cluster-Based Placement and Routing of Memory Units and Compute Uni...
- Publication number 20250045241
- Publication date Feb 6, 2025
- SambaNova Systems, Inc.
- Kin Hing LEUNG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPROXIMATE COMPUTING BASED TENSOR PROCESSING UNIT (APTPU)
- Publication number 20250045240
- Publication date Feb 6, 2025
- University of South Carolina
- Mohammed Elbtity
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...
- Publication number 20250036573
- Publication date Jan 30, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PADDING IN A STREAM OF MATRIX ELEMENTS
- Publication number 20250036411
- Publication date Jan 30, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Son Hung Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTATIONAL MEMORY WITH COOPERATION AMONG ROWS OF PROCESSING ELEM...
- Publication number 20250036592
- Publication date Jan 30, 2025
- UNTETHER AI CORPORATION
- William Martin SNELGROVE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY
- Publication number 20250028675
- Publication date Jan 23, 2025
- Intel Corporation
- JOYDEEP RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NETWORKS ON CHIP (NOC) FOR MANY-CORE NEURAL NETWORK ACCELERATOR
- Publication number 20250028673
- Publication date Jan 23, 2025
- MOFFETT INTERNATIONAL CO., LIMITED
- Xiaoqian ZHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES
- Publication number 20250028652
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reconfigurable Processing Element for a Systolic Array
- Publication number 20250028785
- Publication date Jan 23, 2025
- SambaNova Systems, Inc.
- Mark William Gottscho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE
- Publication number 20250028651
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTED GRAPHICS PROCESSOR UNIT ARCHITECTURE
- Publication number 20250028676
- Publication date Jan 23, 2025
- Micron Technology, Inc.
- Dmitri Yudanov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCHEDULE-AWARE DYNAMICALLY RECONFIGURABLE ADDER TREE ARCHITECTURE F...
- Publication number 20250028565
- Publication date Jan 23, 2025
- Intel Corporation
- Debabrata Mohapatra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SINGLE INSTRUCTION MULTIPLE DISPATCHES FOR SHORT KERNELS IN A RECON...
- Publication number 20250021516
- Publication date Jan 16, 2025
- AzurEngine Technologies Zhuhai Inc.
- Toshio Nagata
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VECTORIZED SCALAR PROCESSOR FOR EXECUTING SCALAR INSTRUCTIONS IN MU...
- Publication number 20250021376
- Publication date Jan 16, 2025
- AzurEngine Technologies Zhuhai Inc.
- Toshio Nagata
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE SUPPORTED MULTIPLY-ACCUMULATE (MAC) OPERATION IN A RECONFI...
- Publication number 20250021306
- Publication date Jan 16, 2025
- AzurEngine Technologies Zhuhai Inc.
- Toshio Nagata
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-HOMOGENEOUS CHIPLETS
- Publication number 20250004982
- Publication date Jan 2, 2025
- ADVANCED MICRO DEVICES, INC.
- Matthaeus G. Chajdas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TILED COMPUTE AND PROGRAMMABLE LOGIC ARRAY
- Publication number 20250004983
- Publication date Jan 2, 2025
- Xilinx, Inc.
- Brian C. GAIDE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO ESTIMATE CARDINALITY OF USERS REPRESENTED...
- Publication number 20250005008
- Publication date Jan 2, 2025
- The Nielsen Company (US), LLC
- Michael Sheppard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PROCESSING METHOD, APPARATUS AND DEVICE, AND STORAGE MEDIUM
- Publication number 20250005103
- Publication date Jan 2, 2025
- HYGON INFORMATION TECHNOLOGY CO., LTD.
- Qing CHEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE MEMORY MANAGEMENT
- Publication number 20250004981
- Publication date Jan 2, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO ATOMICALLY STORE...
- Publication number 20240427728
- Publication date Dec 26, 2024
- Intel Corporation
- Vedvyas Shanbhogue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VECTOR COMPUTATIONAL UNIT
- Publication number 20240427729
- Publication date Dec 26, 2024
- Tesla, Inc.
- Debjit Das Sarma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS...
- Publication number 20240427847
- Publication date Dec 26, 2024
- Intel Corporation
- SUBRAMANIAM MAIYURAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIGITAL SIGNAL PROCESSOR (DSP) AND ELECTRONIC DEVICE USING THE SAME
- Publication number 20240419628
- Publication date Dec 19, 2024
- Samsung Electronics Co., Ltd.
- Hyungwoo LEE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLEXIBLE, SCALABLE GRAPH-PROCESSING ACCELERATOR
- Publication number 20240419735
- Publication date Dec 19, 2024
- ADVANCED MICRO DEVICES, INC.
- Ganesh Dasika
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...
- Publication number 20240419607
- Publication date Dec 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING

comprising an array of processing units with common control

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Systems and methods for synchronization of multi-thread lanes

Computational array microprocessor system using non-consecutive dat...

Application specific integrated circuit accelerators

Atomic compare and swap in a coherent cache system

Low-power, high-performance artificial neural network training acce...

Systems and methods for improving cache efficiency and utilization

Aggressive write flush scheme for a victim cache

Methods and systems configured to specify resources for hyperdimens...

Graphics processor data access and sharing

System having a hybrid threading processor, a hybrid threading fabr...

Multiplier and adder in systolic array

Methods and apparatus to reduce bank pressure using aggressive writ...

Processing system with interspersed processors DMA-FIFO

Methods for multiplying matrices using a plurality of chiplets

On-circuit utilization monitoring for a systolic array

Architecture for block sparse operations on a systolic array

Dual pipeline parallel systolic array

Processing elements array that includes delay queues between proces...

Error checking for systolic array computation

Fracturable data path in a reconfigurable data processor

Using sparsity metadata to reduce systolic array power consumption

Fully pipelined read-modify-write support

Technologies for dynamically managing resources in disaggregated ac...

Multi-tile memory management

Methods and apparatus for allocation in a victim cache system

Neural-processing unit tile for shuffling queued nibbles for multip...

Reconfigurable arithmetic engine circuit

Multiple accumulate busses in a systolic array

Method, apparatus, and computer-readable medium for parallelization...

Processor instruction dispatch configuration

Patents Applicationslast 30 patents

RANDOM SPARSITY HANDLING IN A SYSTOLIC ARRAY

MESSAGE CHANNELS

Systems and Processes for Data Reshape and Transport Using Matrix P...

QUICK CLEARING OF REGISTERS

Cluster-Based Placement and Routing of Memory Units and Compute Uni...

APPROXIMATE COMPUTING BASED TENSOR PROCESSING UNIT (APTPU)

METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...

PADDING IN A STREAM OF MATRIX ELEMENTS

COMPUTATIONAL MEMORY WITH COOPERATION AMONG ROWS OF PROCESSING ELEM...

GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY

NETWORKS ON CHIP (NOC) FOR MANY-CORE NEURAL NETWORK ACCELERATOR

VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES

Reconfigurable Processing Element for a Systolic Array

ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE

DISTRIBUTED GRAPHICS PROCESSOR UNIT ARCHITECTURE

SCHEDULE-AWARE DYNAMICALLY RECONFIGURABLE ADDER TREE ARCHITECTURE F...

SINGLE INSTRUCTION MULTIPLE DISPATCHES FOR SHORT KERNELS IN A RECON...

VECTORIZED SCALAR PROCESSOR FOR EXECUTING SCALAR INSTRUCTIONS IN MU...

HARDWARE SUPPORTED MULTIPLY-ACCUMULATE (MAC) OPERATION IN A RECONFI...

NON-HOMOGENEOUS CHIPLETS

TILED COMPUTE AND PROGRAMMABLE LOGIC ARRAY

METHODS AND APPARATUS TO ESTIMATE CARDINALITY OF USERS REPRESENTED...

DATA PROCESSING METHOD, APPARATUS AND DEVICE, AND STORAGE MEDIUM

MULTI-TILE MEMORY MANAGEMENT

PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO ATOMICALLY STORE...

VECTOR COMPUTATIONAL UNIT

SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS...

DIGITAL SIGNAL PROCESSOR (DSP) AND ELECTRONIC DEVICE USING THE SAME

FLEXIBLE, SCALABLE GRAPH-PROCESSING ACCELERATOR

METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...