comprising an array of processing units with common control

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G06F15/80

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F15/00Digital computers in general Data processing equipment in general

Current Industry

G06F15/80comprising an array of processing units with common control

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Vectorized scalar processor for executing scalar instructions in mu...
- Patent number 12,360,805
- Issue date Jul 15, 2025
- AzurEngine Technologies Zhuhai Inc.
- Toshio Nagata
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coalescing adjacent gather/scatter operations
- Patent number 12,360,774
- Issue date Jul 15, 2025
- Intel Corporation
- Andrew T. Forsyth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Discrete three-dimensional processor
- Patent number 12,355,023
- Issue date Jul 8, 2025
- Hong Kong HaiCun Technology Co., Limited
- Guobiao Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device including array of processor elements and meth...
- Patent number 12,353,343
- Issue date Jul 8, 2025
- Renesas Electronics Corporation
- Taro Fujii
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two-dimensional processing array with a vertically stacked memory t...
- Patent number 12,346,286
- Issue date Jul 1, 2025
- ALIBABA (CHINA) CO., LTD.
- Shuangchen Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accelerated polynomial coding system and method
- Patent number 12,341,532
- Issue date Jun 24, 2025
- STREAMSCALE, INC.
- Michael H. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Neural network accelerators
- Patent number 12,333,415
- Issue date Jun 17, 2025
- Hewlett Packard Enterprise Development LP
- Vaithyalingam Nagendran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sorting the nodes of an operation unit graph for implementation in...
- Patent number 12,332,837
- Issue date Jun 17, 2025
- SambaNova Systems, Inc.
- Hong Suh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rotating data for neural network computations
- Patent number 12,333,417
- Issue date Jun 17, 2025
- Google LLC
- Jonathan Ross
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing cores and information transfer circuits arranged in matrix
- Patent number 12,327,114
- Issue date Jun 10, 2025
- PREFERRED NETWORKS, INC.
- Tanvir Ahmed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for accelerating neural networks
- Patent number 12,327,139
- Issue date Jun 10, 2025
- UNIVERSITY-INDUSTRY FOUNDATION, YONSEI UNIVERSITY
- Youngsok Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate atomic operations in victim cache
- Patent number 12,321,284
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implicit fence for write messages
- Patent number 12,321,310
- Issue date Jun 3, 2025
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with write miss merging
- Patent number 12,321,285
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple contexts for a compute unit in a reconfigurable data proce...
- Patent number 12,314,754
- Issue date May 27, 2025
- SambaNova Systems, Inc.
- Raghu Prabhakar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-memory on-chip computational network
- Patent number 12,314,837
- Issue date May 27, 2025
- Amazon Technologies, Inc.
- Randy Huang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital pre-distortion (DPD) adaptation using a hybrid hardware acc...
- Patent number 12,314,216
- Issue date May 27, 2025
- Intel Corporation
- Zoran Zivkovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid hardware accelerator and programmable array architecture
- Patent number 12,314,217
- Issue date May 27, 2025
- Intel Corporation
- Zoran Zivkovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfigurable dataflow unit with streaming write functionality
- Patent number 12,306,788
- Issue date May 20, 2025
- SambaNova Systems, Inc.
- Manish K. Shah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Message based processor with transmission disabling mode
- Patent number 12,298,933
- Issue date May 13, 2025
- Snap Inc.
- Orlando Miguel Pires dos Reis Moreira
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual vector arithmetic logic unit
- Patent number 12,299,413
- Issue date May 13, 2025
- Advanced Micro Devices, Inc.
- Bin He
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore master/slave communications
- Patent number 12,299,768
- Issue date May 13, 2025
- Imagination Technologies Limited
- Michael John Livesley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Load balancing system for the execution of applications on reconfig...
- Patent number 12,298,932
- Issue date May 13, 2025
- SambaNova Systems, Inc.
- Milad Sharif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sparse optimizations for a matrix accelerator architecture
- Patent number 12,293,431
- Issue date May 6, 2025
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Artificial intelligence accelerator device
- Patent number 12,293,229
- Issue date May 6, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Xiaoyu Sun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write merging on stores with different privilege levels
- Patent number 12,292,839
- Issue date May 6, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Matrix multiplication hardware architecture
- Patent number 12,287,844
- Issue date Apr 29, 2025
- SHANGHAI INFINIGENCE AI INTELLIGENT TECHNOLOGY CO., LTD.
- Shulin Zeng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technologies for dividing work across accelerator devices
- Patent number 12,288,101
- Issue date Apr 29, 2025
- Intel Corporation
- Susanne M. Balle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
General-purpose systolic array
- Patent number 12,287,756
- Issue date Apr 29, 2025
- Google LLC
- Reginald Clifford Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Execution unit sharing between processing cores in a cluster of a s...
- Patent number 12,282,447
- Issue date Apr 22, 2025
- QUALCOMM Incorporated
- Hithesh Hassan Lepaksha
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
LOW LATENCY MATRIX MULTIPLY UNIT
- Publication number 20250232003
- Publication date Jul 17, 2025
- Google LLC
- Andrew Everett Phelps
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR DEEP LEARNING NETWORK EXECUTION PIPELINE...
- Publication number 20250231770
- Publication date Jul 17, 2025
- Intel Corporation
- Liu Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MESSAGE-BASED PROCESSOR WITH TRANSMISSION DISABLING MODE
- Publication number 20250231905
- Publication date Jul 17, 2025
- Snap Inc.
- Orlando Miguel Pires dos Reis Moreira
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW LATENCY MATRIX MULTIPLY UNIT
- Publication number 20250232001
- Publication date Jul 17, 2025
- Google LLC
- Andrew Everett Phelps
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GENERAL-PURPOSE SYSTOLIC ARRAY
- Publication number 20250231906
- Publication date Jul 17, 2025
- Google LLC
- Reginald Clifford Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION
- Publication number 20250225083
- Publication date Jul 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CMOS COMPATIBLE MATRIX COMPUTING NETWORK
- Publication number 20250217312
- Publication date Jul 3, 2025
- Intel Corporation
- Zhen Zhou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANY-CORE PROCESSING APPARATUS, DATA PROCESSING METHOD, AND DEVICE...
- Publication number 20250217311
- Publication date Jul 3, 2025
- LYNXI TECHNOLOGIES CO., LTD.
- Wei HE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCE INTERPOLATION OPERATIONS
- Publication number 20250217313
- Publication date Jul 3, 2025
- ARM Limited
- Balaji VENU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE
- Publication number 20250209564
- Publication date Jun 26, 2025
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR STALLED ROUTING ASSOCIATED WITH NUMBER-THEORETIC- TR...
- Publication number 20250208879
- Publication date Jun 26, 2025
- Intel Corporation
- Raghavan KUMAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPLEMENTING ASYMMETRIC PROCESSOR CORES TO ENABLE HIGHER OPERATING...
- Publication number 20250199996
- Publication date Jun 19, 2025
- QUALCOMM Incorporated
- Raghava Rao Denduluri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPLEMENTING ASYMMETRIC PROCESSOR CORES TO ENABLE HIGHER OPERATING...
- Publication number 20250199997
- Publication date Jun 19, 2025
- QUALCOMM Incorporated
- Raghava Rao Denduluri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING SPARSITY METADATA TO REDUCE SYSTOLIC ARRAY POWER CONSUMPTION
- Publication number 20250199863
- Publication date Jun 19, 2025
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Computing-in-Memory Chip Architecture, Packaging Method, and Apparatus
- Publication number 20250199998
- Publication date Jun 19, 2025
- Hangzhou Zhicun (Witmem) Technology Co., Ltd.
- Shaodi WANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-Core Processor, Multi-Core Processor Processing Method, and R...
- Publication number 20250199999
- Publication date Jun 19, 2025
- Huawei Technologies Co., Ltd
- Guozhu Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR OFFLOADING ACCELERATION TASK SCHEDULING OPERATIONS...
- Publication number 20250202771
- Publication date Jun 19, 2025
- Intel Corporation
- Susanne M. Balle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPATIAL ARCHITECTURE FOR ATTENTION MECHANISMS
- Publication number 20250190177
- Publication date Jun 12, 2025
- UNTETHER AI CORPORATION
- Andrew Vincent ROCK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTING ARRAY USING GLOBAL NODE PROCESSING
- Publication number 20250190396
- Publication date Jun 12, 2025
- International Microsystems Inc.
- Peter Arthur Schade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICORE LIFESPAN MANAGEMENT USING EXTRANEOUS CORES
- Publication number 20250190253
- Publication date Jun 12, 2025
- ADVANCED MICRO DEVICES, INC.
- Srilatha Manne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR MULTI-BANKED VICTIM CACHE WITH DUAL DATAPATH
- Publication number 20250190368
- Publication date Jun 12, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GAME ENGINE ON A CHIP
- Publication number 20250182372
- Publication date Jun 5, 2025
- TMRW FOUNDATION IP S.ÀR.L.
- Cevat YERLI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Irregular Cadence Data Processing Units
- Publication number 20250181551
- Publication date Jun 5, 2025
- Google LLC
- Indranil Chakraborty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR DATA ACCESS AND SHARING
- Publication number 20250173308
- Publication date May 29, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIE-TO-DIE DENSE PACKAGING OF DETERMINISTIC STREAMING PROCESSORS
- Publication number 20250173309
- Publication date May 29, 2025
- Groq, Inc.
- Dennis Charles Abts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY
- Publication number 20250166114
- Publication date May 22, 2025
- Intel Corporation
- Abhishek Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LEVEL HIERARCHICAL ROUTING MATRICES FOR PATTERN-RECOGNITION P...
- Publication number 20250165429
- Publication date May 22, 2025
- Micron Technology, Inc.
- Harold B Noyes
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Forming Constant Extensions in the Same Execute Packet in a VLIW Pr...
- Publication number 20250156186
- Publication date May 15, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Timothy David Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR SYNCHRONIZATION OF MULTI-THREAD LANES
- Publication number 20250156222
- Publication date May 15, 2025
- Intel Corporation
- Valentin Andrei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA INITIALIZATION TECHNIQUES
- Publication number 20250156371
- Publication date May 15, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING

comprising an array of processing units with common control

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Vectorized scalar processor for executing scalar instructions in mu...

Coalescing adjacent gather/scatter operations

Discrete three-dimensional processor

Semiconductor device including array of processor elements and meth...

Two-dimensional processing array with a vertically stacked memory t...

Accelerated polynomial coding system and method

Neural network accelerators

Sorting the nodes of an operation unit graph for implementation in...

Rotating data for neural network computations

Processing cores and information transfer circuits arranged in matrix

Apparatus for accelerating neural networks

Methods and apparatus to facilitate atomic operations in victim cache

Implicit fence for write messages

Victim cache with write miss merging

Multiple contexts for a compute unit in a reconfigurable data proce...

Multi-memory on-chip computational network

Digital pre-distortion (DPD) adaptation using a hybrid hardware acc...

Hybrid hardware accelerator and programmable array architecture

Reconfigurable dataflow unit with streaming write functionality

Message based processor with transmission disabling mode

Dual vector arithmetic logic unit

Multicore master/slave communications

Load balancing system for the execution of applications on reconfig...

Sparse optimizations for a matrix accelerator architecture

Artificial intelligence accelerator device

Write merging on stores with different privilege levels

Matrix multiplication hardware architecture

Technologies for dividing work across accelerator devices

General-purpose systolic array

Execution unit sharing between processing cores in a cluster of a s...

Patents Applicationslast 30 patents

LOW LATENCY MATRIX MULTIPLY UNIT

METHODS AND APPARATUS FOR DEEP LEARNING NETWORK EXECUTION PIPELINE...

MESSAGE-BASED PROCESSOR WITH TRANSMISSION DISABLING MODE

LOW LATENCY MATRIX MULTIPLY UNIT

GENERAL-PURPOSE SYSTOLIC ARRAY

HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION

CMOS COMPATIBLE MATRIX COMPUTING NETWORK

MANY-CORE PROCESSING APPARATUS, DATA PROCESSING METHOD, AND DEVICE...

REDUCE INTERPOLATION OPERATIONS

SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE

TECHNIQUES FOR STALLED ROUTING ASSOCIATED WITH NUMBER-THEORETIC- TR...

IMPLEMENTING ASYMMETRIC PROCESSOR CORES TO ENABLE HIGHER OPERATING...

IMPLEMENTING ASYMMETRIC PROCESSOR CORES TO ENABLE HIGHER OPERATING...

USING SPARSITY METADATA TO REDUCE SYSTOLIC ARRAY POWER CONSUMPTION

Computing-in-Memory Chip Architecture, Packaging Method, and Apparatus

Multi-Core Processor, Multi-Core Processor Processing Method, and R...

TECHNOLOGIES FOR OFFLOADING ACCELERATION TASK SCHEDULING OPERATIONS...

SPATIAL ARCHITECTURE FOR ATTENTION MECHANISMS

COMPUTING ARRAY USING GLOBAL NODE PROCESSING

MULTICORE LIFESPAN MANAGEMENT USING EXTRANEOUS CORES

METHODS AND APPARATUS FOR MULTI-BANKED VICTIM CACHE WITH DUAL DATAPATH

GAME ENGINE ON A CHIP

Irregular Cadence Data Processing Units

GRAPHICS PROCESSOR DATA ACCESS AND SHARING

DIE-TO-DIE DENSE PACKAGING OF DETERMINISTIC STREAMING PROCESSORS

ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY

MULTI-LEVEL HIERARCHICAL ROUTING MATRICES FOR PATTERN-RECOGNITION P...

Forming Constant Extensions in the Same Execute Packet in a VLIW Pr...

SYSTEMS AND METHODS FOR SYNCHRONIZATION OF MULTI-THREAD LANES

DATA INITIALIZATION TECHNIQUES