1. Technical Field
The present invention is directed generally toward chip testing. Specifically, the invention relates to a method and apparatus for concurrently observing the state of internal signals within a chip during testing.
2. Description of the Related Art
Since the introduction of integrated circuitry some decades ago, integrated circuit technology has progressed steadily to provide continually increasing integrated circuit density and speed, while lowering power consumption. As a result, extremely complex integrated circuit designs have become possible, sometimes including up to millions of transistors. There is no indication that this trend towards higher density and speed in integrated circuits will abate, or reverse, at any time in the foreseeable future.
As the ability to increase logic capacity or density of modern integrated circuitry has grown, so has the complexity of modern logic designs. Associated with such increased logic complexity and logic density, however, is a similar increase in interconnection density (i.e., the interconnections between logic elements on an integrated circuit chip). Generally, the greater the number of logic elements which are employed in a logic design, the greater the number of logic signals which interconnect them. These interconnections can often occupy large areas on an integrated circuit die or semiconductor die, particularly when large busses and complex logic blocks are employed in the design of the integrated circuit.
In attempting to improve interconnection efficiency, designers will often employ multiplexing (MUX) techniques. As is known, communication signals from several channels may be combined in a multiplexer and sent in the form of a single, complex signal to another device that recovers the separate signals at the receiving end.
Due to the growing complexity of modern logic designs, the reliability of data signals in the integrated circuit chips is an ever-increasing important issue. Prior to employing test MUX methodology, testing strategy consisted of simulating the functionality of the chips as best as possible and then bringing a few state machines and other variables that were of particular concern or interest out to registers. However, the observable signals, such as external pins and the couple of registers that could be read, were a very small percentage of signals in the chip. Thus, designers still faced a large amount of guesswork when it came to debugging the chips. As a consequence of the testing limitations, debug cycles spanned several chip revisions, resulting in a time-consuming and costly process.
The addition of a single large MUX structure to the chip design improved the ability to observe the state of internal signals during operation. The MUX structure allowed the designers to select signals from any area of the chip and output to a few general purpose pins. This single large test MUX structure offered great flexibility in selecting signal sets for observation by providing for any-to-any observability. Debugging chips became faster and easier. However, despite providing the advantage of allowing one to “mix and match” signal sets, the single large MUX approach also presented substantial interconnect routing costs and congestion. Physical placement became a problem, since there were thousands of wires being routed from all over the chip to basically a single place. Consequently, in order to get a routable database, some of the observable signals had to be discarded, thereby discarding some of the destination routing flexibility.
To address the interconnect routing liability of the single large MUX approach, a hierarchy-based test MUX was designed. The hierarchy-based test MUX relieved the congestion by distributing the routing destinations throughout the chip and increased the capability to observe more signals than using the single large MUX structure. However, the destination flexibility was now removed, and signal observation was limited to a single group together. As a result, although the hierarchy-based test MUX assisted in validation/debug efforts, constraints were placed upon which signals could be concurrently observed.
Consequently, it would be beneficial to have a test MUX structure that provides greater flexibility in selecting signals for concurrent observation. Furthermore, it would also be desirable to have a test MUX structure that allowed for observing the same signal set for several modules concurrently. Moreover, it would be desirable to have a test MUX structure that allowed the mapping of each of the test signal groups to any of the test output groups.
The present invention provides a method and apparatus for observing the state of signals during chip testing. For a chip containing many instances of the same module, it is advantageous to observe the same signal set for several of the modules concurrently. In particular, the present invention improves upon prior test MUX methods by placing additional mapping/steering logic within a module to provide greater flexibility in selecting signal sets for concurrent observation. The addition of mapping/steering logic to a module's test MUX structure allows a chip designer to arbitrarily map each of the test signal groups to any of the test output groups.
The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
The description of the preferred embodiment of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiment was chosen and described in order to best explain the principles of the invention the practical application to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
As previously mentioned, the present invention provides a method and apparatus for observing the state of signals during chip testing. The present invention places additional mapping/steering logic within a module to provide greater flexibility in selecting signal sets for concurrent observation. The addition of mapping/steering logic to a module's test MUX structure allows a chip designer to arbitrarily map each of the test signal groups to any of the test output groups.
For a chip containing many instances of the same module, it is advantageous to observe the same signal set for several of the modules concurrently. The present invention improves upon prior test MUX methods by placing additional mapping/steering logic within a module, as shown in
For example purposes, a 32-bit test MUX is used in the chip design shown in
Prior art test MUX methods that offered any-to-any (unconstrained) observability resulted in substantial interconnect routing costs and congestion. Subsequent prior art test MUX methods that attempted to reduce the routing costs and congestion resulted in a constrained but fixed mapping of the test MUX signals. In contrast, the addition of the byte lane mapping logic in the present invention as shown in
As mentioned previously, the present invention involves chip testing by observing the state of internal signals during operation. The present invention may also be implemented in multiple modules, allowing observation of the same signal set for several modules concurrently.
The plurality of modules 310, 320, 330, and 340 in the top-level test MUX structure in
The present invention as illustrated in
Thus, the present invention provides a mechanism for chip testing by concurrently observing the state of internal signals during operation. With the present invention, the addition of mapping/steering logic within the module allows each of the test signal groups to be arbitrarily mapped to any of the test output groups, thereby providing the flexibility of moving the test outputs around in order to observe the same set of signals from two or more similar or identical blocks at the same time.
Thus, the present invention solves the disadvantages of the prior art by providing a method and apparatus for concurrently observing the state of signals during chip testing. It is critical that designs be verified for functional correctness at every stage in the design flow in order to ensure that errors are detected as early as possible. Early detection of errors may prevent massive redesigning efforts from occurring well into the design process. It is advantageous for a chip containing many instances of the same module to observe the same signal set for several of the modules concurrently. The present invention enhances the hierarchical test MUX method by disclosing a test MUX structure which allows for greater flexibility in selecting signals for concurrent observation. The addition of mapping/steering logic to a module's test MUX structure allows a chip designer to arbitrarily map each of the test signal groups to any of the test output groups.
The description of the present invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiment was chosen and described in order to best explain the principles of the invention, the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.