Reliability becomes a big concern for modern VLSI chips, due to the shrinking lithography, new material, and design complexity, etc. The major causes of reliability failures include electro-migration (modeled as resistive bridges), gate oxide breakdown (resistive shorts), hot carrier injection (delay faults), etc. Most of the reliability failures will cause the chip to degrade or slow down, and eventually the chip will stop functioning. Therefore, there is a need to monitor and predict the reliability of a chip in the field. So far, there is no on-line reliability monitor once the chip is shipped. Therefore, the degradation of a chip cannot be monitored. This embodiment teaches a new solution for this problem.
Logic-Built-In-Self-Test (LBIST) is a widely accepted Design-for-Test (DFT) feature of VLSI chip designs, especially for the microprocessor designs. It can be used to test the circuit at wafer, chip, and system level. During testing, a specific designed circuitry is running and generates test stimulus and collects testing results. Test can be performed at both dc and ac fashion.
With added features and new methodology, LBIST can be used as an on-line reliability monitor with very little or no overhead, depending on the LBIST implementation.
In an embodiment of this invention, instead of using LBIST to get a pass or no-pass result, a selective signature feature is used to collect the top failing paths by shmooing the chip over a cycle time. These paths can be stored on-chip or off-chip for later use. Once the chip is running in the field for a certain time, the same procedure is performed to collect the top failing paths and compared with the stored old paths, if the order of the top paths changes, it indicates that for example there is a path (not the slowest path before) that slows more than others, which could be potential reliability concern. Therefore, a potential reliability failure is identified in the field.
The LSSD (level sensitive scan design) methodology is a system design and a Design-for-Test (DFT) approach that incorporates several basic test concepts, i.e. scan design. In such a design, most of the device's storage elements, such as latches or registers, are concatenated in one or more scan chains and can be externally accessible via one or more serial inputs and outputs. Storage elements that are not in this category are usually memory or other special macros that are isolated and tested independently. Furthermore, this design methodology ensures that all logic feedback paths are gated by one or more of these storage elements, thereby simplifying a sequential design into subsets of combinational logic (100, 110 and 120, respectively) sections as shown in
These basic design concepts in conjunction with the associated system and scan clocking sequences greatly simply the test generation, testing, and diagnose-ability of very complex logic structures. Every latch can be used as a pseudo Primary Input (PI) and as a pseudo Primary Output (PO) in addition to the standard PIs and POs to enhance the stimulation and observe-ability of the device being tested or diagnosed. LSSD latches are typically implemented in a L1/L2 configuration where the L1 or master latch has two data ports and may be updated either using scan clock A/B or functional clock C1/C2 (200 and 210, respectively) as shown in
In a typical STUMPS structure, shown in
This STUMPS structure can be further enhanced by adding some control logic (400) to not only let the test results from a group of latches compress into MISR, but an individual latch as well.
In an embodiment of this invention, with the structure shown in
An embodiment of the invention is a method for measuring and predicting reliability of a VLSI chip, the method is comprised of:
A system, apparatus, or device comprising one of the following items is an example of the invention: VLSI, chip, reliability analyzer, failure analyzer, tests, storing, registers, Shmoo test, computer monitor, or any display device, applying the method mentioned above, for purpose of VLSI/chip analysis, reliability, and management.
Any variations of the above teaching are also intended to be covered by this patent application.
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