Claims
- 1. An interpolating circuit for use with a counter clocked by a master clock in a tester system, the interpolating circuit comprising:a shift register clocked by the master clock, the shift register having an input and an output, the input coupled to receive an activation signal, and the output coupled to provide a stop signal, whereby the stop signal is a delayed form of the activation signal; a ramp circuit having a capacitor, the ramp circuit charging the capacitor in response to receipt of the activation signal, and the ramp circuit discharging the capacitor in response to receipt of the stop signal; and a signal driver connected to the ramp circuit, the signal driver activating an enable signal to the counter when the capacitor is charged to a predetermined voltage.
- 2. The interpolating circuit of claim 1, wherein the shift register has multiple outputs, one of which is selectively coupled to provide the stop signal to calibrate the ramp circuit.
- 3. The interpolating circuit of claim 2, wherein coupling to provide the stop signal from different outputs of the shift register produces different count values in the counter.
- 4. The interpolating circuit of claim 2, wherein the shift register includes sequentially connected flip flops, the flip flops connected to drive the multiple outputs.
- 5. The interpolating circuit of claim 1, wherein the ramp circuit receives distinct start and stop signals.
Parent Case Info
This application is a divisional (and claims the benefit of priority under 356 USC 120) of U.S. application Ser. No. 08/949,747, filed Oct. 14, 1997, now U.S. Pat. No. 6,081,484. The disclosure of the prior application is considered part of (and is incorporated by reference) the disclosure of this application.
US Referenced Citations (5)