Claims
- 1. A memory controller, comprising:
a plurality of multi-entry read buffers each adapted to be coupled to a memory module, data from said memory modules being stored in said read buffers in response to a read command; a plurality of load pointer logic circuits each generating a load pointer that identifies an entry in an associated read buffer in which data is to be loaded; a plurality of unload pointer logic circuits each generating an unload pointer that identifies an entry in an associated read buffer from which data is to be consumed; each of said load pointer logic circuits and said unload pointer logic circuits receiving a synch arm signal which causes said logic circuits to hold their associated pointers at a predetermined pointer value to initialize the pointers.
- 2. The memory controller of claim 1 wherein during initialization all of said unload pointer logic circuits receive a read strobe signal that causes the unload pointer logic circuits to release their unload pointers to begin incrementing.
- 3. The memory controller of claim 2 each unload pointer logic circuit increments its unload pointer using a clock signal provided from a clock divider coupled to the unload pointer logic circuit.
- 4. The memory controller of claim 1 wherein all of said load pointer logic circuits couple to a data bus which couples to at least some of the memory modules and during initialization when each of said load pointer logic circuits detects the presence of a bit pattern on its associated data bus causes its load pointer to be released and begin incrementing.
- 5. The memory controller of claim 4 wherein each load pointer logic circuit increments its load pointer using a clock to master clock that is provided and routed by the memory controller to the memory modules and back to the memory controller.
- 6. The memory controller of claim 1 wherein, after initialization completes, said load and unload pointers are free running pointers.
- 7. The memory controller of claim 1 wherein, after initialization, said load pointer logic circuits increment their load pointers using source synchronous clocking.
- 8. The memory controller of claim 7 wherein, after initialization, said unload pointer logic circuits increment their unload pointers using a clock that is not guaranteed to be substantially in phase with clocks used by the load pointer logic circuits to increment the load pointers.
- 9. A method to initialize a memory controller coupled to a plurality of memory modules via a plurality of memory channels, comprising:
writing a predetermined bit pattern to each memory channel for storage in the memory modules; for each memory channel, keeping load and unload pointers associated with a read buffer from incrementing; issuing a read command to cause the memory modules to provide the predetermined bit pattern back to the memory controller over the memory channels; for each memory channel, detecting that the requested bit pattern has begun to arrive over the memory channel and then releasing that channel's load pointer to begin incrementing in accordance with a source synchronous clock signal.
- 10. The method of claim 9 further including:
counting a predetermined amount of time after issuing the read command to the memory channels; and releasing all of the unload pointers associated with the read buffers in all of the memory channels to increment in accordance a clock signal that is different than said source synchronous clock signal.
- 11. The method of claim 10 wherein said predetermined amount of time is substantially the maximum skew time associated with the memory channels.
- 12. A computer system, comprising:
a CPU core; an I/O device coupled to said CPU core; and a memory controller coupled to a plurality of memory modules, including:
a plurality of multi-entry read buffers each adapted to be coupled to a memory module, data from said memory modules being stored in said read buffers in response to a read command; plurality of load pointer logic circuits each generating a load pointer that identifies an entry in an associated read buffer in which data is to be loaded; a plurality of unload pointer logic circuits each generating an unload pointer that identifies an entry in an associated read buffer from which data is to be consumed; and each of said load pointer logic circuits and said unload pointer logic circuits receiving a synch arm signal which causes said logic circuits to hold their associated pointers at a predetermined pointer value to initialize the pointers.
- 13. The computer system of claim 12 wherein during initialization all of said unload pointer logic circuits receive a read strobe signal that causes the unload pointer logic circuits to release their unload pointers to begin incrementing.
- 14. The computer system of claim 13 each unload pointer logic circuit increments its unload pointer using a clock signal provided from a clock divider coupled to the unload pointer logic circuit.
- 15. The computer system of claim 12 wherein all of said load pointer logic circuits -couple to a data bus which couples to at least some of the memory modules and during initialization when each of said load pointer logic circuits detects the presence of a bit pattern on its associated data bus causes its load pointer to be released and begin incrementing.
- 16. The computer system of claim 15 wherein each load pointer logic circuit increments its load pointer using a clock to master clock that is provided and routed by the memory controller to the memory modules and back to the memory controller.
- 17. The computer system of claim 12 wherein, after initialization completes, said load and unload pointers are free running pointers.
- 18. The computer system of claim 12 wherein, after initialization, said load pointer logic circuits increment their load pointers using source synchronous clocking.
- 19. The computer system of claim 18 wherein, after initialization, said unload pointer logic circuits increment their unload pointers using a clock that is not guaranteed to be substantially in phase with clocks used by the load pointer logic circuits to increment the load pointers.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application relates to the following commonly assigned co-pending applications entitled:
[0002] “Apparatus And Method For Interfacing A High Speed Scan-Path With Slow-Speed Test Equipment,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-23700; “Rotary Rule And Coherence Dependence Priority Rule,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-27300; “Speculative Scalable Directory Based Cache Coherence Protocol,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-27400; “Scalable Efficient I/O Port Protocol,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-27500; “Efficient Translation Buffer Miss Processing For Applications Using Large Pages In Systems With A Large Range Of Page Sizes By Eliminating Page Table Level,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-27600; “Fault Containment And Error Recovery Techniques In A Scalable Multiprocessor,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-27700; “Speculative Directory Writes In A Directory Based CC-Non Uniform Memory Access Protocol,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-27800; “Special Encoding Of Known Bad Data,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-27900; “Broadcast Invalidate Scheme,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-28000; “Mechanism To Keep All Pages Open In A DRAM Memory System,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-28100; “Programmable DRAM Address Mapping Mechanism,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-28200; “Mechanism To Enforce Memory Read/Write Fairness, Avoid Tristate Bus Conflicts, And Maximize Memory Bandwidth,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-29200; “An Efficient Address Interleaving With Simultaneous Multiple Locality Options,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-29300; “A High Performance Way Allocation Strategy For A Multi-Way Associative Cache System,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-29400; “Method And System For Absorbing Defects In High Performance Microprocessor With A Large N-Way Set Associative Cache,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-29500; “A Method For Reducing Directory Writes And Latency In A High Performance, Directory-Based, Coherency Protocol,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-29600; “Mechanism To Reorder Memory Read And Write Transactions For Reduced Latency And Increased Bandwidth,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-30800; “Look-Ahead Mechanism To Minimize And Manage Bank Conflicts In A Computer Memory System,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-30900; “Resource Allocation Scheme That Ensures Forward Progress, Maximizes Utilization Of Available Buffers And Guarantees Minimum Request Rate,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-31000; “Input Data Recovery Scheme,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-31100; “Fast Lane Prefetching,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-31200; “Mechanism To Control The Allocation Of An N-Source Shared Buffer,” Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-31400; and “Chaining Directory Reads And Writes To Reduce DRAM Bandwidth In A Directory Based CC-NUMA Protocol, Ser. No. ______, filed Aug. 31, 2000, Attorney Docket No. 1662-31500, all of which are incorporated by reference herein.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09652480 |
Aug 2000 |
US |
Child |
10441451 |
May 2003 |
US |