Claims
- 1. A memory access control circuit, comprising:a holder for removably holding a recording medium having a memory storing a data signal and a controller to read the data signal from said memory in response to a read control signal; an outputter for outputting to said controller a plurality of read control signals different in active period from one another; a determiner for determining whether each of the plurality of data signals read in response to the plurality of read control signals is proper in data value or not; and an enabler for enabling a shortest active period among the active periods corresponding to determination results that the data value is proper.
- 2. A memory access control circuit according to claim 1, wherein said memory stores a common data signal that is common to respective ones of said recording medium, each of the plurality of read control signals including storage-destination address information for the common data signal, and said determiner determines whether the common data signal read from said memory exhibits a predetermined value or not.
- 3. A memory access control circuit according to claim 1, further comprising:a detector for detecting a capacity value of said memory, and an enabler for enabling said outputter when the capacity value exceeds a predetermined threshold.
- 4. A memory access control circuit according to claim 3, wherein said memory stores a capacity value data signal representative of the capacity value, and said detector detects the capacity value by reading the capacity value data signal.
Priority Claims (2)
Number |
Date |
Country |
Kind |
2000-35058 |
Feb 2000 |
JP |
|
2000-137508 |
May 2000 |
JP |
|
Parent Case Info
This is a DIVISION of SER. NO. 09/780,424, filed Feb. 12, 2001.
US Referenced Citations (1)
Number |
Name |
Date |
Kind |
5291468 |
Carmon et al. |
Mar 1994 |
A |