Patent Application
20250218496
With development of semiconductor technologies, semiconductor memories are widely applied to electronic apparatuses. A dynamic random access memory (DRAM) belongs to a volatile memory, and the dynamic random access memory is usually utilized as a cache due to a fast access speed.
Two parts, that is, a peripheral circuit (Periphery) and a memory array (Core) are mainly included in the dynamic random access memory. To further increase the storage density, in a three-dimensional DRAM (3D DRAM), the peripheral circuit (Periphery) and the memory array (Core) are respectively disposed in two independent chips, and then the two chips are connected to each other in a bonding manner. In addition, a three-dimensional structure of the memory array is more complex, and therefore additional control logic is required.
The present disclosure relates to the semiconductor field, and in particular, to a memory and a control method therefor, and an electronic device.
Embodiments of the present disclosure provide a memory and a control method therefor, and an electronic device.
The technical solutions of the present disclosure are implemented as follows.
According to a first aspect, the present disclosure provides a memory. A first chip is included in the memory, multiple memory array tiles are included in the first chip, multiple local bit lines and multiple common bit lines are included in each of the memory array tiles, the local bit lines extend in a first direction, the common bit lines extend in a second direction, one of the common bit lines exists on each of two sides of the local bit lines in the first direction, and the first direction intersects the second direction.
Each of the local bit lines is coupled to the common bit line on one side through a respective bit line selector, and each of the local bit lines is coupled to the common bit line on the other side through a respective precharge switch.
The bit line selector is configured to receive a sub word line drive signal, and selectively connect a connected local bit line to a connected common bit line based on the sub word line drive signal.
The precharge switch is configured to receive a sub word line drive complementary signal, and selectively connect a connected local bit line to a connected common bit line based on the sub word line drive complementary signal; and both the sub word line drive signal and the sub word line drive complementary signal are generated by decoding a row address signal in a command address signal received by the memory.
In some embodiments, multiple sub array tiles sequentially arranged in the second direction are included in each of the memory array tiles, multiple storage regions sequentially stacked in a third direction are included in each of the sub array tiles, and two storage layer groups arranged in the first direction are included in each of the storage regions; and multiple ones of the local bit lines are disposed in each of the storage layer groups, a first common bit line is disposed on the outer side of each of the storage layer groups away from the other one of the storage layer groups in the same one of the storage regions, and a second common bit line is disposed on the inner side of each of the storage layer groups close to the other one of the storage layer groups in the same one of the storage regions.
For each of the storage layer groups, each of the local bit lines is coupled to the second common bit line through the respective bit line selector, and each of the local bit lines is coupled to the first common bit line through the respective precharge switch.
In some embodiments, multiple sub array tiles sequentially arranged in the second direction are included in each of the memory array tiles, multiple storage regions sequentially stacked in a third direction are included in each of the sub array tiles, and two storage layer groups arranged in the first direction are included in each of the storage regions; and multiple ones of the local bit lines are disposed in each of the storage layer groups, a first common bit line is disposed on the outer side of each of the storage layer groups away from the other one of the storage layer groups in the same one of the storage regions, and a second common bit line is disposed on the inner side of each of the storage layer groups close to the other one of the storage layer groups in the same one of the storage regions.
The storage regions are numbered in the third direction for the same one of the sub array tiles.
For an odd-numbered one of the storage regions, each of the local bit lines is coupled to the first common bit line through the respective bit line selector, and each of the local bit lines is coupled to the second common bit line through the respective precharge switch.
For an even-numbered one of the storage regions, each of the local bit lines is coupled to the second common bit line through the respective bit line selector, and each of the local bit lines is coupled to the first common bit line through the respective precharge switch.
In some embodiments, multiple local word lines are further included in the memory array tile, and each of the local word lines runs through multiple stacked storage layer groups in the third direction; and the third direction is perpendicular to the first direction and perpendicular to the second direction.
One sub word line group is formed by multiple ones of the local word lines that are aligned in the first direction and that pass through the same one of the storage layer groups.
One of the local bit lines and one sub word line group have a correspondence, and a memory cell is formed at an intersection of the local bit line and each corresponding one of the local word lines.
All local word lines in the same sub word line group share the same sub word line drive signal and the same sub word line drive complementary signal, the bit line selector of the local bit line receives the sub word line drive signal of a corresponding sub word line group, and the precharge switch of the local bit line receives the sub word line drive complementary signal of the corresponding sub word line group.
In some embodiments, multiple common word lines extending in the second direction are further included in each of the memory array tiles.
The local word lines in each of the sub array tiles are numbered sequentially and independently, and the identically numbered local word lines in different ones of the sub array tiles are electrically connected to the same one of the common word lines, and share the same sub word line drive signal and the same sub word line drive complementary signal.
In some embodiments, in the memory array tiles, the common word lines are sequentially numbered in the first direction, and one main word line group is formed by N consecutively numbered ones of the common word lines.
A decoding unit and multiple sub word line driver units are included in the memory, where N is a positive integer.
The decoding unit is configured to decode the row address signal to generate a main word line drive signal, the sub word line drive signal, and the sub word line drive complementary signal that are of each of the common word lines.
The sub word line driver unit is coupled to one of the common word lines and is configured to: receive, and enable or disable the coupled common word line based on, a corresponding main word line drive signal, a corresponding sub word line drive signal, and a corresponding sub word line drive complementary signal.
The two storage layer groups in each of the storage regions are sequentially referred to as a first storage layer group and a second storage layer group in the first direction, the main word line drive signal is configured to select one main word line group from both the first storage layer group and the second storage layer group, and the sub word line drive signal and the sub word line drive complementary signal are configured to select one of the common word lines from the selected main word line group in the first storage layer group, or select one of the common word lines from the selected main word line group in the second storage layer group.
In some embodiments, a first switching transistor, a second switching transistor, and a third switching transistor are included in the sub word line driver unit.
Control terminals of both the first switching transistor and the second switching transistor receive the main word line drive signal, a first terminal of the first switching transistor receives the sub word line drive signal, a second terminal of the first switching transistor, a first terminal of the second switching transistor, and a first terminal of the third switching transistor are all connected to the common word line, both a second terminal of the second switching transistor and a second terminal of the third switching transistor are connected to a power terminal, and a control terminal of the third switching transistor receives the sub word line drive complementary signal.
In some embodiments, a second chip is further included in the memory, the first chip and the second chip are stacked in the third direction, and the first chip is bonded to the second chip.
A sense amplification region is included in the second chip.
In the first chip, a stair contact structure is disposed between two of the storage layer groups adjacent in the first direction, and the common bit line directly connected to the bit line selector is coupled to the sense amplification region through the stair contact structure.
According to a second aspect, an embodiment of the present disclosure provides a control method for a memory. Multiple memory array tiles are included in a first chip in the memory, multiple local bit lines and multiple common bit lines are included in each of the memory array tiles, each of the local bit lines is coupled to a common bit line on one side through a bit line selector, and each of the local bit lines is coupled to a common bit line on the other side through a respective precharge switch.
The method includes the steps as follows.
A command address signal is received, and a row address signal in the command address signal is decoded to generate multiple main word line drive signals, multiple sub word line drive signals, and multiple sub word line drive complementary signals.
Whether a corresponding bit line selector is to connect a connected local bit line to a connected common bit line is controlled based on each of the sub word line drive signals.
Whether a corresponding precharge switch is to connect a connected local bit line to a connected common bit line is controlled based on each of the sub word line drive complementary signals.
In some embodiments, multiple sub array tiles sequentially arranged in a second direction are included in each of the memory array tiles, multiple storage regions sequentially stacked in a third direction are included in each of the sub array tiles, and two storage layer groups arranged in a first direction are included in each of the storage regions; and multiple ones of the local bit lines are disposed in each of the storage layer groups, and one of the common bit lines is separately disposed on two sides of each of the storage layer groups in the first direction.
Multiple local word lines are further included in the memory array tile, and each of the local word lines runs through multiple stacked storage layer groups in the third direction; one sub word line group is formed by multiple ones of the local word lines that are aligned in the first direction and that pass through the same one of the storage layer groups, and all local word lines in the same sub word line group share the same sub word line drive signal and the same sub word line drive complementary signal; and one of the local bit lines and one sub word line group have a correspondence, and a memory cell is formed at an intersection of the local bit line and each corresponding one of the local word lines.
Each sub word line group has a sub word line drive signal and a sub word line drive complementary signal; and the method further includes the steps as follows.
The sub word line drive signal of the sub word line group is transmitted to the bit line selector of the local bit line corresponding to the sub word line group.
The sub word line drive complementary signal of the sub word line group is transmitted to the precharge switch of the local bit line corresponding to the sub word line group.
In some embodiments, the local word lines in each of the sub array tiles are numbered sequentially and independently, and the identically numbered local word lines in different ones of the sub array tiles are electrically connected to the same one of the common word lines, and share the same sub word line drive signal and the same sub word line drive complementary signal; and in the memory array tiles, the common word lines are numbered in the first direction, and one main word line group is formed by N consecutively numbered ones of the common word lines.
Two storage layer groups in each of the storage regions are sequentially referred to as a first storage layer group and a second storage layer group in the first direction; and the method further includes the steps as follows.
One main word line group is selected from both the first storage layer group and the second storage layer group based on the main word line drive signals.
One of the common word lines is selected from the selected main word line group in the first storage layer group or the selected main word line group in the second storage layer group based on the sub word line drive signal and the sub word line drive complementary signal.
The selected common word line is enabled, and an operation indicated by the command address signal is performed.
According to a third aspect, an embodiment of the present disclosure provides an electronic device, and the memory according to the first aspect is included in the electronic device.
The embodiments of the present disclosure provide the memory and the control method therefor, and the electronic device, to control working states of the precharge switch and the bit line selector of the local bit line based on the sub word line drive signal and the sub word line drive complementary signal generated by decoding the row address signal. Therefore, although the precharge switch and the bit line selector are additionally introduced into a three-dimensional memory, it is unnecessary to additionally introduce control information and redundant decoding logic, thereby improving control efficiency and omitting a redundant component.
To make the objectives, technical solutions, and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further described in detail below with reference to the accompanying drawings and the embodiments. The described embodiments should not be considered as limitations to the present disclosure. All other embodiments obtained by a person of ordinary skill in the art without creative efforts fall within the scope of the present disclosure.
The following descriptions relate to “some embodiments” describing a subset of all possible embodiments. However, it may be understood that “some embodiments” may be the same subset or different subsets of all the possible embodiments, and may be combined with each other when there is no conflict.
The following descriptions are added if descriptions such as “first/second” appear in the application document. In the following descriptions, involved terms “first/second/third” are merely for distinguishing between similar objects and do not represent specific rankings of the objects. It may be understood that “first/second/third” may be interchanged for a specific sequence or order if allowed, so that the embodiments of the present disclosure described herein can be implemented in a sequence other than those shown or described herein.
Unless otherwise defined, all technical and scientific terms employed in this specification have meanings the same as those commonly understood by a person skilled in the technical field of the present disclosure. The terms employed in this specification are merely intended to describe the embodiments of the present disclosure, but are not intended to limit the present disclosure.
Explanations of nouns:
Before the embodiments of the present disclosure are described, three directions that may be employed to describe three-dimensional structures in planes in the following embodiments are first defined. For example, in a Cartesian coordinate system, the three directions may include a first direction, a second direction, and a third direction.
A semiconductor chip may include a top surface located on the front and a bottom surface located on the back opposite to the front. When flatness of the top surface and the bottom surface is ignored, a direction intersecting with (e.g., perpendicular to) the top surface and the bottom surface of the semiconductor chip is defined as a third direction. In addition, an extension direction of a local bit line in the semiconductor chip is defined as a first direction, an extension direction of a local word line in the semiconductor chip is defined as a second direction, and the first direction intersects the second direction.
A first chip and a second chip stacked in the third direction are included in a 3D DRAM, memory arrays (Core) are distributed in the first chip, and a peripheral control region (Periphery) and a sense amplification region are distributed in the second chip. For the first chip, a large quantity of memory cells are included in the memory array (Core), and the memory cells are further divided into multiple memory array tiles (Mat), so that control and management are better performed.
Data reading is taken as an example. Multiple groups of target memory cells are enabled by opening a common word line, each group of target memory cells are aligned in the third direction, and bit line selectors Se of local bit lines connected to each group of target memory cells are turned on. In this case, each target memory cell is connected to a respective corresponding second common bit line, so that a group of second common bit lines aligned in the third direction share charges with a respective target memory cell, sense amplification is performed, and the second common bit line is at a high potential or a low potential (which depends on data stored in the target memory cell) after the sense amplification. A bit line selector Se of an unselected local bit line is turned off and a precharge switch Eq is turned on, and all first common bit lines are charged to a precharge potential, so that all unselected local bit lines are at the precharge potential. Herein, the precharge potential may be an intermediate potential, and the intermediate potential may be half of a power voltage (Vblh) of a memory array, that is, the intermediate potential=½ Vblh.
In short, for the three-dimensional memory 3D DRAM, local bit lines of the same storage layer group share one first common bit line and the same second common bit line. The bit line selector Se is employed to choose whether to access the second common bit line, and the precharge switch Eq is employed to choose whether to access the first common bit line. Therefore, it is necessary to additionally design a control logic of the bit line selector Se/the precharge switch Eq.
The following describes the embodiments of the present disclosure in detail with reference to the accompanying drawings.
In an embodiment of the present disclosure, a memory is provided. A first chip is included in the memory, and multiple memory array tiles 11 are included in the first chip.
Each local bit line is coupled to the common bit line on one side through a respective bit line selector Se, and each local bit line is coupled to the common bit line on the other side through a respective precharge switch Eq.
The bit line selector Se is configured to receive a sub word line drive signal Phdec<i> (i is a positive integer), and selectively connect a connected local bit line to a connected common bit line based on the sub word line drive signal.
The precharge switch Eq is configured to receive a sub word line drive complementary signal PhdecN<i> (i is a positive integer), and selectively connect a connected local bit line to a connected common bit line based on the sub word line drive complementary signal.
Herein, both the sub word line drive signal Phdec<i> and the sub word line drive complementary signal PhdecN<i> are generated by decoding a row address signal in a command address signal received by the memory. Generally, the sub word line drive complementary signal PhdecN<i> may be obtained by performing inversion processing on the sub word line drive signal Phdec<i>. In addition, in some embodiments, the sub word line drive complementary signal PhdecN<i> may be obtained by performing inversion processing and delay processing on the sub word line drive signal Phdec<i>, and the sub word line drive signal Phdec<i> and the sub word line drive complementary signal PhdecN<i> are not in a completely strict inversion state.
It should be understood that the row address signal is configured to indicate word line information selected (e.g., enabled) in this operation. To be specific, in this embodiment of the present disclosure, the word line information is reused to control working states of the precharge switch Eq and the bit line selector Se of the local bit line. For a specific principle, refer to subsequent description. Therefore, for a three-dimensional memory, although the precharge switch Eq and the bit line selector Se are additionally introduced, it is unnecessary to additionally introduce control information and redundant decoding logic, thereby improving control efficiency and omitting a redundant component.
It should be noted that
Referring to
In some embodiments, as shown in
For each storage layer group, each local bit line is coupled to the second common bit line 13 through a respective bit line selector Se, and each local bit line is coupled to the first common bit line 12 through a respective precharge switch Eq.
In some embodiments, a second chip is further included in the memory. The first chip and the second chip are stacked in the third direction, and the first chip is bonded to the second chip. A sense amplification region is included in the second chip.
In the first chip, a stair contact structure is disposed between two storage layer groups adjacent in the first direction, and the common bit line directly connected to the bit line selector Se is coupled to the sense amplification region through the stair contact structure.
It should be noted that the first chip is connected to the second chip through bonding. The bonding connection means that two chips are electrically connected through a hybrid bonding (also referred to as a bonding pillar) structure. Hybrid bonding refers to a process of creating permanent bonding between heterogeneous or homogeneous chips. “Hybrid bonding” refers to forming dielectric-dielectric and metal-metal bonding between two surfaces, and has the following advantages: (1) Shorter interconnection distance: No lead is required for interconnection, and no TSV is required for crossing the entire CMOS layer. Interconnection can be implemented simply by a copper contact connected to a rear channel. (2) Higher interconnection density: An area of a copper contact is extremely small. In comparison with a solder ball and a TSV with a diameter of one hundred microns, a spacing size of the copper contact in a hybrid bonding process is even less than 10 microns, which can undoubtedly achieve a higher interconnection density. (3) Lower costs: It undoubtedly takes more time to interconnect each chip individually. A large area of high-density interconnection can be implemented through wafer bonding, which contributes significantly to the improvement of production capacity. Naturally, production costs can be reduced.
It should be noted that multiple sense amplifiers (SA) are included in the sense amplification region, which are also referred to as sensitive amplifiers. By performing sense amplification on an electrical signal of a common bit line connected to a selected memory cell, a potential of the common bit line finally reaches a low potential or a high potential, so that data is read from or written into the selected memory cell.
Herein, a storage structure is formed by vertically stacking multiple layers of memory cells (namely, multiple storage layer groups) in a 3D DRAM. In this case, to ensure that the sense amplifier can be successfully connected to the common bit line in each storage layer group, a 3D stair contact structure (Staircase) needs to be formed. Different stairs of the stair contact structure are electrically isolated, and one stair is correspondingly connected to one common bit line (connected to the bit line selector Se). Further, the common bit line is connected to the sense amplifier SA in the sense amplification region, to implement sense amplification processing.
In this way, the local bit line in each storage layer group is coupled, through the bit line selector Se, to the second common bit line 13 disposed in the middle part of the storage region to which the local bit line belongs, and the stair contact structure is further disposed in the middle part of the storage region. In other words, the second common bit line 13 in each storage layer group can be externally connected to the sense amplifier in the sense amplification region through the stair contact structure disposed in the middle part of the storage region.
In some other embodiments, referring to
For the odd-numbered storage regions 1 and 3, each local bit line is coupled to the first common bit line 12 through the respective bit line selector Se, and each local bit line is coupled to the second common bit line 13 through the respective precharge switch Eq. For the even-numbered storage regions 0, 2, and 4, each local bit line is coupled to the second common bit line 13 through the respective bit line selector Se, and each local bit line is coupled to the first common bit line 12 through the respective precharge switch Eq.
That is, the first common bit lines 12 of two adjacent storage layer groups are adjacent in the third direction, and the second common bit lines 13 of the two adjacent storage layer groups are adjacent in the third direction, but any first common bit line 12 and any second common bit line 13 are not adjacent in the third direction. In addition, for the odd-numbered storage regions 1 and 3, the local bit line is connected to the first common bit line 12 through the bit line selector Se, and is connected to the second common bit line 13 through the precharge switch Eq. For the even-numbered storage regions 0, 2, and 4, the local bit line is connected to the second common bit line 13 through the bit line selector Se, and is connected to the first common bit line 12 through the precharge switch Eq. Therefore, in a process of sense amplification processing, for multiple selected storage layer groups, for two adjacent first common bit lines 12, it is inevitable that one first common bit line 12 is in a sense amplification state (at a high potential or a low potential after the sense amplification state ends, which depends on a specific data value), and the other first common bit line 12 is at a precharge potential. For two adjacent second common bit lines 13, it is inevitable that one second common bit line 13 is in a sense amplification state (at a high potential or a low potential after the sense amplification state ends, which depends on a specific data value), and the other second common bit line is at a precharge potential, where the low potential<the precharge potential<the high potential. However, sense amplification processing is not simultaneously performed on the two common bit lines adjacent in the third direction, so that the two common bit lines adjacent in the third direction are not simultaneously in the sense amplification state. Therefore, a coupling condition of the two adjacent common bit lines obviously weakens, and sense amplification margin is improved.
Certainly, regardless of changes of locations of the precharge switch Eq and the bit line selector Se, control signals received by the precharge switch Eq and the bit line selector Se are unchanged, so that the sub word line drive complementary signal PhdecN<i> and the sub word line drive signal Phdec<i> generated by the row address signal are still reused for control.
In addition, referring to
In some embodiments, referring to
For example, for a first storage layer group, one sub word line group is formed by local word lines WL<0>, WL<4>, . . . , WL<1592>, and WL<1596>, and the sub word line group shares Phdec<0> and PhdecN<0>. One sub word line group is formed by local word lines WL<1>, WL<5>, . . . , WL<1593>, and WL<1597>, and the sub word line group shares Phdec<1> and PhdecN<1>. One sub word line group is formed by local word lines WL<2>, WL<6>, . . . , WL<1594>, and WL<1598>, and the sub word line group shares Phdec<2> and PhdecN<2>. One sub word line group is formed by local word lines WL<3>, WL<7>, . . . , WL<1595>, and WL<1599>, and the sub word line group shares Phdec<3> and PhdecN<3>.
For a second storage layer group, one sub word line group is formed by local word lines WL<1600>, WL<1604>, . . . , WL<3192>, and WL<3196>, and the sub word line group shares Phdec<4> and PhdecN<4>. One sub word line group is formed by local word lines WL<1601>, WL<1605>, . . . , WL<3193>, and WL<3197>, and the sub word line group shares Phdec<5> and PhdecN<5>. One sub word line group is formed by local word lines WL<1602>, WL<1606>, . . . , WL<3194>, and WL<3198>, and the sub word line group shares Phdec<6> and PhdecN<6>. One sub word line group is formed by local word lines WL<1603>, WL<1607>, . . . , WL<3195>, and WL<3199>, and the sub word line group shares Phdec<7> and PhdecN<7>.
One local bit line and one sub word line group have a correspondence, and a memory cell is formed at an intersection of the local bit line and each corresponding local word line. For example, a local bit line BL0 corresponds to local word lines WL<0>, WL<4>, . . . , WL<1592>, and WL<1596>, and there is a memory cell at an intersection of the local bit line BL0 and the local word line WL<0>, there is a memory cell at an intersection of the local bit line BL0 and WL<4>, . . . , and there is a memory cell at an intersection of the local bit line BL0 and WL<1596>.
The bit line selector Se of the local bit line receives a sub word line drive signal of a corresponding sub word line group, and the precharge switch Eq of the local bit line receives a sub word line drive complementary signal of the corresponding sub word line group, e.g., a control signal of the bit line selector Se of the local bit line BL0 being Sel<0>=Phdec<0> and a control signal of the precharge switch Eq of the local bit line BL0 being Eq<0>=PhdecN<0>.
In some embodiments, as shown in
In other words, local word lines WL<0>, WL<4>, . . . , and WL<1596> in each of sub array tiles Sub Mat0, Sub Mat1, . . . , and Sub Mat19 share the sub word line drive signal Phdec<0> and the sub word line drive complementary signal PhdecN <0>.
Specifically, the local word line WL<0> in each of the sub array tiles Sub Mat0, Sub Mat1, . . . , and Sub Mat19 is connected to a common bit line Common WL0, the local word line WL<4> in each of the sub array tiles Sub Mat0, Sub Mat1, . . . , and Sub Mat19 is connected to a common bit line Common WL4, . . . , and the local word line WL<1596> in each of the sub array tiles Sub Mat0, Sub Mat1, . . . , and Sub Mat19 is connected to a common bit line Common WL1596. However, the common bit lines Common WL0, Common WL4, . . . , and Common WL1596 share the sub word line drive signal Phdec<0> and the sub word line drive complementary signal PhdecN<0>.
In addition, the bit line selector Se of the first local bit line BL0 in each storage region in each sub array tile receives the sub word line drive signal Phdec<0>, and the precharge switch Eq of the local bit line BL0 in each storage region in each sub array tile receives the sub word line drive complementary signal PhdecN<0>.
In some embodiments, as shown in
Referring to
The decoding unit 21 is configured to decode the row address signal to generate main word line drive signals, namely, GrDec<399:0>, sub word line drive signals Phdec<7:0>, and sub word line drive complementary signals PhdecN<7:0> that are of each common word line.
The sub word line driver unit 22 is coupled to one common word line, and is configured to: receive, and enable or disable the coupled common word line based on, a corresponding main word line drive signal, a corresponding sub word line drive signal, and a corresponding sub word line drive complementary signal.
The main word line drive signal is configured to select one main word line group from both the first storage layer group and the second storage layer group, and the sub word line drive signal and the sub word line drive complementary signal are configured to select one common word line from the selected main word line group in the first storage layer group, or select one common word line from the selected main word line group in the second storage layer group.
For example, it is assumed that the main word line drive signals GrDec<0>=0, and GrDec<1> to GrDec<399>=1 (it indicates “selected” when the main word line drive signal is at a low level, and it indicates “not selected” when the main word line drive signal is at a high level), the sub word line drive signals Phdec<0>=1, and Phdec<1> to Phdec<7>=0, and the sub word line drive complementary signals PhdecN<0>=0, and PhdecN<1> to PhdecN<7>=1. In this case, the common bit line Common WL<0> is selected, that is, WL<0> in each of the sub array tiles Sub Mat0, Sub Mat1, . . . , and Sub Mat19 is selected (enabled). In addition, for each storage region of each of the sub array tiles Sub Mat0, Sub Mat1, . . . , and Sub Mat19 (because
In some embodiments, referring to
Control terminals of both the first switching transistor 301 and the second switching transistor 302 receive the main word line drive signal Grdec, a first terminal of the first switching transistor 301 receives the sub word line drive signal Phdec, a second terminal of the first switching transistor 301, a first terminal of the second switching transistor 302, and a first terminal of the third switching transistor 303 are all connected to the common word line Common WL, both a second terminal of the second switching transistor 302 and a second terminal of the third switching transistor 303 are connected to a power terminal, and a control terminal of the third switching transistor 303 receives the sub word line drive complementary signal PhdecN.
It should be noted that the power terminal may be a ground terminal, the first switching transistor 301 is P-type doped, and both the second switching transistor 302 and the third switching transistor 303 are N-type doped.
In this way, in a case, if Grdec-0, it indicates that a main word line group in which the common word line is located is selected, and the first switching transistor 301 is turned on. If Phdec=1, it indicates that the common word line is selected, and in this case, the common word line Common WL is at a high level (namely, selected/enabled), and a transistor in a connected memory cell is enabled. In another case, if Grdec=0 and Phdec=0, it indicates that although the main word line group in which the common word line is located is selected, the common word line is not selected, the common word line Common WL is at a low level, and the transistor in the connected memory cell is not enabled. In still another case, if Grdec=1, it indicates that the entire main word line group in which the common word line is located is not selected, the first switching transistor 301 is not turned on, the common word line Common WL is at a low level, and the transistor in the connected memory cell is not enabled.
In addition, the third switching transistor 303 is configured to quickly disable a corresponding common word line after the common word line is selected and a corresponding operation is performed.
In conclusion, this embodiment of the present disclosure provides the three-dimensional memory. The first chip and the second chip are included in the three-dimensional memory. The first chip and the second chip are stacked in the third direction, and are connected in a hybrid bonding manner. The first chip is mainly utilized to manufacture the memory array (Core), which is specifically divided into multiple memory array tiles (Mat) for better control and management. The second chip is mainly utilized to manufacture the peripheral control region (Periphery), the sense amplification region, and the like. In the first chip, multiple sub array tiles sequentially arranged in the second direction are included in each memory array tile, multiple storage regions sequentially stacked in the third direction are included in each sub array tile, and two storage layer groups arranged in the first direction are included in each storage region. Multiple local bit lines are included in each storage layer group, one common bit line is separately disposed on the two sides of each storage layer group in the first direction, each local bit line is coupled to the common bit line on one side through the respective bit line selector, and each local bit line is coupled to the common bit line on the other side through the respective precharge switch. In addition, the bit line selector works based on the sub word line drive signal, and the precharge switch works based on the sub word line drive complementary signal. In this way, the word line information is reused in this embodiment of the present disclosure to control the working states of the precharge switch Eq and the bit line selector Se of the local bit line. Therefore, although the precharge switch Eq and the bit line selector Se are additionally introduced into the three-dimensional memory, it is unnecessary to additionally introduce control information and redundant decoding logic, thereby improving control efficiency and omitting a redundant component.
In another embodiment of the present disclosure, reference is made to
As shown in
In S501, a command address signal is received, and a row address signal in the command address signal is decoded to generate multiple main word line drive signals, multiple sub word line drive signals, and multiple sub word line drive complementary signals.
In S502, whether a corresponding bit line selector is to connect a connected local bit line to a connected common bit line is controlled based on each sub word line drive signal.
In S503, whether a corresponding precharge switch is to connect a connected local bit line to a connected common bit line is controlled based on each sub word line drive complementary signal.
In some embodiments, referring to
Each sub word line group has a sub word line drive signal and a sub word line drive complementary signal; and the method further includes the steps as follows.
The sub word line drive signal of the sub word line group is transmitted to the bit line selector of the local bit line corresponding to the sub word line group.
The sub word line drive complementary signal of the sub word line group is transmitted to the precharge switch of the local bit line corresponding to the sub word line group.
In some embodiments, the local word lines in each sub array tile are numbered sequentially and independently, and the identically numbered local word lines in different sub array tiles are electrically connected to the same common word line, and share the same sub word line drive signal and the same sub word line drive complementary signal; and in the memory array tiles, the common word lines are numbered in the first direction, and one main word line group is formed by N consecutively numbered common word lines.
Two storage layer groups in each of the storage regions are sequentially referred to as a first storage layer group and a second storage layer group in the first direction; and the method further includes the steps as follows.
One main word line group is selected from both the first storage layer group and the second storage layer group based on the main word line drive signals.
One common word line is selected from the selected main word line group in the first storage layer group or the selected main word line group in the second storage layer group based on the sub word line drive signal and the sub word line drive complementary signal.
The selected common word line is enabled, and an operation indicated by the command address signal is performed.
In this way, word line information is reused in this embodiment of the present disclosure to control working states of the precharge switch Eq and the bit line selector Se of the local bit line. Therefore, although the precharge switch Eq and the bit line selector Se are additionally introduced into a three-dimensional memory, it is unnecessary to additionally introduce control information and redundant decoding logic, thereby improving control efficiency and omitting a redundant component.
In still another embodiment of the present disclosure, an electronic device is further provided. The memory shown in
Referring to
It should be noted that in this specification, the terms “include”, “comprise”, or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or apparatus including a series of elements includes not only those elements but also other elements that are not expressly listed, or further includes elements inherent to such a process, method, article, or apparatus. An element preceded by “includes a . . . ” does not, without more constraints, preclude the presence of additional identical elements in the procedure, method, article, or apparatus including the element.
The sequence numbers of the foregoing embodiments of the present disclosure are merely for the purpose of description, and are not intended to indicate priorities of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure may be randomly combined when there is no conflict, to obtain new method embodiments. The features disclosed in the several product embodiments provided in the present disclosure may be randomly combined when there is no conflict, to obtain new product embodiments. The features disclosed in the several method or device embodiments provided in the present disclosure may be randomly combined when there is no conflict, to obtain new method embodiments or new device embodiments.
The foregoing descriptions are merely specific implementations of the present disclosure, but are not intended to limit the protection scope of the present disclosure. Any variation or replacement readily figured out by a person skilled in the art within the technical scope disclosed in the present disclosure shall fall within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202311869141.2 | Dec 2023 | CN | national |
This application is a continuation of International Patent Application No. PCT/CN2024/126301 filed on Oct. 22, 2024, which claims priority to Chinese Patent Application No. 202311869141.2 filed on Dec. 29, 2023. The disclosures of the above-referenced applications are hereby incorporated by reference in their entirety.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2024/126301 | Oct 2024 | WO |
| Child | 18970679 | US |
