Patent Application
20210035644
The invention relates to a memory apparatus and a data access method for a memory, and more particularly, to a memory apparatus capable of increasing speed and a data access method for a memory.
With the advancement of electronic technology, electronic products have become an important tool in everyday life. In an electronic apparatus, the access speed of the memory apparatus therein may affect the response speed of the electronic apparatus. Referring to
When a data access operation is performed on the memory cell 100, a reset operation, a set operation, or a read operation may be performed for the memory cell 100 by applying a bias voltage to the phase change material layer PCL. In particular, the reset and set operations are used to change the resistance value provided by the phase change material layer PCL. In
In any case, as may be seen from
The invention provides a memory apparatus and a data access method for a memory, which may effectively improve the erase speed of a memory cell.
The data access method for a memory of the invention includes the following steps.
A data erase command is received for performing a data erase operation. During the data erase operation: a selected memory cell block in the memory is set according to the data erase command, a flag memory cell corresponding to the selected memory cell block is provided, a data in the flag memory cell is erased according to the data erase command, and a data in a plurality of selected memory cells in the selected memory cell block is kept unchanged.
The memory apparatus of the invention includes a plurality of memory cell blocks, a plurality of flag memory cells, and a controller. The flag memory cells respectively correspond to the memory cell blocks. The controller is coupled to the memory cell blocks and the flag memory cells and set to receive a data erase command to perform a data erase operation; and, during the data erase operation, a selected memory cell block in the memory cell blocks is set according to the data erase command; and, according to the data erase command, a data in the flag memory cell corresponding to the selected memory cell block is erased, and a data in the plurality of selected memory cells in the selected memory cell block is kept unchanged.
Based on the above, in the invention, when the data erase operation for the selected memory cell block is performed, the erase operation is performed only for the flag memory cell corresponding to the selected memory cell block, and a physical data erase operation is not performed for the selected memory cell in the selected memory cell block. In this way, the time required for the data erase operation may be greatly reduced, the power consumed may be reduced, and the overall effect of the memory may be improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are not intended to limit the scope of the invention.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
Please refer to
Next, in step S330, a flag memory cell corresponding to the selected memory cell block is provided, and when the erase operation is performed for the selected memory cell block, in step S330, a physical erase operation is performed only for the flag memory cell, and the physical erase operation is not performed for a plurality of selected memory cells in the selected memory cell block, and a data in the selected memory cells is kept unchanged.
As may be seen from the above description, in the present embodiment, when an erase operation is performed for a plurality of selected memory cells in the selected memory cell block, a physical erase operation only needs to be performed for a single flag memory cell, and a physical erase operation does not need to be performed for all of the selected memory cells in the selected memory cell block. It takes 100 nanoseconds to perform a physical erase operation (reset operation) for a single memory cell, and a single flag memory cell corresponds to a selected memory cell block with 4K bits, for example. When a comprehensive erase operation is performed for memories respectively with 4K bits, 32K bits, and 64K bits, the time required for the practice of the present embodiment and the conventional method may be as shown in Table 1 below:
As is clear from Table 1, the time required for the memory to perform the erase operation may be greatly reduced by the method of an embodiment of the invention.
Referring to
In detail, step S420 is used to obtain the instruction data bit recorded in the flag memory cell corresponding to the read selected memory cell block. In particular, the instruction data bit may be used to instruct whether the corresponding elected memory cell block is in an erased state. For example, when the selected memory block is in the erased state, the instruction data bit may be a first logic level. In contrast, when the selected memory block is in a non-erased state, the instruction data bit may be a second logic level, wherein the first logic level and the second logic level are complementary. In step S430, an operation (for example, a logic operation) with each of the read data bits may be performed via the instruction data bit, the read data bits are masked when the instruction data bit is the first logic level, and all of the final read data bits are changed to the erased state. In contrast, when the instruction data bit is the second logic level, the final read data bits are made the same as the read data bits.
In the present embodiment, the first logic level may be logic 1, the second level may be logic 0, and the logic operation may be a logic OR operation. In another embodiment of the invention, the first logic level may be logic 0, the second level may be logic 1, and the logic operation may be a logic AND operation.
Referring to
In the present embodiment, the flag memory cell CF0 may be disposed in the selected memory cell block 510, or may be disposed at any position outside the selected memory cell block 510 without specific limitation. The flag memory cell CF0 is disposed in the memory and has the same hardware architecture as any of the selected memory cells C0 to C63.
In addition, the selected memory cell block 510 of the present embodiment has a selected memory cell of 64 bits, which is merely an illustrative example. The number of bits included in the selected memory block 510 may be determined by the designer without limitation.
Referring to
In the present embodiment, the memory cell array 610 may be formed by a resistive memory cell, a flash memory cell, a phase change memory cell, or any other form of non-volatile memory cell. The controller 620 may be designed by a hardware description language (HDL) or any other design methods of a digital circuit known to those having ordinary skill in the art, and is a hardware circuit implemented by a field programmable gate array (FPGA), complex programmable logic device (CPLD), or application-specific integrated circuit (ASIC). The sense amplifier 630 may then be constructed using any sense amplifier known to those having ordinary skill in the art without specific limitation.
For details of the implementation of the operation circuit 640, please refer to the schematics of different embodiments of the operation circuit respectively shown in
The OR gates OR1 to ORM respectively receive a plurality of read data S0 to SM and collectively receive an instruction data bit BF1. The OR gates OR1 to ORM also respectively generate a plurality of final read data bits D0 to DM. In the present embodiment, when the memory cell block corresponding to the instruction data bit BF1 is in the erased state, the instruction data bit BF1 is logic 1. In this case, the OR gates OR1 to ORM mask the read data S0 to SM according to the instruction data bit BF1 and change all of the final read data bits D0 to DM to logic 1 (erased state). In contrast, when the memory cell block corresponding to the instruction data bit BF1 is in the non-erased state, the instruction data bit BF1 is logic 0. In this case, the OR gates OR1 to ORM respectively transmit the read data S0 to SM to generate the final read data bits D0 to DM. That is to say, the read data S0 to SM are respectively equal to the final read data bits D0 to DM.
In
Based on the above, in the invention, a flag memory cell is disposed corresponding to each memory cell block, and the erased state of the corresponding memory cell block is recorded via the flag memory cell. In this way, when the selected memory cell block is erased, an erase operation may be performed only for the corresponding flag memory cell, thereby effectively saving the time taken by the memory cell erase operation and improving memory access efficiency. Moreover, in an embodiment of the invention, the number of times the memory cell is physically erased may be reduced, thus increasing the life of the memory.
Although the invention has been described with reference to the above embodiments, it will be apparent to one of ordinary skill in the art that modifications to the described embodiments may be made without departing from the spirit of the invention. Accordingly, the scope of the invention is defined by the attached claims not by the above detailed descriptions.
