Patent Application
20240290386
The present disclosure claims priority of Chinese Patent Application No. 202310187788.0, filed on Feb. 28, 2023, the entire contents of which are hereby incorporated by reference in its entirety.
The present disclosure relates to the field of semiconductor manufacturing technologies, and in particular to a memory block and a buried layer manufacturing method thereof.
Three-dimensional (3D) memory arrays are a new type of electronic devices, which may include, for example, a NOR flash memory array, a NAND flash memory array, a dynamic random-access memory (DRAM) array, etc. However, in the memory array of the three-dimensional architecture, for a drain region as a bit line (BL) and a source region as a source line (SL), the source region and the drain region are made of semiconductor materials with doping, whose electrical conductivity is weak and electrical resistance is large, which greatly affects the speed of read (RD), program (PGM), and other operations performed by the memory block.
The present disclosure provides a memory block and a buried layer manufacturing method thereof, which is intended to solve the problem that existing 3D memory arrays have poor conductivity and high resistance in the source and drain regions, the problem resulting in greatly affecting the speed of the block in performing operations such as reading and writing (RD), programming (PGM), etc.
To solve the above technical problem, the present disclosure provides a memory block, including: a memory array, including: a plurality of columns of semiconductor stacked strip structures that are spaced apart along a row direction; wherein each column of stacked strip structure extends along a column direction and includes at least one drain region semiconductor strip, at least one channel semiconductor strip, and at least one source region semiconductor strip that are stacked along a height direction; each drain region semiconductor strip and/or each source region semiconductor strip in each column of semiconductor stacked strip structure includes a low-resistance conductive structure.
In some embodiments, the memory array includes a plurality of memory cells distributed in a three-dimensional array; wherein the memory array includes a plurality of memory subarray layers sequentially stacked along the height direction, and each memory subarray layer includes a drain region semiconductor layer, a channel semiconductor layer, and a source region semiconductor layer stacked along the height direction; in each memory subarray layer, the drain region semiconductor layer includes a plurality of drain region semiconductor strips spaced apart along the row direction, each drain region semiconductor strip extending along the column direction; the channel semiconductor layer includes a plurality of channel semiconductor strips spaced apart along the row direction, each channel semiconductor strip extending along the column direction; the source region semiconductor layer includes a plurality of source region semiconductor strips spaced apart along the row direction, each source region semiconductor strip extending along the column direction; the drain region semiconductor strips, the channel semiconductor strips, and the source region semiconductor strips that are in a same column are stacked to form a corresponding column of semiconductor stacked strip structure.
In some embodiments, each drain region semiconductor strip and/or each source region semiconductor strip in each column of semiconductor stacked strip structure at a non-edge position includes the low-resistance conductive structure.
In some embodiments, each column of semiconductor stacked strip structure at a non-edge position includes a first semiconductor substructure, a second semiconductor substructure, and an insulating isolation structure arranged between the first semiconductor substructure and the second semiconductor substructure; each drain region semiconductor strip in the column of semiconductor stacked strip structure at the non-edge position is divided into a first drain region semiconductor sub-strip and a second drain region semiconductor sub-strip; each channel semiconductor strip in the column of semiconductor stacked strip structure at the non-edge position is divided into a first channel semiconductor sub-strip and a second channel semiconductor sub-strip; each source region semiconductor strip in the column of semiconductor stacked strip structure at the non-edge position is divided into a first source region semiconductor sub-strip and a second source region semiconductor sub-strip.
In some embodiments, each of the first drain region semiconductor sub-strip and the second drain region semiconductor sub-strip includes a first drain region semiconductor layer structure, a second drain region semiconductor layer structure, and a third drain region semiconductor layer structure; the second drain region semiconductor layer structure is arranged between the first drain region semiconductor layer structure and the third drain region semiconductor layer structure; the first drain region semiconductor layer structure and the third drain region semiconductor layer structure are each of a silicon semiconductor layer structure, and the second drain region semiconductor layer structure is of a silicon germanium semiconductor layer structure; and/or each of the first source region semiconductor sub-strip and the second source region semiconductor sub-strip includes a first source region semiconductor layer structure, a second source region semiconductor layer structure, and a third source region semiconductor layer structure; the second source region semiconductor layer structure is arranged between the first source region semiconductor layer structure and the third source region semiconductor layer structure; the first source region semiconductor layer structure and the third source region semiconductor layer structure are each of a silicon semiconductor layer structure, and the second source region semiconductor layer structure is of a silicon germanium semiconductor layer structure.
In some embodiments, a length of the second drain region semiconductor layer structure in the row direction is less than a length of the first drain region semiconductor layer structure and a length of the third drain region semiconductor layer structure in the row direction, to define a drain region filling space between the first drain region semiconductor layer structure, the second drain region semiconductor layer structure, and the third drain region semiconductor layer structure; a drain region low-resistance conductive layer structure is formed in the drain region filling space, and the low-resistance conductive structure in each of the first drain region semiconductor sub-strip and the second drain region semiconductor sub-strip includes the drain region low-resistance conductive layer structure; and/or a length of the second source region semiconductor layer structure in the row direction is less than a length of the first source region semiconductor layer structure and a length of the third source region semiconductor layer structure in the row direction, to define a source region filling space between the first source region semiconductor layer structure, the second source region semiconductor layer structure, and the third source region semiconductor layer structure; a source region low-resistance conductive layer structure is formed in the source region filling space, and the low-resistance conductive structure in each of the first source region semiconductor sub-stripe and the second source region semiconductor sub-strip includes the source region low-resistance conductive layer structure.
In some embodiments, the drain region low-resistance conductive layer structure and/or the source region low-resistance conductive layer structure is made of a high-conductivity material; the drain region low-resistance conductive layer structure or the source region low-resistance conductive layer structure includes a first conductive layer structure, a second conductive layer structure, a third conductive layer structure, a fourth conductive layer structure, and a fifth conductive layer structure; the first conductive layer structure is formed on a portion of an upper surface of the first drain region semiconductor layer structure or the first source region semiconductor layer structure, the second conductive layer structure is formed on a side of the second drain region semiconductor layer structure or the second source region semiconductor layer structure, the third conductive layer structure is formed on a portion of a lower surface of the third drain region semiconductor layer structure or the third source region semiconductor layer structure, the fourth conductive layer structure is formed on a side of the first drain region semiconductor layer structure or the first source region semiconductor layer structure, and the fifth conductive layer structure is formed on a side of the third drain region semiconductor layer structure or the third source region semiconductor layer; the first conductive layer structure, the second conductive layer structure, the third conductive layer structure, the fourth conductive layer structure, and the fifth conductive layer structure are made of a material including a metal silicide; or the drain region low-resistance conductive layer structure or the source region low-resistance conductive layer structure includes a first conductive layer structure, a second conductive layer structure, and a third conductive layer structure; the first conductive layer structure is formed on a portion of an upper surface of the first drain region semiconductor layer structure or the first source region semiconductor layer structure, the second conductive layer structure is formed on a side of the second drain region semiconductor layer structure or the second source region semiconductor layer structure, and the third conductive layer structure is formed on a portion of a lower surface of the third drain region semiconductor layer structure or the third source region semiconductor layer structure; each of the first conductive layer structure, the second conductive layer structure, and the third conductive layer structure includes at least a first low-resistance layer; the first low-resistance layer is made of a material including titanium nitride or tantalum nitride; or the drain region low-resistance conductive layer structure or the source region low-resistance conductive layer structure includes a conductive layer structure filled in the drain region filling space or the source region filling space, and the conductive layer structure is made of a material including a metal.
In some embodiments, each of the first conductive layer structure, the second conductive layer structure, and the third conductive layer structure further includes a second low-resistance layer, wherein the second low-resistance layer is attached to a surface of the first low-resistance layer; a material of the second low-resistance layer includes titanium or tantalum, or the material of the second low-resistance layer includes a combination layer of titanium and another metal, or a combination layer of tantalum and another metal.
In some embodiments, the first conductive layer structure and the third conductive layer structure are spaced apart from each other to define a first space configured to be filled with an insulating substance.
In some embodiments, the column of semiconductor stacked strip structure is etched into a stepped structure at an edge position, for leading out each drain region semiconductor strip and each source region semiconductor strip in the column of semiconductor stacked strip structure.
In some embodiments, adjacent two of the plurality of memory subarray layers include the drain region semiconductor layer, the channel semiconductor layer, the source region semiconductor layer, the channel semiconductor layer, and the drain region semiconductor layer, in a sequential cascade along the height direction, so as to share the same source region semiconductor layer; an interlayer isolation layer is arranged on every adjacent two of the plurality of memory subarray layers to be isolated from another two of the plurality of memory subarray layers.
To solve the above technical problem, the present disclosure further provides a memory cell, including: a drain region portion, a channel portion, and a source region portion stacked perpendicular to a substrate wherein a side of the drain region portion, the channel portion, and the source region portion is arranged with a gate portion, and the drain region portion and/or the source region portion is arranged with a low-resistance conductive structure.
In some embodiments, the drain region portion includes a first drain region semiconductor layer structure, a second drain region semiconductor layer structure, and a third drain region semiconductor layer structure; the second drain region semiconductor layer structure is arranged between the first drain region semiconductor layer structure and the third drain region semiconductor layer structure; the first drain region semiconductor layer structure and the third drain region semiconductor layer structure are each of a silicon semiconductor layer structure, and the second drain region semiconductor layer structure is of a silicon germanium semiconductor layer structure; and/or the source region portion includes a first source region semiconductor layer structure, a second source region semiconductor layer structure, and a third source region semiconductor layer structure; the second source region semiconductor layer structure is arranged between the first source region semiconductor layer structure and the third source region semiconductor layer structure; the first source region semiconductor layer structure and the third source region semiconductor layer structure are each of a silicon semiconductor layer structure, and the second source region semiconductor layer structure is of a silicon germanium semiconductor layer structure.
In some embodiments, a length of the second drain region semiconductor layer structure in a first direction is less than a length of the first drain region semiconductor layer structure and a length of the third drain region semiconductor layer structure in the first direction, to define a drain region filling space between the first drain region semiconductor layer structure, the second drain region semiconductor layer structure, and the third drain region semiconductor layer structure; a drain region low-resistance conductive layer structure is formed in the drain region filling space; and/or a length of the second source region semiconductor layer structure in the first direction is less than a length of the first source region semiconductor layer structure and a length of the third source region semiconductor layer structure in first row direction, to define a source region filling space between the first source region semiconductor layer structure, the second source region semiconductor layer structure, and the third source region semiconductor layer structure; a source region low-resistance conductive layer structure is formed in the source region filling space.
In some embodiments, the drain region low-resistance conductive layer structure and/or the source region low-resistance conductive layer structure is a low-resistance conductive layer structure made of a high-conductivity material; the low-resistance conductive layer structure includes a first conductive layer structure, a second conductive layer structure, a third conductive layer structure, a fourth conductive layer structure, and a fifth conductive layer structure; the first conductive layer structure is formed on a portion of an upper surface of the first drain region semiconductor layer structure or the first source region semiconductor layer structure, the second conductive layer structure is formed on a side of the second drain region semiconductor layer structure or the second source region semiconductor layer structure, the third conductive layer structure is formed on a portion of a lower surface of the third drain region semiconductor layer structure or the third source region semiconductor layer structure, the fourth conductive layer structure is formed on a side of the first drain region semiconductor layer structure or the first source region semiconductor layer structure, and the fifth conductive layer structure is formed on a side of the third drain region semiconductor layer structure or the third source region semiconductor layer; the first conductive layer structure, the second conductive layer structure, the third conductive layer structure, the fourth conductive layer structure, and the fifth conductive layer structure are made of a material including a metal silicide; or the low-resistance conductive layer structure includes a first conductive layer structure, a second conductive layer structure, and a third conductive layer structure; the first conductive layer structure is formed on a portion of an upper surface of the first drain region semiconductor layer structure or the first source region semiconductor layer structure, the second conductive layer structure is formed on a side of the second drain region semiconductor layer structure or the second source region semiconductor layer structure, and the third conductive layer structure is formed on a portion of a lower surface of the third drain region semiconductor layer structure or the third source region semiconductor layer structure; each of the first conductive layer structure, the second conductive layer structure, and the third conductive layer structure includes at least a first low-resistance layer; the first low-resistance layer is made of a material including titanium nitride or tantalum nitride; or the low-resistance conductive layer structure includes a conductive layer structure filled in the drain region filling space or the source region filling space, and the conductive layer structure is made of a material including a metal.
In some embodiments, each of the first conductive layer structure, the second conductive layer structure, and the third conductive layer structure further includes a second low-resistance layer, wherein the second low-resistance layer is attached to a surface of the first low-resistance layer; a material of the second low-resistance layer includes titanium or tantalum, or the material of the second low-resistance layer includes a combination layer of titanium and another metal, or a combination layer of tantalum and another metal.
To solve the above technical problem, the present disclosure further provides manufacturing method of a memory block, including: providing a semiconductor substrate; wherein the semiconductor substrate includes a substrate, and a plurality of columns of semiconductor stacked strip structures formed on the substrate; the plurality of columns of semiconductor stacked strip structures are spaced apart along a row direction, each column of semiconductor stacked strip structure extends along a column direction, and each column of semiconductor stacked strip structure includes at least one drain region semiconductor strip, at least one channel semiconductor strip, and at least one source region semiconductor strip stacked along a height direction; defining an isolation opening in each column of semiconductor stacked strip structure; wherein the isolation opening divides the column of semiconductor stacked strip structure into a first semiconductor substructure and a second semiconductor substructure; and defining a filling opening in a drain/source region semiconductor sub-strip in each of the first semiconductor substructure and the second semiconductor substructure through the isolation opening, and forming a low-resistance conductive structure in the filling opening.
In some embodiments, the providing a semiconductor substrate includes: providing the substrate; forming a plurality of memory subarray layers sequentially on the substrate along the height direction; wherein each memory subarray layer includes a drain region semiconductor layer, a channel semiconductor layer, and a source region semiconductor layer stacked along the height direction; and forming a first hard mask layer on the plurality of memory subarray layers, and defining a plurality of isolation wall holes and word line holes on the first hard mask layer and the plurality of memory subarray layers, for causing the drain region semiconductor layer of each memory subarray layer to be divided into a plurality of drain region semiconductor strips, the channel semiconductor layer of each memory subarray layer to be divided into a plurality of channel semiconductor strips, and the source region semiconductor layer of each memory subarray layer to be divided into a plurality of source region semiconductor strips, along the row direction; each of the plurality of drain region semiconductor strips, the plurality of channel semiconductor strips, and the plurality of source region semiconductor strips extends along the column direction, and a column of the drain region semiconductor strips, channel semiconductor strips, and source region semiconductor strips in the plurality of memory subarray layers constitutes a corresponding column of semiconductor stacked strip structure.
In some embodiments, each of the drain region semiconductor and the source region semiconductor is denoted as a drain/source region semiconductor layer, and formation of the drain/source region semiconductor layer includes: forming a first drain/source semiconductor sublayer by epitaxial growth; wherein the first drain/source semiconductor sublayer is a semiconductor sublayer made of silicon; forming a second drain/source semiconductor sublayer by epitaxial growth on the first drain/source semiconductor sublayer; wherein the second drain/source semiconductor sublayer is a semiconductor sublayer made of silicon germanium; and forming a third drain/source semiconductor sublayer by epitaxial growth on the second drain/source semiconductor sublayer; wherein the third drain/source semiconductor sublayer is a semiconductor sublayer made of silicon; wherein after the plurality of memory subarray layers are divided into the multiple columns of semiconductor stacked strip structures along the row direction, the first drain/source semiconductor sublayer is divided into a plurality of columns of first drain/source semiconductor sublayer strips, the second drain/source semiconductor sublayer is divided into a plurality of columns of second drain/source semiconductor sublayer strips, and the third drain/source semiconductor sublayer is divided into a plurality of columns of third drain/source semiconductor sublayer strips; each drain region semiconductor strip and/or each source region semiconductor strip in the column of semiconductor stacked strip structure includes a corresponding first drain/source semiconductor sublayer strip, second drain/source semiconductor sublayer strip, and third drain/source semiconductor sublayer strip; each of the first drain/source semiconductor sublayer strip, second drain/source semiconductor sublayer strip, and third drain/source semiconductor sublayer strip is denoted as a drain/source semiconductor sublayer strip; after the isolation opening is defined in each column of semiconductor stacked strip structure at a non-edge position to divide the column of semiconductor stacked strip structure into the first semiconductor substructure and the second semiconductor substructure, each drain/source semiconductor sublayer strip and/or each drain/source region semiconductor sub-strip in the first semiconductor substructure includes a corresponding first drain/source semiconductor layer structure, a second drain/source semiconductor layer structure, and a third drain/source semiconductor layer structure.
In some embodiments, the defining a filling opening in a drain/source region semiconductor sub-strip in each of the first semiconductor substructure and the second semiconductor substructure through the isolation opening, and forming a low-resistance conductive structure in the filling opening include: in the isolation opening, replacing each of a first sacrificial semiconductor layer and a second sacrificial semiconductor layer in each of the first semiconductor substructure and the second semiconductor substructure with an insulating isolation layer through a first recessed groove, replacing a portion of the second drain/source semiconductor layer structure in each of the first semiconductor substructure and the second semiconductor substructure with a protective dielectric layer, and replacing a portion of the channel semiconductor sub-strip in each of the first semiconductor substructure and the second semiconductor substructure with an insulating isolation layer; removing the protective dielectric layer in the first recessed groove in each of the first semiconductor substructure and the second semiconductor substructure, and deepening the first recessed groove to form a drain/source region filled space; and depositing a high-conductivity material in a drain/source region filling space to form the low-resistance conductive structure.
In some embodiments, in the isolation opening, the replacing each of a first sacrificial semiconductor layer and a second sacrificial semiconductor layer in each of the first semiconductor substructure and the second semiconductor substructure with an insulating isolation layer through a first recessed groove, replacing a portion of the second drain/source semiconductor layer structure in each of the first semiconductor substructure and the second semiconductor substructure with a protective dielectric layer, and replacing a portion of the channel semiconductor sub-strip in each of the first semiconductor substructure and the second semiconductor substructure with an insulating isolation layer include: in the isolation opening, etching the portion of each of the first sacrificial semiconductor layer, the second sacrificial semiconductor layer, and the second drain/source semiconductor layer structure in each of the first semiconductor substructure and the second semiconductor substructure to remove the portion of each of the first sacrificial semiconductor layer, the second sacrificial semiconductor layer, and the second drain/source semiconductor layer structure; forming the protective dielectric layer in the first recessed groove in the removed portion of each of the first sacrificial semiconductor layer, the second sacrificial semiconductor layer, and the second drain/source semiconductor layer structure; removing the protective dielectric layer in the first recessed groove corresponding to each of the first sacrificial semiconductor layer and the second sacrificial semiconductor layer to expose a residual part of the first sacrificial semiconductor layer and the second sacrificial semiconductor layer; removing the residual part of the first sacrificial semiconductor layer and the second sacrificial semiconductor layer; and performing deposition in a region where the removed first sacrificial semiconductor layer and the second sacrificial semiconductor layer are located to fill with an insulating material, for replacing the first sacrificial semiconductor layer and the second sacrificial semiconductor layer with the insulating isolation layer, and forming the insulating isolation layer on a sidewall of the isolation opening.
In some embodiments, in the isolation opening, the replacing each of a first sacrificial semiconductor layer and a second sacrificial semiconductor layer in each of the first semiconductor substructure and the second semiconductor substructure with an insulating isolation layer through a first recessed groove, replacing a portion of the second drain/source semiconductor layer structure in each of the first semiconductor substructure and the second semiconductor substructure with a protective dielectric layer, and replacing a portion of the channel semiconductor sub-strip in each of the first semiconductor substructure and the second semiconductor substructure with an insulating isolation layer further include: removing the insulating isolation layer formed on the sidewall of the isolation opening; etching the portion of the channel semiconductor sub-strip in each of the first semiconductor substructure and the second semiconductor substructure to remove the portion of the channel semiconductor sub-strip, and defining a second recessed groove in the removed portion of the channel semiconductor sub-strip; and performing deposition in a region where the second recessed groove is located to fill with an insulating material, and forming the insulating isolation layer in the second recessed groove and on the sidewall of the isolation opening.
In some embodiments, the removing the protective dielectric layer in the first recessed groove in each of the first semiconductor substructure and the second semiconductor substructure, and deepening the first recessed groove to form a drain/source region filled space include: removing the insulating isolation layer formed on a sidewall of the isolation opening; removing the protective dielectric layer in the first recessed groove; and continuing to etching the portion of each of the first semiconductor substructure and the second semiconductor substructure within the first recessed groove to remove the portion of the second drain/source region semiconductor layer structure, deepening the first recessed groove, and forming the drain/source region filling space.
In some embodiments, the depositing a high-conductivity material in a drain/source region filling space to form the low-resistance conductive structure includes: depositing a metal on an inner surface of the drain/source filled space and on a sidewall of the isolation opening; performing a heat treatment to react the metal with a silicon material of the drain/source region semiconductor sub-strip in each of the first semiconductor substructure and the second semiconductor substructure to form a metal-silicide layer; wherein the metal remains on a sidewall of the insulating isolation layer; and removing the metal remaining on the sidewall of the insulating isolation layer, and retaining the metal-silicide layer to form the low-resistance conductive structure; wherein the low-resistance conductive structure includes a first conductive layer structure, a second conductive layer structure, a third conductive layer structure, a fourth conductive layer structure, and a fifth conductive layer structure; the first conductive layer structure is formed on a portion of an upper surface of the first drain region semiconductor layer structure or the first source region semiconductor layer structure, the second conductive layer structure is formed on a side of the second drain region semiconductor layer structure or the second source region semiconductor layer structure, the third conductive layer structure is formed on a portion of a lower surface of the third drain region semiconductor layer structure or the third source region semiconductor layer structure, the fourth conductive layer structure is formed on a side of the first drain region semiconductor layer structure or the first source region semiconductor layer structure, and the fifth conductive layer structure is formed on a side of the third drain region semiconductor layer structure or the third source region semiconductor layer structure.
In some embodiments, the depositing a high-conductivity material in a drain/source region filling space to form the low-resistance conductive structure includes: depositing a first low-resistance layer on an inner surface of the drain/source region filling space; wherein a material of the first low-resistance layer includes titanium nitride and tantalum nitride; etching in a direction from the isolation opening toward a corresponding one of the first semiconductor substructure and the second semiconductor substructure to remove titanium nitride or tantalum nitride from the sidewall of the isolation opening, for forming the low-resistance conductive structure; wherein the low-resistance conductive layer structure includes a first conductive layer structure, a second conductive layer structure, and a third conductive layer structure; the first conductive layer structure is formed on a portion of an upper surface of the first drain region semiconductor layer structure or the first source region semiconductor layer structure, the second conductive layer structure is formed on a side of the second drain region semiconductor layer structure or the second source region semiconductor layer structure, and the third conductive layer structure is formed on a portion of a lower surface of the third drain region semiconductor layer structure or the third source region semiconductor layer structure; each of the first conductive layer structure, the second conductive layer structure, and the third conductive layer structure includes the first low-resistance layer.
In some embodiments, after the first low-resistance layer is deposited on the inner surface of the drain/source region filling space, a second low-resistance layer is deposited on the first low-resistance layer and on the sidewall of the isolation opening; wherein a material of the second low-resistance layer includes titanium or tantalum, a combination layer of titanium and another metal, or a combination layer of tantalum and another metal; the second low-resistance layer on the sidewall of the isolation opening is removed by etching in the direction from the isolation opening toward a corresponding one of the first semiconductor substructure and the second semiconductor substructure, for forming the low-resistance conductive structure; wherein each of the first conductive layer structure, the second conductive layer structure, and the third conductive layer structure further includes and the second low-resistance layer.
In some embodiments, the depositing a high-conductivity material in a drain/source region filling space to form the low-resistance conductive structure includes: depositing a metal within the drain/source region filling space and on a sidewall of the isolation opening; and removing the metal on the sidewall of the isolation opening by etching in a direction from the isolation opening toward a corresponding one of the first semiconductor substructure and the second semiconductor substructure to form the low-resistance conductive structure; wherein the low-resistance conductive structure includes a conductive layer structure filled in the drain/source region filling space, and the conductive layer structure is made of a material including a metal.
In some embodiments, the depositing a high-conductivity material in a drain/source region filling space to form the low-resistance conductive structure further includes: filling an insulating material in a first space between the first conductive layer structure and the third conductive layer structure, and in the isolation opening to form the insulating isolation layer.
Compared to the related art, the beneficial effect of the present disclosure: the present disclosure provides a memory block, including: a memory array, including: a plurality of columns of semiconductor stacked strip structures that are spaced apart along a row direction; wherein each column of stacked strip structure extends along a column direction and includes at least one drain region semiconductor strip, at least one channel semiconductor strip, and at least one source region semiconductor strip that are stacked along a height direction; each drain region semiconductor strip and/or each source region semiconductor strip in each column of semiconductor stacked strip structure includes a low-resistance conductive structure. The drain region semiconductor strip and the source region semiconductor strip having a low-resistance conductive structure have higher electron mobility, and thus higher conductivity and lower resistance, thereby enhancing the response speed of the storage block. In addition, due to the elevated electrical energy utilization, the array of drain/source connection terminals for voltage renewal in the memory block may be reduced or removed, thereby enhancing the space utilization of the memory block and saving process steps and material costs.
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following is a brief description of the drawings required for the description of the embodiments, and it will be obvious that the drawings in the following description are only some embodiments of the present disclosure, and that other drawings can be obtained from these drawings without creative work for those skilled in the art.
The technical solutions in embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, but not all of them. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of the present disclosure.
The terms “first”, “second”, and “third” in the present disclosure are intended for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, a feature defined with “first”, “second”, or “third” may explicitly or implicitly include at least one such feature. In the description of the present disclosure, “a plurality of” or “multiple” means at least two, e.g., two, three, etc., unless otherwise expressly and specifically limited. All directional indications (e.g., up, down, left, right, forward, backward . . . ) in the present disclosure are intended only to explain the relative position relationship, movement, etc., between components in a particular posture (as shown in the accompanying drawings), and if that particular posture is changed, the directional indications are changed accordingly. In addition, the terms “include” and “have”, and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus including a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to the process, method, product, or apparatus.
References herein to “embodiment” mean that particular features, structures, or characteristics described in connection with an embodiment may be included in at least one embodiment of the present disclosure. The presence of the phrase at various positions in the specification does not necessarily mean the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.
The present disclosure is described in detail below in conjunction with the accompanying drawings and embodiments.
Referring to
Referring to
As shown in
In each memory subarray layer 1a, the drain region semiconductor layer (D) includes multiple drain region semiconductor strips 11 spaced along a row direction X, each drain region semiconductor strip 11 extending along a column direction Y. The channel semiconductor layer (CH) includes multiple channel semiconductor strips 12 spaced along the row direction X, each channel semiconductor strip 12 extending along the column direction Y. The source region semiconductor layer (S) includes multiple source region semiconductor strips 13 spaced along the row direction X, each source region semiconductor strip 13 extending along the column direction Y. Each drain region semiconductor strip 11, channel semiconductor strip 12, and source region semiconductor strip 13 is a single-crystal semiconductor strip, respectively. It is understood by those skilled in the art that each drain region semiconductor strip 11, channel semiconductor strip 12, and source region semiconductor strip 13 may be a single-crystal semiconductor strip formed by processing the drain region semiconductor layer, channel semiconductor layer, and source region semiconductor layer formed by epitaxy, respectively. As shown in
As shown in
In the height direction Z, a projection of at least a part of each gate strip 2 coincides with a projection of a part of a corresponding channel semiconductor strip 12 in each memory subarray layer 1a on a projection plane. The projection plane is a plane defined by the height direction Z and the column direction Y, i.e., the projection plane extends along the height direction Z and the column direction Y. As shown in
In other words, it is understood by those skilled in the art that the memory array 1 includes multiple stacked structures 1b distributed along the row direction X, each stacked structure 1b extending along the column direction Y. Each stacked structure 1b includes drain region semiconductor strips 11, channel semiconductor strips 12, and source region semiconductor strips 13 stacked along the height direction. Each drain region semiconductor strip 11, channel semiconductor strip 12, and source region semiconductor strip 13 extends along the column direction Y. Multiple gate strips 2 spaced along the column direction Y are arranged on each of two sides of each stacked structure 1b, and each gate strip 2 extends along the height direction Z.
A projection of a part of each semiconductor strip structure coincides with a projection of a corresponding part of a corresponding gate strip 2 on the projection plane. In particular, a projection of a part of the channel semiconductor strip 12 in each semiconductor strip structure coincides with a projection of a part of a corresponding gate strip 2 on the projection plane. In this way, a part of the gate strip 2, a corresponding part of the channel semiconductor strip 12, a part of the drain region semiconductor strip 11 adjacent to the corresponding part of the channel semiconductor bar 12, and a part of the source region semiconductor strip 13 adjacent to the corresponding part of the channel semiconductor bar 12 are configured to form a memory cell. For example, as shown in
It will be understood by those skilled in the art that, a channel is required to be formed in a semiconductor region between the semiconductor drain region and the semiconductor source region; and the gate is arranged on a side of the semiconductor region between the semiconductor drain region and the semiconductor source region for constituting a semiconductor device. Therefore, as shown in
Therefore, as shown in
In the present disclosure, each drain region semiconductor strip 11 is a semiconductor strip of a first doping type, such as an N-type doped semiconductor strip. In some embodiments, each drain region semiconductor strip 11 serves as a bit line (BL) of a memory block.
Each channel semiconductor strip 12 is a semiconductor strip of a second doping type, such as a P-type doped semiconductor strip. In some embodiments, each channel semiconductor strip 12 serves as a well region of a memory cell.
Each source region semiconductor strip 13 is also a semiconductor strip of the first doping type, such as an N-type doped semiconductor strip. In some embodiments, each source region semiconductor strip 13 serves as a source line (SL) of the memory block.
Of course, it is understood by those skilled in the art that in other types of memory devices, each drain region semiconductor strip and each source region semiconductor strip may also be a P-type doped semiconductor strip, while each channel semiconductor strip 12 is an N-type doped semiconductor strip. The present disclosure does not limit thereto.
Referring further to
Referring together to
In each memory subarray layer 1a, the drain region semiconductor layer, the channel semiconductor layer, and the source region semiconductor layer include multiple drain region semiconductor strips 11, multiple channel semiconductor strips 12, and multiple source region semiconductor strips 13, respectively, spaced along the row direction X.
Two adjacent memory subarray layers 1a include a drain region semiconductor layer, a channel semiconductor layer, a source region semiconductor layer, a channel semiconductor layer, and a drain region semiconductor layer sequentially stacked to share the same source region semiconductor layer.
An interlayer isolation layer is arranged between every two memory subarray layers 1a to isolate from the other two memory subarray layers 1a. That is, an interlayer isolation layer is arranged between each two consecutive memory subarray layers 1a and another two consecutive memory subarray layers 1a, the another two consecutive memory subarray layers 1a being adjacent to the each two consecutive memory subarray layers 1a. For example, in the height direction Z, an interlayer isolation layer is arranged between the first/second memory subarray layers 1a and the third/fourth memory subarray layers 1a; another interlayer isolation layer is arranged between the third/fourth memory subarray layers 1a and the fifth/sixth memory subarray layers 1a, and so on. The first/second memory subarray layers mean the first memory subarray layer and the second memory subarray layer which share a common source region semiconductor layer, and the third/fourth memory subarray layers mean the third memory subarray layer and the fourth memory subarray layer which share another common source region semiconductor layer, while the fifth/sixth memory subarray layers mean the fifth memory subarray layer and the sixth memory subarray layer which share another common source region semiconductor layer. It is understood that the one interlayer isolation layer is disposed between the second memory subarray layer 1a and the third memory subarray layer 1a; and the other interlayer isolation layer is disposed between the fourth memory subarray layer 1a and the fifth memory subarray layer 1a.
Specifically, as shown in
In other words, in the present disclosure, each stacked structure 1b may include multiple stacked substructures, each stacked substructure including a drain region semiconductor strip 11, a channel semiconductor strip 12, a source region semiconductor strip 13, a channel semiconductor strip 12, and a drain region semiconductor strip 11 stacked sequentially along the height direction Z, thereby sharing the same source region semiconductor strip 13. In the stacked structure 1b, an interlayer isolation strip 14a is arranged between two adjacent stacked substructures to isolate them from each other. That is, in two adjacent memory subarray layers 1a, the drain region semiconductor strip 11, channel semiconductor strip 12, source region semiconductor strip 13, channel semiconductor strip 12, and drain region semiconductor strip 11 in the same column form a stacked substructure, such that two adjacent memory subarray layers 1a share a common source region semiconductor strip 13.
Referring further to
A region between two adjacent isolation walls 3 in the same column in the column direction Y is configured to define a word line hole 4. That is, any two adjacent isolation walls 3 in the same column, cooperating with two columns of semiconductor strip structures 1b (i.e., stacked structures 1b) on both sides thereof, may define multiple regions for the word line holes 4, and these regions may be processed such that corresponding word line holes 4 may be defined. That is, the multiple columns of drain region semiconductor strips 11, channel semiconductor strips 12, and source region semiconductor strips 13 extending along the column direction Y pass through the multiple rows of isolation walls 3 extending along the row direction X, to define the multiple word line holes 4 cooperating with the multiple isolation walls 3. Each word line hole 4 extends along the height direction Z.
Each word line hole 4 is configured to fill a gate material to form a corresponding gate strip 2. That is, a gate strip 2 is filled between two adjacent isolation walls 3 in the same column direction Y.
Referring together to
In addition, a projection of the gate portion 2′ at least partially coincides with a projection of the channel portion 12′ on a projection plane in the height direction Z. The projection plane is located on a side of the drain region portion 11′, the channel portion 12′, and the source region portion 13′, and extends along the height direction Z and the column direction Y.
As shown in
In addition, as shown in
Therefore, it will be understood by those skilled in the art that in the memory array 1 shown in
In addition, it should be noted that for the convenience of the accompanying drawings showing the storage structure portion 5′, the drain region portion 11′, the channel portion 12′, the source region portion 13′, the gate portion 2′, and the storage structure portion 5 shown in
It will be understood by those skilled in the art that, as above, the part of the gate strip 2 whose projection coincides with the projection of the adjacent channel semiconductor strip 12 on the above projection plane is configured as the control gate of the memory cell, such that the part of the gate strip 2 as the gate portion 2′ is the part whose projection coincides with the projection of the channel semiconductor 12 on the projection plane; the part of the channel semiconductor strip 12 whose projection coincides with the projection of the gate strip 2 on the above projection plane is the corresponding part of the channel semiconductor strip 12 as the well region, such that the part of the channel semiconductor strip 12 as the channel portion 12′ is the part of the channel semiconductor strip 12 whose projection coincides with the projection of the gate strip 2 on the projection plane; the parts of the drain region semiconductor strip 11 and the source region semiconductor strip 13 as the drain region portion 11′ and the source region portion 13′, i.e., the part of the drain region semiconductor strip 11 or the source region semiconductor strip 13 arranged above or below the channel portion 12′, are configured as the semiconductor drain region and the semiconductor source region, respectively.
Similarly, the storage structure portion 5′ is a part of the storage structure 5 disposed between the channel portion 12′ and the gate portion 2′.
Referring further to
Specifically, further referring to
For ease of understanding, it may be considered that the drain region portion 11′, the channel portion 12′, and the source region portion 13′ cooperate with the gate portion 2′ on the left side and the storage structure portion 5′ between them to form a memory cell (bit); the drain region portion 11′, the channel portion 12′, and the source region portion 13′ cooperate with the gate portion 2′ on the right side and the storage structure portion 5′ between them to form another memory cell (bit).
Therefore, returning to
In conjunction with
In other embodiments, in conjunction with
As shown in
In the present disclosure, by making each drain region semiconductor strip 11, channel semiconductor strip 12, and source region semiconductor strip 13 include multiple protrusions 15b that are raised toward the two sides, it is possible to increase the surface area of each drain region semiconductor strip 11, channel semiconductor strip 12, and source region semiconductor strip 13, thereby increasing the area of a corresponding region of the channel portion 12′ and the gate portion 2′ in each memory cell, thereby enhancing the performance of the memory block 10.
Specifically, the convex surface of the protrusion 15b away from the body structure 15a may be an arc or other form of convex surface, where the arc may include a columnar semicircular surface. The protrusions 15b of each column of drain region semiconductor strip 11, channel semiconductor strip 12, and source region semiconductor strip 13 form a columnar semicircle. The gate strip 2 corresponding to the protrusions 15b is arranged with a concave surface toward the drain region semiconductor strip 11, the channel semiconductor strip 12, and the source region semiconductor strip 13, and the concave surface is a curved surface corresponding to the convex surface of the protrusions 15b to ensure that the gate strip 2 matches the channel semiconductor strip 12 at the corresponding position.
In some embodiments, as shown in
Referring to
Therefore, with reference to
The first dielectric layer (first dielectric portion 51) and the second dielectric layer (second dielectric portion 53) may be made of an insulating material, such as silicon oxide. The charge-trapping layer (charge-trapping portion 52) may be made of a storage material with charge energy trapping properties, in particular, the charge-trapping layer may be made of silicon nitride. Therefore, the first dielectric layer (first dielectric portion 51), the charge-trapping layer (charge-trapping portion 52), and the second dielectric layer (second dielectric portion 53) form an ONO storage structure. Specifically, reference thereto may be made to a manufacturing method involving a memory block of a charge trapping storage structure in the following embodiments.
In other embodiments, referring to
Specifically, in conjunction with
Among them, the floating gate 54 may be made of polycrystalline silicon. The insulating dielectric may be made of an insulating material such as silicon oxide. Specifically, reference thereto may be made to a manufacturing method involving a memory block of a floating gate storage structure in the following embodiments.
In the memory cell of the charge trapping storage structure shown in
The ONO storage structure is characterized by the fact that the charges injected into can be fixed near an injection point, while the floating gate storage structure (e.g.,
That is, for the memory cell and memory block of the charge trapping storage structure shown in
In contrast, in the floating gate storage structure shown in
It will be understood by those skilled in the art that some parts of the insulating dielectric (e.g., the second insulating dielectric layer 85b mentioned above) are interconnected with each other, as long as it is possible to ensure that the floating gates 54 of each memory cell are independent of each other and that the surfaces of each floating gate 54 are wrapped with the insulating dielectric. Therefore, parts of the insulating dielectric (e.g., the second insulating dielectric layer 85b mentioned above) that wraps the floating gates 54 in the word line hole 4 may extend substantially in the height direction, thereby wrapping the floating gates 54 of each memory cell. Specifically, reference to the memory block 10 with a floating gate storage structure may be made to a manufacturing method involving a memory block of a floating gate storage structure in the following embodiments.
In addition, it will be understood by those skilled in the art that the storage structure 5 may be adopted with other types of storage structures, such as ferroelectric, variable resistance, or other types of capacitive storage structures.
In some embodiments, referring to
As above, the part of the gate strip 2 whose projection overlaps with the projection of the channel semiconductor strip 12 in an adjacent stacked structures 1b on the above projection plane is configured as the control gate of the corresponding memory cell. Therefore, each gate strip 2 is configured to form the control gate (CG) of multiple memory cells. As is known, the control gates of a row of memory cells need to be connected to a corresponding word line, through which a voltage is applied to the control gates of the row of the memory cells, thereby controlling the memory cells to perform various memory operations.
In the present disclosure, as shown in
Specifically, the word line of the same row may be an individual word line connected to the gate strip 2 in each word line hole 4 of the same row. Of course, the word lines of the same row may include multiple different types of word lines; the gate strips 2 in multiple word line holes 4 of the same row may each be connected to the multiple different types of word lines of the corresponding row. In some embodiments, as shown in
Specifically, the memory cells of the same row in the multiple memory subarray layers 1a are connected to the odd word line 8a of the corresponding row through the odd word line holes 4 of the same row, respectively; the others of the memory cells of the same row in the multiple memory subarray layers 1a are connected to the even word line 8b of the corresponding row through the even word line holes 4 of the same row, respectively. For example, a first part of the memory cells of the first row are connected to the odd word line 8a of the first row through the first word line hole 4, the third word line hole 4, the fifth word line hole 4 . . . , respectively; a second part of the memory cells of the first row are connected to the even word line 8b of the first row through the second word line hole 4, the fourth word line hole 4, the sixth word line hole 4 . . . , respectively. That is, the odd word line 8a of the word line of the same row is connected to multiple memory cells (the first part of the memory cells) in the multiple memory subarray layers 1a corresponding to the odd word line holes 4 of this row; the even word line 8b of the word line of the same row are connected to multiple memory cells (the second part of the memory cells) in the multiple memory subarray layers 1a corresponding to the even word line holes 4 of this row.
As above, each drain region semiconductor strip 11, channel semiconductor strip 12, and source region semiconductor strip 13 has odd word line holes 4 distributed on one side thereof and even word line holes 4 distributed on the other side thereof. Therefore, a part of the drain region semiconductor strip 11, channel semiconductor strip 12, and source region semiconductor strip 13 in each same column in each memory subarray layer 1a may cooperate with an odd gate strip 2 in an odd word line hole 4 on one side thereof and a storage structure arranged between the gate strip 2 and the drain region semiconductor strip 11, channel semiconductor strip 12, and source region semiconductor strip 13, to form a memory cell, i.e., a first memory cell; and may cooperated with an even word line hole 4 on the other side thereof and a storage structure 5 arranged therebetween, to form another memory cell, i.e., a second memory cell.
In other words, the gate strip 2 filled in each word line hole 4 may be configured to form a memory cell (bit) in conjunction with the drain region semiconductor strip 11, the channel semiconductor strip 12, the source region semiconductor strip 13, and the storage structure 5 on the left side in each memory subarray layer 1a; and may be configured to form another memory cell (bit), i.e., a second memory cell, in conjunction with the drain region semiconductor strip 11, the channel semiconductor strip 12, the source region semiconductor strip 13, and the storage structure 5 on the right side in each memory subarray layer 1a.
Therefore, for an odd word line hole 4, the left half or right half of each drain region semiconductor strip 11, channel semiconductor strip 12, and source region semiconductor strip 13 in the same column in each memory subarray layer 1a may cooperate with the corresponding gate strip 2 in the odd word line hole 4 to form a first memory cell. Specifically, in each memory subarray layer 1a, for each column of drain region semiconductor strip 11, channel semiconductor strip 12, and source region semiconductor strip 13: for example, word line holes 4 on the left side of the first column of drain region semiconductor strip 11, channel semiconductor strip 12, and source region semiconductor strip 13 counting from left to right are odd word line holes, and a part of the drain region semiconductor strip 11, channel semiconductor strip 12, and source region semiconductor strip 13 of that column cooperate with a gate strip 2 in a corresponding odd word line hole 4 on its left side for forming a first memory cell. Word line holes 4 on the right side of the second column of the drain region semiconductor strip 11, channel semiconductor strip 12, and source region semiconductor strip 13 counting from left to right are odd word line holes, and a part of the drain region semiconductor strip 11, channel semiconductor strip 12, and source region semiconductor strip 13 of this column cooperate with a gate strip 2 in a corresponding odd word line hole 4 on its right side also for forming a first memory cell.
Similarly, for an even word line hole 4, the other half of each drain region semiconductor strip 11, channel semiconductor strip 12, and source region semiconductor strip 13 in the same column in each memory subarray layer 1a may cooperate with a corresponding gate strip 2 in the even word line hole 4 to form a second memory cell. Specifically, in each memory subarray layer 1a, for each column of drain region semiconductor strip 11, channel semiconductor strip 12, and source region semiconductor strip 13: for example, word line holes 4 on the right side of the first column of drain region semiconductor strip 11, channel semiconductor strip 12, and source region semiconductor strip 13 from left to right are even word line holes, and a part of the drain region semiconductor strip 11, channel semiconductor strip 12, and source region semiconductor strip 13 of that column cooperate with a gate strip 2 in a corresponding even word line hole 4 on its right side for forming a second memory cell. Word line holes 4 on the left side of the second column of the drain region semiconductor strip 11, channel semiconductor strip 12, and source region semiconductor strip 13 from left to right are even word line holes, and a part of the drain region semiconductor strip 11, channel semiconductor strip 12, and source region semiconductor strip 13 of this column cooperate with a gate strip 2 in a corresponding even word line hole 4 on its left side also for forming a second memory cell.
Therefore, in the present disclosure, each gate strip 2 in the memory array 1 is connected to a corresponding word line, and the gate strips 2 in the same row are connected to the corresponding row of word line. The gate strips 2 in the odd word line hole 4 in the same row are connected to the odd word lines 8a in the corresponding row of word line, and the gate strips 2 in the even word line hole 4 in the same row are connected to the even word lines 8b in the corresponding row of word line. In other words, all the first memory cells of the same row in the multiple memory subarray layers 1a are each connected to an odd word line 8a of the corresponding row through odd gate strips 2 in odd word line holes 4 of the same row, and all the second memory cells of the same row in the multiple memory subarray layers 1a are each connected to an even word line 8a of the corresponding row through even gate strips 2 in even word line holes 4 of the same row.
Of course, in other embodiments, it may be, in the same row, every adjacent three, four, or five word line holes 4, etc. are configured as a group, then each line word line includes three, four, five, etc. different types of word lines, and the gate strip 2 in each word line hole 4 in each group is connected to a different type of word line.
Furthermore, as shown in
As shown in
Of course, it is understood by those skilled in the art that multiple word lines may be arranged on another stacked chip, and the stacked chip may be stacked with and electrically connected to a chip in which the memory block 10 is located. For example, the stacked chip may be stacked with the chip in which the memory block 10 is located through hybrid bonding. An end of each word line connection line 7 in the memory block 10 away from the corresponding gate strip 2 serves as a word line connection terminal of the memory block 10 for connecting to the stacked chip stacked together in the height direction Z of the memory block 10.
In addition, as shown in
Referring further to
It will be understood by those skilled in the art that the memory block 10 may be connected to another stacked chip stacked together in the height direction Z of the memory block 10 through the bit line connection terminal, and provide a bit line voltage to each drain region semiconductor strip 11 in the memory block 10 as a bit line through the bit line connection terminal through another stacked chip. Of course, the bit line connection terminal may be further configured to be connected to the control circuit on the chip where the memory block 10 is located, i.e., the relevant lines, the memory array 1, and the control circuit are arranged on the same chip.
Similarly, for each column of drain region semiconductor strips 11, channel semiconductor strips 12, and source region semiconductor strips 13 of the multiple memory subarray layers 1a, the multiple source region semiconductor strips 13 in the same column are led out through different source line connection lines 13a disposed on an end of each source region semiconductor strip, and the source connection lines 13a extend along the height direction Z.
As shown in
Of course, it is understood by those skilled in the art that in other embodiments, the memory block 10 may include multiple common source lines 13b, such as a predetermined number of the multiple common source lines 13b, and the source region semiconductor strips 13 in the multiple memory subarray layers 1a may be connected to different multiple common source lines 13b via corresponding source connection lines 13a according to a predetermined rule. In addition, also similar to the bit line connection line 11a corresponding to the drain region semiconductor strip 11, an end of the source connection line 13a corresponding to each source region semiconductor strip 13 away from the source region semiconductor strip 13 may be configured as a source connection terminal to receive the source voltage.
Referring further to
Of course, it can be understood by those skilled in the art that the common source line 13b may be arranged in another stacked chip stacked with the memory block 10 in the height direction Z. That is, an end of the source connection line 13a away from the corresponding source region semiconductor strip 13 may be configured as a source connection terminal for connection with another stacked chip stacked with the memory block 10 in the height direction Z, such that the common source line 13b are arranged in another stacked chip.
As above, for each column of drain region semiconductor strips 11, channel semiconductor strips 12, and source region semiconductor strips 13 of the multiple memory subarray layers 1a, the multiple channel region semiconductor strips 12 in the same column are led out through different well region connection lines 12a disposed on an end of each channel semiconductor strip 12, and the well region connection lines 12a extend along the height direction Z.
As shown in
Of course, it will be understood by those skilled in the art that the corresponding well region connection line 12a of each channel semiconductor strip 12 in the memory block 10 may be connected to multiple separate well voltage lines 12b to apply a well voltage to each channel semiconductor strip 12 separately. For example, similar to the above, an end of the well region connection line 12a corresponding to each channel semiconductor strip 12 away from the channel semiconductor strip 12 serves as a well connection terminal which is configured to receive a separate well voltage.
Referring further to
Of course, it will be understood by those skilled in the art that the common well region line 12b may be arranged in another stacked chip stacked together with the memory block 10 in the height direction Z. That is, an end of the well region connection line 12a away from the corresponding channel semiconductor strip 12 may be configured as a well region connection terminal for connection to another stacked chip stacked together with the memory block 10 in the height direction Z, thereby arranging the common well region line 12b in another stacked chip.
Furthermore, it is noted that, as shown in
In addition, since the various wires in the present disclosure are arranged on the same side of the memory array 1 in the memory block 10, it is more convenient to perform the bonding stacking process in three dimensions with the stacked chips, thereby improving the performance of the related memory devices, and manufacturing the chips separately is conducive to optimizing the process and reducing the manufacturing time.
It can be understood by those skilled in the art that in some embodiments, in order for the memory block 10 to obtain better performance, the outermost memory cell may generally serve as a virtual memory cell (dummy cell) and does not perform actual storage works. For example, the memory cells included in the lowermost memory subarray layer 1a may be configured as virtual memory cells. In addition, in some embodiments, the leftmost and rightmost columns of the memory block 10 are each arranged with a column of drain region semiconductor strips 11, channel semiconductor strips 12, and source region semiconductor strips 13, respectively. The memory cells formed by the leftmost column of the drain region semiconductor strips 11, the channel semiconductor strips 12, and the source region semiconductor strips 13, together with the gate strips 2 in the word line holes 4 on the right side and the storage structures 5 between them, and the memory cells formed by the rightmost column of drain region semiconductor strips 11, channel semiconductor strips 12 and source region semiconductor strips 13, together with the gate strips 2 in the word line hole 4 on the left side and the storage structures 5 between them, are also taken as virtual memory cells not participating in the actual storage work.
Therefore, in the present disclosure, unless intentionally pointed out, the memory subarray layers 1a in the entire specification do not include the lowermost memory subarray layer involved in the virtual memory cells (dummy cells); nor do the drain region semiconductor strips 11, the channel semiconductor strips 12, and the source region semiconductor strips 13 include the leftmost column of drain region semiconductor strips 11, channel semiconductor strips 12, and source region semiconductor strips 13, and the rightmost column of drain region semiconductor strips 11, channel semiconductor strips 12, and source region semiconductor strips 13, involved in the virtual memory cells (dummy cells).
Therefore, as above, in a same row, from left to right, the first word line hole 4 only corresponds to a column of drain region semiconductor strips 11, channel semiconductor strips 12, and source region semiconductor strips 13 on the right side; the last word line hole 4 only corresponds to a column of drain region semiconductor strips 11, channel semiconductor strips 12, and source region semiconductor strips 13 on the left side. Therefore, those skilled in the art can understand that the first and last word line holes functionally constitute a complete word line hole.
In conjunction with
As shown in
As shown in
As shown in
According to the above conditions, it is understood by those skilled in the art that in the same row direction X, the memory block 10 includes (N+1) word line holes 4, such as shown as WL-hole-1-1, . . . , WL-hole-1-(N+1); and in the same column direction Y, the memory block 10 includes M word line holes 4, such as shown as WL-hole-1-(N+1), . . . , WL-hole-M-(N+1). A side of each column of drain region semiconductor strips 11, channel semiconductor strips 12, and source region semiconductor strips 13 corresponds to M word line holes 4. Each row of word lines (one odd word line 8a and one even word line 8b) corresponds to (N+1) word line holes 4. As above, in the same row, the word line holes 4 at the first and last ends each correspond to only one memory cell in each memory subarray layer 1a, and therefore the word line holes 4 at the first and last ends can be functionally regarded as a complete word line hole; while other word line holes 4 correspond to two memory cells (one on each of the left and right sides) in each memory subarray layer 1a. Therefore, each row of word lines corresponds to N*2*P memory cells. When N is an even number, an odd word line 8a corresponds to (N/2+1) word line holes, which includes word line holes 4 at the first and last ends of the same row, that is, an odd word line 8a also corresponds to N/2 complete word line holes 4, corresponding to (N/2)*P*2 memory cells. An even word line 8b corresponds to N/2 word line holes 4, corresponding to (N/2)*P*2 memory cells. In other words, the number of memory cells corresponding to an odd word lines 8a and the number of memory cells corresponding to an even word lines 8b are the same.
In some embodiments, assume that the memory block 10 specifically includes 8 layers of the memory subarray layers 1a and 1024 rows of word lines, each row of word lines includes an odd word line 8a and an even word line 8b, each layer of the memory subarray layer 1a includes 2048 columns of the drain region semiconductor strips 11 as bit lines, and the memory block 10 includes 2048*8 of the drain region semiconductor strips 11 as bit lines.
In the same row direction X, the memory block 10 includes (2048+1=2049) word line holes 4; in the same column direction Y, the memory block 10 includes 1024 word line holes 4. Each drain region semiconductor strip 11 as a bit line corresponds to 1024 word line holes 4, corresponding to 1024*2 memory cells. Each row of word lines corresponds to (2048+1=2049) word line holes 4. The word line holes 4 at the first and last ends each correspond to only one memory cell in each memory subarray layer 1a, which functionally constitutes a complete word line hole 4, which corresponds to 2048*2*8=32K memory cells. N is an even number 2048, then an odd word line 8a corresponds to (2048/2+1=1025) word line holes, which includes the word line holes 4 at the first and last ends of the same row, that is, an odd word line 8a also corresponds to 1024 complete word line holes 4, which corresponds to (2048/2)*8*2 memory cells; an even word line 8b corresponds to 2048/2 word line holes 4, which corresponds to (2048/2)*8*2 memory cells.
In the memory block 10, ⅛ of the memory cells corresponding to a word line, that is, 1024*2 memory cells, may be defined as one memory page (128 complete word line holes 4). In the memory block 10, 32K memory cells corresponding to one word line may be defined as a sector, which can be understood that one sector corresponds to 2 word lines, (2048+1) word line holes 4 (2048 complete word line holes 4), and 2048*2*8 memory cells (bit).
In the memory block 10, 16 sectors may be defined to form a sub memory block 10 (eblk) including 0.5M memory cells (2048*2*8*16=1024*2*2*8*16=1024*1024*0.5). In specific embodiments, the memory block 10 includes 64 sub memory blocks 10 including 32M memory cells. Each memory block 10 shares a common source line 13b and a common well region line 12b.
The memory block 10 provided in the embodiments includes a memory array 1, and the memory array 1 includes multiple memory cells distributed in a three-dimensional array; the memory array 1 includes multiple memory subarray layers 1a stacked sequentially along a height direction Z, and each memory subarray layer 1a includes a drain region semiconductor layer, a channel semiconductor layer, and a source region semiconductor layer stacked along the height direction Z; the drain region semiconductor layer, channel semiconductor layer, and source region semiconductor layer in each memory subarray layer 1a include multiple drain region semiconductor strips 11, channel semiconductor strips 12, and source region semiconductor strips 13, respectively, distributed along a row direction X, and each drain region semiconductor strip 11, channel semiconductor strip 12, and source region semiconductor strip 13 extends along a column direction Y; multiple gate strips 2 distributed along the column direction Y are arranged on each side of each column of drain region semiconductor strips 11, channel semiconductor strips 12, and source region semiconductor strips 13, each gate strip 2 extending along the height direction Z; in the height direction Z, a projection of at least a part of each gate strip 2 coincides with a projection of a part of a corresponding channel semiconductor strip 12 in each memory subarray layer 1a on a projection plane, the projection plane extending along the height direction Z and the column direction Y. Apart of the gate strip 2, a corresponding part of the channel semiconductor strip 12, a part of the drain region semiconductor strip 11 adjacent to the corresponding part of the channel semiconductor bar 12, and a part of the source region semiconductor strip 13 adjacent to the corresponding part of the channel semiconductor bar 12 are configured to form a memory cell. The memory block 10 has a higher storage density compared to a two-dimensional memory array.
As above, the memory block 10 of the present disclosure includes at least two structures of memory cells. In some embodiments, in combination with
The drain region portion 11′ is a part of the drain region semiconductor layer, the channel portion 12′ is a part of the channel semiconductor layer, and the source region portion 13′ is a part of the source region semiconductor layer of the memory block 10 provided in the above embodiments. The specific structures, functions, and stacking methods of the drain region portion 11′, the channel portion 12′, the source region portion 13′, and the storage structure portion 5′ can be found in those of the drain region semiconductor layer, the channel semiconductor layer, the source region semiconductor layer, and the storage structure portion 5′ in each of the memory subarray layers 1a described above, and the same or similar technical effects can be achieved, which will not be repeated herein.
When the drain region portion 11′, the channel portion 12′, and the source region portion 13′ are each in a strip structure and the storage structure portion 5′ is a charge trapping storage structure portion, the specific structure of the memory cell can be seen in
Referring to
Referring to
The substrate 81 may be a single-crystal substrate 81; specifically, it may be made of single-crystal silicon. The first single-crystal sacrificial semiconductor layer 82 and/or the second single-crystal sacrificial semiconductor layer 14 may be made of silicon germanium (SiGe). The multiple memory subarray layers 1a are sequentially layered in a height direction Z perpendicular to the substrate 81. Each memory subarray layer 1a includes a drain region semiconductor layer 11c, a channel semiconductor layer 12c′, and a source region semiconductor layer 13c′ stacked along the height direction Z. Two adjacent memory subarray layers 1a in the height direction Z may share a common source region. The two adjacent memory subarray layers 1a may include sequentially stacked drain region semiconductor layer 11c, channel semiconductor layer 12c′, source region semiconductor layer 13c′, channel semiconductor layer 12c′, and drain region semiconductor layer 11c, to achieve sharing the common source region semiconductor layer 13c′. Therefore, for common-source memory subarray layers 1a, a second single-crystal sacrificial semiconductor layer 14 is arranged on every two memory subarray layers 1a to isolate from the other two memory subarray layers 1a. The second single-crystal sacrificial semiconductor layer 14 may be made of a silicon germanium (SiGe) semiconductor material.
It should be noted that the structure shown in
In some embodiments, step S21 may specifically include the following.
The substrate 81 may be a single-crystal substrate 81; specifically, it may be a single-crystal silicon.
The first single-crystal sacrificial semiconductor layer 82 may be silicon germanium (SiGe).
The material of the second single-crystal sacrificial semiconductor layer 14 is the same as the material of the first single-crystal sacrificial semiconductor layer 82, which may also be silicon germanium (SiGe).
It is understood by those skilled in the art that the purpose of providing the first single-crystal sacrificial semiconductor layer 82 on the substrate 81 first is to avoid electrical leakage caused by the multiple memory subarray layers 1a directly contacting the substrate 81. However, as above, the device performance of the lowermost memory subarray layer 1a in the memory block of the present disclosure is poor, and therefore, the memory cells in the lowermost memory subarray layer 1a are generally configured as virtual memory cells and do not participate in the actual memory work. Therefore, it is understood by those skilled in the art that the first single-crystal sacrificial semiconductor layer 82 may not be arranged on the substrate 81, and a single memory subarray layer 1a or two common-source memory subarray layers 1a are formed directly on the substrate 81 as virtual memory cells, on which the second single-crystal sacrificial semiconductor layer 14 and two common-source memory subarray layers 1a are alternately formed by epitaxial growth until the uppermost layer of two common-source memory subarray layers 1a are formed. That is, the lowermost one memory subarray layer 1a or two common-source memory subarray layers 1a, as a virtual memory cell(s), does not participate in the actual memory work, and therefore, it can also prevent electrical leakage to the substrate 81.
Two adjacent memory subarray layers 1a share a common source region, and each two common-source memory subarray layers may be formed in a manner including the following.
Specifically, a semiconductor material gas and a first type of dopant ion gas may be simultaneously introduced to form one layer of the first single-crystal semiconductor layer of the first doping type on the first single-crystal sacrificial semiconductor layer 82 or the second single-crystal sacrificial semiconductor layer 14 of the lower layer by epitaxial growth. The first single-crystal semiconductor layer serves as a drain region semiconductor layer 11c (or a source region semiconductor layer 13c′). The first type of dopant ion may be an arsenic ion. The semiconductor material may be an existing semiconductor material for forming the drain region (or source region).
Specifically, a semiconductor material gas and a second type of dopant ion gas may be simultaneously fed to form one layer of the second single-crystal semiconductor layer of the second doping type on the first single-crystal semiconductor layer by epitaxial growth. The second single-crystal semiconductor layer serves as a channel semiconductor layer 12c′. The second type of dopant ion may be a BF2+ ion. The semiconductor material may be an existing semiconductor material for forming a well region.
Specifically, a semiconductor material gas and a first type of dopant ion gas may be simultaneously fed to form one layer of the third single-crystal semiconductor layer of the first doping type on the second single-crystal semiconductor layer by epitaxial growth. The third single-crystal semiconductor layer serves as a source region semiconductor layer 13c′ (or a drain region semiconductor layer 11c). The first type of dopant ion may be an arsenic ion. The semiconductor material may be an existing semiconductor material for forming the source drain region (or drain region).
In a specific implementation of step S212a, one layer of the second single-crystal sacrificial semiconductor layer 14 is further formed between every two memory subarray layers 1a. Each two adjacent memory subarray layers 1a separated by the second single-crystal sacrificial semiconductor layer 14 in the height direction Z includes sequentially stacked drain region semiconductor layer 11c, channel semiconductor layer 12c′, source region semiconductor layer 13c′, channel semiconductor layer 12c′, and drain region semiconductor layer 11c to share the same source region semiconductor layer 13c′.
This step b4 is performed in a similar manner to step b2. The fourth single-crystal semiconductor layer serve as the channel semiconductor layer 12c′.
This step b5 is performed in a similar manner as step b1. The fifth single-crystal semiconductor layer serve as the drain region semiconductor layer 11c (or source region semiconductor layer 13c′).
The first single-crystal semiconductor layer, the second single-crystal semiconductor layer, and the third single-crystal semiconductor layer form a memory subarray layer 1a; the third single-crystal semiconductor layer, the fourth single-crystal semiconductor layer, and the fifth single-crystal semiconductor layer form another memory subarray layer 1a; and the two memory subarray layers 1a share the third single-crystal semiconductor layer as the shared source region semiconductor layer 13c′.
It is understood that, in the embodiments, after step b5, one layer of the second single-crystal sacrificial semiconductor layer 14 is formed on the fifth single-crystal semiconductor layer, after which steps b1-b5 may be repeated on the second single-crystal sacrificial semiconductor layer 14 until a predetermined number of layers of the memory subarray layers 1a is formed.
That is, a second single-crystal sacrificial semiconductor layer 14 is formed between every two memory subarray layers 1a. Moreover, each adjacent two memory subarray layers 1a separated by the second single-crystal sacrificial semiconductor layer 14 in the height direction Z includes sequentially stacked drain region semiconductor layer 11c, channel semiconductor layer 12c′, source region semiconductor layer 13c′, channel semiconductor layer 12c′, and drain region semiconductor layer 11c to share the same source region semiconductor layer 13c′.
The first hard mask layer 83 may be made of a silicon dioxide material or a silicon nitride.
Specifically, referring to
In other embodiments, step S21 specifically includes the following operations.
The specific implementation process of forming the multiple memory subarray layers 1a is the same or similar to the specific implementation process of forming the multiple memory subarray layers 1a in step S212a above, and the same or similar technical effect can be achieved, as described above.
Specifically, the first hard mask layer 83 may be formed on the product structure after being processed by step S213b, with the first hard mask layer 83 being disposed on a side surface of the multiple memory subarray layers 1a away from the substrate 81.
In some embodiments, step S22 specifically includes the following.
Referring to
Referring to
As shown in
In a specific implementation, referring to
Specifically, the first single-crystal sacrificial semiconductor layer 82 and the second single-crystal sacrificial semiconductor layer 14 may be removed by etching.
The insulating material may be filled through atomic layer deposition. The insulating material may specifically be silicon oxide. It will be understood by those skilled in the art that after step S223 removing the first single-crystal sacrificial semiconductor layer 82 and the second single-crystal sacrificial semiconductor layer 14, the isolation walls 3 may provide sufficient support to the adjacent stacked structures 1b to facilitate subsequent execution of step S224.
Further, it will be understood by those skilled in the art that in some embodiments, the memory array 1 further includes a support post 16. Specifically, referring to
As shown in
As described above, the first single-crystal sacrificial semiconductor layer 82 and the second single-crystal sacrificial semiconductor layer 14 are required to be replaced with the insulating isolation layer 14′. In this step, the first single-crystal sacrificial semiconductor layer 82 and the second single-crystal sacrificial semiconductor layer 14 are partially replaced with the insulating isolation layer 14′, but in subsequent steps, all of the first single-crystal sacrificial semiconductor layer 82 and the second single-crystal sacrificial semiconductor layer 14 are replaced with the insulating isolation layer 14′ as required for electrical isolation. That is, during the manufacturing of the memory array 1, after etching off the first single-crystal sacrificial semiconductor layer 82 and/or the second single-crystal sacrificial semiconductor layer 14, the memory subarray layers 1a in the relevant regions are overhanging. In these relevant regions, when the isolation walls 3 are provided, the isolation walls 3 can provide sufficient support to the overhanging memory subarray layers 1a in these regions to prevent the memory subarray layers 1a from collapsing.
However, the isolation walls 3 may not present in some regions. For example, in a drain/source lead region, the memory subarray layers 1a in this region are not required to manufacture the memory cells, and the drain region semiconductor strips 11, source region semiconductor strips 13, and/or channel semiconductor strips 12 in the memory subarray layers 1a in this region are required to be led out to be connected with corresponding wires. Therefore, in these regions, multiple support posts 16 are required to be arranged between two columns of the stacked structures 1b. In this way, after etching the first single-crystal sacrificial semiconductor layer 82 and/or the second single-crystal sacrificial semiconductor layer 14 in the stacked structures 1b in these regions during the manufacturing of the memory array 1, the support posts 16 can provide sufficient support to the overhanging memory subarray layers 1a to prevent the memory subarray layers 1a from collapsing, and can support the frame of the memory array 1 and maintain the structural stability of the memory array 1.
It will be understood by those skilled in the art that each support post 16 may be made of the same material as the isolation wall 3 and manufactured in the same process steps as the isolation wall 3. That is, the isolation wall 3 and the support post 16 are similar in nature, except that the isolation wall 3 is arranged in the region of the memory array 1 where the memory cells are required to be manufactured, and it serves to support and form the word line holes 4 during the manufacturing of the memory array 1; whereas the support post 16 is formed in another region of the memory array 1 where the memory cell is not required to be manufactured, for example, the drain/source lead region, and it serves to support the memory array 1 during the manufacturing process. Of course, in other embodiments, the support post 16 may be arranged in the region of the memory array 1 where the memory cells are required to be manufactured. For example, when the distance between two adjacent isolation walls 3 is far, and the isolation wall 3 does not provide sufficient support, then the support post 16 may be arranged in this region as needed to assist the isolation wall 3 to provide support. That is, the support post 16 may be arranged according to the actual needs, which is not limited by the present disclosure.
The material of the support post 16 may be silicon oxide or silicon nitride.
The product structure after processing by step S23 can be seen specifically in
Specifically, one layer of the first dielectric layer is deposited within each word line hole 4 and on a surface of the first hard mask layer 83 away from the substrate 81. The first dielectric layer within each word line hole 4 covers surfaces of the parts of the drain region semiconductor strips 11, channel semiconductor strips 12, and source region semiconductor strips 13 that are exposed on both sides of the word line hole 4. For example, in conjunction with
The charge-trapping layer is disposed on a side surface of the first dielectric layer away from a corresponding column of semiconductor strip structures 1b.
The second dielectric layer is disposed on a side surface of the charge-trapping layer away from the first dielectric layer.
The product structure after processing by step S24 is specified in
As above, in the embodiments, the storage structure 5 is a charge trapping storage structure, such as an ONO type charge trapping storage structure, such that it can hold the electric charges injected into near the injection point. The electric charges can only move in the injection/removal direction (substantially perpendicular to the extension direction of the charge-trapping layer 52), and cannot move freely in the charge-trapping layer 52, especially not in the extension direction of the charge-trapping layer 52. For the charge trapping storage structure, the charge-trapping layer 52 is only required to have an insulating dielectric arranged on its front and back side, and the charge stored in each memory cell will be fixed near the injection point of the charge-trapping portion and will not move to the charge-trapping portion in other memory cells along the same layer of the charge-trapping layer 52. Therefore, in its corresponding manufacturing method, it is only necessary to form a first dielectric layer 51 and a second dielectric layer 53 on both sides of the charge-trapping layer 52, respectively, to separate the charge-trapping layer 52 from the drain region semiconductor strip 11, the channel semiconductor strip 12, the source region semiconductor strip 13 and the gate strip 2, and its manufacturing method is relatively simple.
Specifically, the above manufacturing method of memory blocks may be configured to prepare the memory blocks involved in the following embodiments. The memory block 10 includes a memory array 1, which includes multiple memory cells distributed in a three-dimensional array. The memory array 1 includes multiple stacked structures 1b distributed along the row direction X, each stacked structure 1b extending along the column direction Y, and each stacked structure 1b includes drain region semiconductor strips 11, channel semiconductor strips 12, and source region semiconductor strips 13 stacked along the height direction Z. Each drain region semiconductor strip 11, channel semiconductor strip 12, and source region semiconductor strip 13 extends along column direction Y, and each drain region semiconductor strip 11, channel semiconductor strip 12, and source region semiconductor strip 13 is a single-crystal semiconductor strip.
Multiple gate strips 2 are arranged on each of two sides of each stacked structure 1b along the column direction Y, and each gate strip 2 extends along the height direction Z. In the height direction Z, a projection of at least a part of each gate strip 2 coincides with a projection of a part of a corresponding channel semiconductor strip 12 on a projection plane extending along the height direction Z and the column direction Y. A part of the gate strip 2, a corresponding part of the channel semiconductor strip 12, a part of the drain region semiconductor strip 11 adjacent to the corresponding part of the channel semiconductor bar 12, and a part of the source region semiconductor strip 13 adjacent to the corresponding part of the channel semiconductor bar 12 form a memory cell. Specifically, a charge trapping storage structure is arranged between each gate strip 2 and corresponding drain region semiconductor strips 11, channel semiconductor strips 12, and source region semiconductor strips 13 in the multiple memory subarray layers 1a. The specific structure and function of the charge trapping storage structure, and the position relationship with the memory array 1, etc., can be found in the relevant description above.
Specifically, each stacked structure 1b includes multiple stacked substructures, each stacked substructure including a drain region semiconductor strip 11, a channel semiconductor strip 12, a source region semiconductor strip 13, a channel semiconductor strip 12, and a drain region semiconductor strip 11 stacked sequentially along the height direction Z to share the same source region semiconductor strip 13. Specifically, an interlayer isolation layer is arranged between two adjacent stacked substructures (i.e., the above-mentioned insulating isolation layer 14′) to isolate the two adjacent stacked substructures from each other.
Multiple isolation walls 3 distributed along the column direction Y are arranged on each side of each stacked structure 1b, and each isolation wall 3 extends along the height direction Z and the row direction X to separate at least part of the two adjacent columns of the stacked structures 1b. The isolation walls 3 further serve as support structures to support the two adjacent columns of the stacked structures 1b in the manufacturing process as shown above to facilitate the subsequent manufacturing process. Of course, after the manufacturing process, the isolation walls 3 may be further configured as support structures to support the two adjacent columns of the stacked structures 1b. The isolation wall 3 near an edge of the memory block 10 in the column direction Y is a T-shaped wall to completely isolate the two adjacent columns of the stacked structures 1b. Of course, the isolation wall 3 at the edge in the column direction Y may take other shapes, such as extending in the column direction Y to the edge of the memory block 10 in the column direction Y, etc., as long as it can completely isolate the two adjacent columns of the stacked structures 1b at the edge of the memory block 10 in the column direction Y.
In the column direction Y, a gate strip 2 is arranged between two adjacent isolation walls 3 on the same column; parts of two adjacent columns of the stacked structures 1b share the same gate strip 2.
Other structures and functions of the memory block 10 provided in the embodiments can be found in the specific description of the memory block 10 provided in any of the above embodiments where the storage structure is a charge trapping storage structure, and will not be repeated herein.
The memory cell corresponding to the above manufacturing method includes: a drain region portion 11′, a channel portion 12′, a source region portion 13′, and a gate portion 2′. The drain region portion 11′, the channel portion 12′, and the source region portion 13′ are stacked along the height direction Z, and the gate portion 2′ is disposed on one side of the drain region portion 11′, the channel portion 12′, and the source region portion 13′, and along the height direction Z. In the height direction Z, a projection of the gate portion 2′ at least partially coincides with a projection of the channel portion 12′ on a projection plane, the projection plane extending along the height direction Z and the drain region portion 11′. A charge trapping storage structure portion is arranged between the gate portion 2′ and the drain region portion 11′, the channel portion 12′, and the source region portion 13′.
The specific structure and position of the charge trapping storage structure portion can be found in the above description. Other structures and functions of the memory cell can be found in the description of the memory cell with the charge trapping storage structure portion 5′ involved in the above embodiments, which will not be repeated herein.
In other embodiments, referring
The specific implementation process of step S31-step S32 is the same or similar to the specific implementation process of step S21-step S22 above, and can achieve the same or similar technical effect, as can be seen above, which will not be repeated herein.
It should be noted that the subsequent steps are the relevant steps after the first single-crystal sacrificial semiconductor layer 82 and the second single-crystal sacrificial semiconductor layer 14 are replaced by the insulating isolation layer 14′ using the word line holes 4. The relevant process steps of the embodiments are the same as the relevant process steps of the previous embodiments, and will not be repeated herein.
In some embodiments, step S331 specifically includes the following.
Referring to
In the embodiments, etching may be performed using an etchant with a high etch ratio for the channel semiconductor strips 12 and the insulating isolation layers 14′, and with a low etch ratio for the drain region semiconductor strips 11 and the source region semiconductor strips 13. For example, when the drain region semiconductor strips 11 and the source region semiconductor strips 13 are N-type semiconductor strips and the channel semiconductor strips 12 are P-type semiconductor strips, then an etchant with a high etch ratio for the P-type semiconductor material and with a low etch ratio for the N-type semiconductor material may be applied for selective etching, such that only the parts of the channel semiconductor strips 12 and the insulating isolation layers 14′ exposed on both sides of the word line hole 4 are etched, thereby defining the first recesses 84.
It will be understood by those skilled in the art that when acid etching is performed on a part of the channel semiconductor strips 12, the etchant etches a part of the insulating isolation layers 14′ while etching the part of the channel semiconductor strip 12, defining third recesses 84a, as shown in
Although in
Referring to
When the first recesses 84 are filled with the first insulating dielectric 85, the third recess 84a, formed by etching off parts of the insulating layers 14′, are also filled with the first insulating dielectric 85. Since the material of the first insulating dielectric 85 is silicon oxide, which is the same material as the insulating isolation layers 14′, the device performance will not be affected.
In some embodiments, referring to
The second recesses 84′ may be defined by etching. A vertical cross-sectional view of the product after removing the parts of the drain region semiconductor strips 11 and the parts of the source region semiconductor strips 13 exposed on both sides of each word line hole 4 to define the multiple second recesses 84′ can be seen in
The second insulating dielectric 86 may be formed by deposition. The second insulating dielectric 86 may be made of silicon nitride. After Step D, step E is performed.
As shown in
The structure of the product after step S332 can be seen in
Specifically, a floating gate material may be deposited in the floating gate slot to form the floating gate 54, and the floating gate material may include polycrystalline silicon material.
In some embodiments, referring to
It will be understood that after Step 3331, the first insulating dielectric layer 85a wraps only a part of the floating gate 54.
Referring to
As can be seen in
The structure of the product after step S34 can be seen in
A projection of at least a part of each gate strip 2 coincides with a projection of a part of a corresponding channel semiconductor strip 12 in each memory subarray layer 1a on a projection plane, the projection plane extending along the height direction Z and the column direction Y. A part of the gate strip 2, a corresponding part of the channel semiconductor strip 12, a part of the drain region semiconductor strip 11 adjacent to the corresponding part of the channel semiconductor strip 12, a part of the source region semiconductor strip 13 adjacent to the corresponding part of the channel semiconductor strip 12, and a part of a corresponding floating gate storage structure, form a memory cell.
In the embodiments, the storage structure 5 is a floating gate storage structure, as above, and the floating gate storage structure is characterized by the fact that the charge injected in can be uniformly distributed in the entire floating gate 54, and the charge can move not only in the injection/removal direction (substantially perpendicular to the extension direction of the floating gate), but also in the floating gate 54, particularly in the extension direction of the floating gate 54. Therefore, in the floating gate storage structure, the floating gate 54 of each memory cell is independent, and each surface of each floating gate 54 is required to be covered by an insulating dielectric to be isolated from each other, thereby preventing the charges stored in the floating gates 54 in one memory cell from moving to the floating gates 54 in other memory cells. Therefore, in the manufacturing method thereof, the floating gate 54 of each memory cell is independent, and the insulating dielectric formed by the first insulating dielectric layer 85a and the second insulating dielectric layer 85b can completely wrap and isolate the various surfaces of the floating gates 54, such that the floating gates 54 of each memory cell are independent and the charge stored in each floating gate 54 cannot move to the floating gates 54 of other memory cells.
Specifically, the manufacturing method may be configured to prepare the memory block involved in the following embodiments. The memory block 10 includes a memory array 1, which includes multiple memory cells distributed in a three-dimensional array. The memory array 1 includes multiple stacked structures 1b distributed along the row direction X, each stacked structure 1b extending along the column direction Y, and each stacked structure 1b includes drain region semiconductor strips 11, channel semiconductor strips 12, and source region semiconductor strips 13 stacked along the height direction Z. Each drain region semiconductor strip 11, channel semiconductor strip 12, and source region semiconductor strip 13 extends along column direction Y, and each drain region semiconductor strip 11, channel semiconductor strip 12, and source region semiconductor strip 13 is a single-crystal semiconductor strip.
Multiple gate strips 2 are arranged on each of two sides of each stacked structure 1b along the column direction Y, and each gate strip 2 extends along the height direction Z. In the height direction Z, a projection of at least a part of each gate strip 2 coincides with a projection of a part of a corresponding channel semiconductor strip 12 on a projection plane extending along the height direction Z and the column direction Y. A part of the gate strip 2, a corresponding part of the channel semiconductor strip 12, a part of the drain region semiconductor strip 11 adjacent to the corresponding part of the channel semiconductor bar 12, and a part of the source region semiconductor strip 13 adjacent to the corresponding part of the channel semiconductor bar 12 form a memory cell. Specifically, a floating gate storage structure is arranged between each gate strip 2 and corresponding drain region semiconductor strips 11, channel semiconductor strips 12, and source region semiconductor strips 13 in the multiple memory subarray layers 1a. The floating gate storage structure includes multiple first insulating dielectric layers 85a, multiple floating gates 54, and the second insulating dielectric layer 85b. Each first insulating dielectric layer 85a is disposed between at least a corresponding channel semiconductor strip 12 and a corresponding floating gate 54, the floating gate 54 is located disposed a corresponding first insulating dielectric layer 85a and the second insulating dielectric layer 85b, and the second dielectric layer 85b is disposed between the floating gates 54 and the gate strip 2.
Specifically, each stacked structure 1b includes multiple stacked substructures, each stacked substructure including a drain region semiconductor strip 11, a channel semiconductor strip 12, a source region semiconductor strip 13, a channel semiconductor strip 12, and a drain region semiconductor strip 11 stacked sequentially along the height direction Z to share the same source region semiconductor strip 13. Specifically, an interlayer isolation layer is arranged between two adjacent stacked substructures to isolate the two adjacent stacked substructures from each other.
Multiple isolation walls 3 distributed along the column direction Y are arranged on each side of each stacked structure 1b, and each isolation wall 3 extends along the height direction Z and the row direction X to separate at least part of the two adjacent columns of the stacked structures 1b. The isolation walls 3 further serve as support structures to support the two adjacent columns of the stacked structures 1b. The isolation wall 3 near an edge of the memory block 10 in the column direction Y is a T-shaped wall to completely isolate the two adjacent columns of the stacked structures 1b.
In the column direction Y, a gate strip 2 is arranged between two adjacent isolation walls 3 on the same column; parts of two adjacent columns of the stacked structures 1b share the same gate strip 2.
Other structures and functions of the memory block 10 provided in the embodiments can be found in the specific description of the memory block 10 provided in any of the above embodiments where the storage structure is a floating gate storage structure, and will not be repeated herein.
The memory cell corresponding to the above manufacturing method includes: a drain region portion 11′, a channel portion 12′, a source region portion 13′, and a gate portion 2′. The drain region portion 11′, the channel portion 12′, and the source region portion 13′ are stacked along the height direction Z, and the gate portion 2′ is disposed on one side of the drain region portion 11′, the channel portion 12′, and the source region portion 13′, and along the height direction Z. In the height direction Z, a projection of the gate portion 2′ and a projection the channel portion 12′ on a projection plane extending along the height direction Z at least partially coincide, the projection plane being located on a side of the drain region portion 11′, the channel portion 12′, and the source region portion 13′ and extending along the height direction Z and column direction Y. A floating gate storage structure portion is arranged between the gate portion 2′ and the drain region portion 11′, the channel portion 12′, and the source region portion 13′.
The floating gate storage structure portion specifically includes a corresponding first insulating dielectric layer 85a, a corresponding floating gate 54, and a part of the second insulating dielectric layer 85b. The first insulating dielectric layer 85a is disposed between the channel portion 12′ and the floating gate 54, the floating gate 54 is disposed between the first insulating dielectric layer 85a and the part of the second insulating dielectric layer 85b, and the part of the second insulating dielectric layer 85b is disposed between the floating gate 54 and the gate strip 2. The part of the second insulating dielectric layer 85b covers five surfaces of the floating gate 54. One of the five surfaces of the floating gate 54 is fully covered by the second insulating dielectric layer 85b. The part of the second insulating dielectric layer 85b includes a multilayer structure including a part of a silicon oxide layer, a part of a silicon nitride layer, and a part of another silicon oxide layer.
Other structures and functions of the memory cell can be found in the description of the memory cell for which the storage structure portion 5′ is a floating gate storage structure portion involved in the above-described embodiments, and will not be repeated herein.
Referring to
As shown in
In conjunction with
Referring to
Each drain/source connection terminal subarray 9a of the multiple first-type drain/source connection terminal subarrays and the second-type drain/source connection terminal subarrays includes a first drain/source connection terminal group 92a and a second drain/source connection terminal group 92b. As shown in
The multiple drain/source connection terminals 91a/91b in the first drain/source connection terminal group 92a of the first-type drain/source connection terminal subarray correspond to the drain/source region semiconductor strips 11/13 of the low zone F1 of one of the two corresponding adjacent columns of semiconductor strip structures 1b; and the multiple drain/source connection terminals 91a/91b in the first drain/source connection terminal group 92a are connected to the drain/source region semiconductor strips 11/13 of the low zone F1 of the corresponding column of semiconductor strip structures 1b by multiple drain/source connection plugs 94. Each drain/source connection terminal 91a/91b of the first drain/source connection terminal group 92a corresponds to a drain/source connection plug 94. It will be understood by those skilled in the art that an exposed part of the drain/source connection plugs 94 may serve as the corresponding drain/source connection terminal 91a/91b.
Those skilled in the art can understand that the same drain/source region semiconductor strip 11/13 in any of the above-mentioned columns of semiconductor strip structures 1b corresponds to multiple corresponding drain/source connection terminals 91a/91b in a corresponding column of one or more drain/source connection terminal arrays 9. For example, in conjunction with
In this way, each drain/source region semiconductor strip 11/13 can be connected to multiple drain/source connection terminals 91a/91b, such that a part of each drain/source region semiconductor strip 11/13 that is at corresponding positions of two adjacent drain/source connection terminals 91a/91b may directly transmit signals through the drain/source connection terminals 91a/91b at the corresponding positions, for performing read (RD), program (PGM), and other operations; compared with leading through a connection line at the end of each drain/source region semiconductor strip 11/13 (i.e., the edge portion of the memory block 10) and performing related operations of the entire drain/source region semiconductor strip 11/13 through the connection line, the resistance may be reduced to facilitate signal transmission and improve the speed of read (RD), program (PGM), and other operations of the memory block 10 in the present disclosure.
The multiple drain/source connection terminals 91a/91b of the second drain/source connection terminal group 92b in the first-type drain/source connection terminal subarray correspond to the drain/source region semiconductor strips 11/13 of the low zone F1 of the other of the two corresponding adjacent columns of semiconductor strip structures 1b; and the multiple drain/source connection terminals 91a/91b in the second drain/source connection terminal group 92b are connected the drain/source region semiconductor strips 11/13 of the low zone F1 of the other of the two corresponding adjacent columns of semiconductor strip structures 1b through multiple drain/source connection plugs 94.
It should be noted that the drain/source region semiconductor strips 11/13 of the low zone F1 and the high zone F2 of the column of semiconductor strip structures 1b involved in the present disclosure may be divided by a middle layer of the column of semiconductor strip structures 1b as a dividing line. For example, when the column of semiconductor strip structures 1b corresponds to eight layers of memory subarray layer 1a, the drain/source region semiconductor strips 11/13 of the low zone F1 of the column of semiconductor strip structures 1b refers to the drain/source region semiconductor strip 11/13 corresponding to the fifth memory subarray layer 1a to the eighth memory subarray layer 1a counting from top to bottom, and the drain/source region semiconductor strip 11/13 of the high zone F2 of the column of semiconductor strip structures 1b refers to the drain/source region semiconductor strips 11/13 corresponding to the first memory subarray layer 1a to the fourth memory subarray layer 1a from top to bottom.
The multiple drain/source connection terminals 91a/91b in the first drain/source connection terminal group 92a of the second-type drain/source connection terminal subarray correspond to the drain/source region semiconductor strips 11/13 of the high zone F2 of one of the two corresponding adjacent columns of semiconductor strip structures 1b; and the multiple drain/source connection terminals 91a/91b in the first drain/source connection terminal group 92a are connected to the drain/source region semiconductor strips 11/13 of the high zone F2 of the corresponding column of semiconductor strip structures 1b by multiple drain/source connection plugs 94. Each drain/source connection terminal 91a/91b of the first drain/source connection terminal group 92a corresponds to a drain/source connection plug 94.
The multiple drain/source connection terminals 91a/91b of the second drain/source connection terminal group 92b in the second-type drain/source connection terminal subarray correspond to the drain/source region semiconductor strips 11/13 of the high zone F2 of the other of the two corresponding adjacent columns of semiconductor strip structures 1b; and the multiple drain/source connection terminals 91a/91b in the second drain/source connection terminal group 92b are connected the drain/source region semiconductor strips 11/13 of the high zone F2 of the other of the two corresponding adjacent columns of semiconductor strip structures 1b through multiple drain/source connection plugs 94. Each drain/source connection terminal 91a/91b of the second drain/source connection terminal group 92b corresponds to a drain/source connection plug 94.
For example, in conjunction with
In other embodiments, referring further to
The first drain/source connection terminal group 92a in each drain/source connection terminal subarray 9a of each first-type drain/source connection terminal array (e.g., an upper drain/source connection terminal array 9) is configured to be connected to drain/source region semiconductor strips 11/13 of the low zone F1 in a corresponding column of semiconductor strip structures 1b. The second drain/source connection terminal group 92b in each drain/source connection terminal subarray 9a of each first-type drain/source connection terminal array is configured to be connected to drain/source region semiconductor strips 11/13 of the low zone F1 in another adjacent corresponding column of semiconductor strip structures 1b. That is, each drain/source connection terminal group 92a/92b in the same drain/source connection terminal array 9 is configured to be connected to drain/source region semiconductor strips 11/13 of either the low zone F1 or the high zone F2.
The first drain/source connection terminal group 92a in each drain/source connection terminal subarray 9a in each second-type drain/source connection terminal array (e.g., the lower drain/source connection terminal array 9) is configured to be connected to drain/source region semiconductor strips 11/13 of the high zone F2 in a corresponding column of semiconductor strip structures 1b; the second drain/source connection terminal group 92b in each drain/source connection terminal subarray 9a in each second-type drain/source connection terminal array is configured to be connected to drain/source region semiconductor strips 11/13 of the high zone F2 in another adjacent corresponding column of semiconductor strip structures 1b.
It will be understood by those skilled in the art that each of the drain/source connection terminal groups 92a/92b in one of the two adjacent drain/source connection terminal arrays 9 is configured to be connected to the drain/source region semiconductor strip 11/13 of the low zone F1; each of the drain/source connection terminal groups 92a/92b in the other drain/source connection terminal array 9 is configured to be connected to the drain/source region semiconductor strips 11/13 of the high zone F2.
As described above, in the above embodiments of the present disclosure, the drain/source region semiconductor strips 11/13 in each column of semiconductor strip structures 1b are connected to the drain/source connection terminals 91a/91b in corresponding two adjacent drain/source connection terminal subarrays 9a distributed in the row direction X, respectively; and/or, the drain/source region semiconductor strips 11/13 in each column of semiconductor strip structures 1b are connected to the drain/source connection terminals 91a/91b in corresponding two adjacent drain/source connection terminal subarrays 9a distributed in the column direction Y, respectively.
Of course, in other embodiments, it will be understood by those skilled in the art that each drain/source connection terminal subarray 9a in the drain/source connection terminal array 9 may have other designs as long as the drain/source connection terminals 91a/91b in the drain/source connection terminal subarray 9a may lead out the drain/source region semiconductor strips 11/13 in each corresponding column of semiconductor strip structures 1b.
For example, in some embodiments, each drain/source connection terminal array 9 includes multiple drain/source connection terminal subarrays 9a distributed in the X direction, each drain/source connection terminal subarray 9a including a first drain/source connection terminal group 92a and a second drain/source connection terminal group 92b, where multiple drain/source connection terminals 91a/91b in the first drain/source connection terminal group 92a correspond to drain/source region semiconductor strip 11/13 of the low zone F1 of one of corresponding two adjacent columns of semiconductor strip structures 1b; and multiple drain/source connection terminals 91a/91b in the second drain/source connection terminal group 92b corresponding to drain/source region semiconductor strips 11/13 of the high zone F2 of the other of the corresponding two adjacent columns of semiconductor strip structures 1b.
It will be understood by those skilled in the art that the above embodiments are merely examples, and that those skilled in the art may reasonably design based on the above principles.
Furthermore, it will be understood by those skilled in the art that the drain/source region semiconductor strips 11/13 corresponding to the high zone F2 and the low zone F1 may be selected to be connected to either drain/source connection terminal 91a/91b, as long as all of the drain/source region semiconductor strips 11/13 (S/D) are led out. For example, in the second drain/source connection terminal group 92b, the drain/source connection terminals 91a/91b may be connected to the drain/source region semiconductor strips 11/13 in the 1st, 5th, 6th, and 8th memory subarray layers 1a of a column of semiconductor strip structures 1b; while in the first drain/source connection terminal group 92a, the drain/source connection terminals 91a/91b may be connected to the drain/source region semiconductor strips 11/13 in the 2nd, 3rd, 4th, and 7th memory subarray layers 1a of a column of semiconductor strip structures 1b. The present disclosure is not limited in this respect.
Referring further to
In order to prevent the contact between the channel semiconductor strip 12 and the drain/source connection plug 94 from causing a short circuit, a first insulating material 95a (as described in
Further, in order to save the photomask and lead out the drain/source region semiconductor strips 11/13 at different heights in each column of the semiconductor strip structures 1b, as shown in
The first insulating material 95a is arranged between the adjacent drain region semiconductor strip 11 and the source region semiconductor strip 13. A filling material 95b and a second hard mask layer 99 are arranged on the step-like drain/source region semiconductor strips 11/13. The second hard mask layer 99 is disposed on a side surface of the filling material 95b away from the column of semiconductor strip structures 1b. Drain/source connection terminal holes 98 are defined in the filling material 95b, and each drain/source connection terminal hole 98 is filled with a conductive material to form the drain/source connection terminal 91a/91b and the drain/source connection plug 94. Since polycrystalline silicon has better fillability, the filling material 95b may be selected from polycrystalline silicon. When the filling material 95b is made of polysilicon, an insulating layer 95c may be further arranged on the step-like drain/source region semiconductor strips 11/13 and the filling material 95b is specifically arranged on the insulating layer 95c. It is understood by those skilled in the art that when the filling material 95b is made of an insulating material, such as silicon oxide, it is not necessary to form the insulating layer 95c on the step-like drain/source region semiconductor strips 11/13 and it is sufficient to fill the filling material 95b directly; in this case, a spacing dielectric layer on a side wall of the drain/source connection terminal hole 98 is not necessarily arranged.
It can be understood that the drain/source connection plug 94 is specifically inserted in the filling material 95b and extends to a surface of the corresponding drain/source region semiconductor strip 11/13 to be connected with it. The drain/source connection terminals 91a/91b are specifically disposed in the second hard mask layer 99 and are exposed through a side surface of the second hard mask layer 99 away from the filling material 95b. The position of a drain/source connection terminal 91a/91b corresponds to the position of a corresponding drain/source connection plug 94.
Specifically, as shown in
Specifically, further referring to
Specifically, in conjunction with
Specifically, as shown in
The memory block 10 in the embodiments is provided by arranging a drain/source connection terminal array 9 at a predetermined interval in the column direction Y; each drain/source connection terminal array 9 includes multiple drain/source connection terminal subarrays 9a, each drain/source connection terminal subarray 9a corresponding to two adjacent columns of semiconductor strip structures 1b. Each drain/source connection terminal subarray 9a includes multiple drain/source connection terminals 91a/91b, and each drain/source connection terminal 91a/91b is connected to a drain/source region semiconductor strip 11/13 in a corresponding column of semiconductor strip structures 1b, respectively. Each drain/source connection terminal 91a/91b in each drain/source connection terminal subarray 9a is connected to a corresponding drain/source region semiconductor strip 11/13 in a corresponding column of semiconductor strip structures 1b; that is, the same drain/source region semiconductor strip 11/13 of any column of semiconductor strip structures 1b of the memory block 10 is connected to multiple corresponding drain/source connection terminals 91a/91b of multiple corresponding drain/source connection terminals 9a of corresponding columns of one or more drain/source connection terminal arrays 9. In this way, a part of the same drain/source region semiconductor strip 11/13 that is between two adjacent drain/source connection terminals 91a/91b may perform read (RD), program (PGM), and other operations directly through the drain/source connection terminals 91a/91b at corresponding positions. In contrast to leading through a connection line at the end of each drain/source region semiconductor strip 11/13 (i.e., the edge portion of the memory block 10) and performing related operations of the entire drain/source region semiconductor strip 11/13 through the connection line in the related art, the resistance may be reduced to facilitate signal transmission and improve the read (RD), program (PGM), and other operations of the memory block 10 in the present disclosure. In addition, by making the drain/source connection plug 94 made of any one or more of the four metals, copper/titanium/tin/tungsten, with better electrical conductivity, the effect of the resistance of the drain/source connection plug 94 on the signal transmission speed may be reduced.
In addition, the memory block 10 as shown in the above embodiments is arranged with multiple drain/source connection terminal arrays 9, each of which includes multiple drain/source connection terminal subarrays 9a, to achieve connection of the drain/source region semiconductor strips 11/13 in each column of the semiconductor strip structures 1b to the multiple drain/source connection terminals 91a/91b in the multiple drain/source connection terminal subarrays 9a, respectively, thereby achieving improvement of electrical performance.
However, it will be understood by those skilled in the art that the memory block 10 of the present disclosure may be arranged with only one drain/source connection terminal array 9, which may include multiple drain/source connection terminal subarrays 9a, to achieve connection of the drain/source region semiconductor strips 11/13 in each column of the semiconductor strip structures 1b to one drain/source connection terminal 9a/9b in one drain/source connection terminal subarray 9a. Therein, the drain/source connection terminal array 9 may be arranged at a non-edge position of the column of semiconductor strip structures 1b in the column direction Y, i.e., at a position of the column of semiconductor strip structures 1b in the column direction Y that is distinct from the first end and the last end. Since the drain/source connection terminal array 9 may be arranged at a position of the middle region of the column of semiconductor strip structures 1b in the column direction Y, its provision of the drain/source lead region relative to the edge also improves the electrical performance, reduces the resistance, facilitates the signal transmission, and improves the speed of the read (RD), programming (PGM), and other operations performed by the memory block 10.
Specifically, the memory block 10 corresponding to
Referring to
Referring to
The multiple memory subarray layers 1a are sequentially stacked along a height direction Z perpendicular to the substrate 81. Each memory subarray layer 1a includes a drain region semiconductor layer, a channel semiconductor layer, and a source region semiconductor layer stacked along the height direction Z. The drain region semiconductor layer, channel semiconductor layer, and source region semiconductor layer in each memory subarray layer 1a include multiple drain region semiconductor strips 11, channel semiconductor strips 12, and source region semiconductor strips 13, respectively, distributed along a row direction X. Each drain region semiconductor strip 11, channel semiconductor strip 12, and source region semiconductor strip 13 extends along a column direction Y, respectively. Multiple gate strips 2 distributed in the column direction Y are arranged between two adjacent columns of drain region semiconductor strips 11, channel semiconductor strips 12, and source region semiconductor strips 13, and each gate strip 2 extends along the height direction Z.
Multiple isolation walls 3 and multiple gate strips 2 may be further arranged on the semiconductor substrate, the multiple isolation walls 3 and multiple gate strips 2 extending along the height direction Z to the substrate 81, respectively. Other specific structures and manufacturing methods of the semiconductor substrate can be described in the specific structures and manufacturing methods of the memory block provided in any of the above embodiments, which will not be repeated herein.
Referring to
Specifically, multiple drain/source holes 96 in each drain/source holes array 97 distributed along the row direction X are aligned with each other in the column direction Y. Alternatively, as shown in
In some embodiments, multiple drain/source holes 96 may be defined in the semiconductor substrate at intervals of N rows of memory cells to form multiple drain/source holes arrays 97; that is, N rows of memory cells may be arranged between two adjacent regions of the memory cells, such as regions E1 and E2. N may be a natural number greater than or equal to 1. In other embodiments, M rows of memory cells are arranged between two adjacent drain/source holes 96 in the same column, and M may be a natural number greater than or equal to 1. Of course, the distance between each adjacent two regions along the column direction Y may be unequal, i.e., the multiple drain/source holes array 97 may be arranged at non-equal spacing. Alternatively, some of the regions are arranged equally spaced between each adjacent two regions, and the remaining part of the regions are arranged non-equally spaced between each adjacent two regions.
In some embodiments, in the same region (e.g., E1), two adjacent columns (e.g., the first and second columns) of semiconductor strip structures 1b share the same drain/source hole 96. Another drain/source hole 96 is also defined in two adjacent columns (e.g., the first and second columns) of semiconductor strip structures 1b in a region E2 of the semiconductor substrate spaced at a predetermined distance L from region E1.
In conjunction with
As shown in
Each drain/source hole 96 correspondingly forms a corresponding drain/source connection terminal subarray 9a, and multiple drain/source connection terminal subarrays 9a correspondingly formed by multiple drain/source holes 96 in each drain/source hole array 97 constitute a drain/source connection terminal array 9, and each drain/source connection terminal subarray 9a includes multiple drain/source connection terminals 91a/91b. Each drain/source connection terminal 91a/91b is configured to be connected to a corresponding drain/source region semiconductor strip 11/13 of a corresponding column of semiconductor strip structures 1b.
The same drain/source region semiconductor strip 11/13 in each column of semiconductor strip structures 1b is connected to multiple drain/source connection terminals 91a/91b of multiple drain/source connection terminal subarrays 9a in multiple drain/source connection terminal arrays 9.
The same drain/source region semiconductor strip 11/13 in each column of semiconductor strip structures 1b is correspondingly connected to multiple corresponding drain/source connection terminals 91a/91b of multiple corresponding drain/source connection terminal subarrays 9a in corresponding columns in the multiple drain/source connection terminal arrays 9, thereby reducing resistance, facilitating signal transmission, and increasing the speed of this memory block 10 for read (RD), programming (program. PGM) and other operations.
Referring to
In some embodiments, as shown in
In some embodiments, step S43 specifically includes the following.
The specific process of step S432 can be referred to the specific process of step A involved in the above embodiments and can achieve the same or similar technical effect. The structure of the product after processing by step S432 can be seen in
As shown in
In some embodiments, after step S433, the method may further include: thinning the first hard mask layer 83. For example, the first hard mask layer 83 may be thinned by chemical mechanical polishing.
The step-like structure includes multiple steps, each step including a part of a corresponding drain/source region semiconductor strip 11/13. The formation of the step-like structure facilitates the subsequent formation of the drain/source connection plugs 94 to connect the corresponding drain/source region semiconductor strips 11/13.
As shown in
In some embodiments, the drain/source connection terminal subarray region corresponding to the drain/source hole 96 is etched, the drain/source region semiconductor strips 11/13 in the step-like structure may be all drain/source region semiconductor strips 11/13 of the low zone F1 or all drain/source region semiconductor strips 11/13 of the high zone F2. For example, in a second drain/source end group 92b, the drain/source ends 91a/91b may be connected to a drain/source region semiconductor strip 11/13 of the low zone F1 of a column of semiconductor strip structures 1b; and in a first drain/source end group 92a, the drain/source ends 91a/91b may be connected to a drain/source region semiconductor strip 11/13 of the low zone F1 of another column of semiconductor strip structures 1b. Alternatively, in a second drain/source end group 92b, the drain/source ends 91a/91b may be connected to a drain/source region semiconductor strip 11/13 of the high zone F2 of a column of semiconductor strip structures 1b; and in a first drain/source connection terminal group 92a, the drain/source connection terminals 91a/91b may be connected to a drain/source region semiconductor strip 11/13 of the high zone F2 of another column of semiconductor strip structures 1b.
In other embodiments, some of the drain/source region semiconductor strips 11/13 in the step-like structure are drain/source region semiconductor strips 11/13 of the low zone F1 and the others are drain/source region semiconductor strips 11/13 of the high zone F2. That is, the drain/source region semiconductor strip 11/13 corresponding to the high zone F2 and the low zone F1 may be connected to either drain/source connection 91a/91b selectively, as long as all the drain/source region semiconductor strips 11/13 (S/D) are led out. For example, in the second drain/source connection terminal group 92b, the drain/source connection terminals 91a/91b may be connected to the drain/source region semiconductor strips 11/13 in the 1st, 5th, 6th, and 8th memory subarray layers 1a of a column of semiconductor strip structures 1b; while in the first drain/source connection terminal group 92a, the drain/source connection terminals 91a/91b may be connected to the drain/source region semiconductor strips 11/13 in the 2nd, 3rd, 4th, and 7th memory subarray layers 1a of a column of semiconductor strip structures 1b.
The following is an example of forming the step-like structure shown in
Referring to
The drain/source connection terminal subarray region of the first insulating material 95a and the drain/source region semiconductor strip 11/13 of the high zone F2 being a first-type drain/source connection terminal subarray region is removed, and the drain/source connection terminal subarray region of the first insulating material 95a and the drain/source region semiconductor strip 11/13 of the high zone F2 being a second-type drain/source connection terminal subarray region is not removed.
Each step-like structure includes multiple steps, each step including a part of a corresponding drain/source region semiconductor strip 11/13 and a part of the first insulating material 95a wrapping the part of the drain/source region semiconductor strip 11/13. Each step of the high zone F2 and the low zone F1 extends at least partially relative to a previous step.
In some embodiments, referring to
It will be understood by those skilled in the art that the present disclosure requires a total of six etching steps (one step in step A′ and five steps in step B′) to form the six-step step-like structure.
It is understood by those skilled in the art that if the drain/source region semiconductor strips 11/13 in the eight memory subarray layers 1a are etched in a step-like manner without dividing the low zone F1 and high zone F2, 11 steps are required to be formed since the same column of drain/source region semiconductor strips of the eight memory subarray layers 1a include 12 drain/source region semiconductor strips 11/13, i.e., 11 steps of etching are required. Therefore, the above method of the present disclosure can simplify the process steps and reduce the preparation cost.
Among them, the specific process of photomask etching is the same or similar to the related art, which can be found in the related art and will not be repeated herein. The structure of the product after step S434 can be shown in
The structure of the product after processing by step S435 can be seen in
Referring to
In some embodiments, when the filling material 95b is selected to be made of polycrystalline silicon, after the defining the multiple drain/source connection terminal holes 98 and before the filling with the conductive material, step S436 may further include: forming a spacing dielectric layer on a side wall of each drain/source connection terminal hole 98. In other words, the spacing dielectric layer is formed on the side wall of the drain/source connection terminal hole 98 before filling the filling material 95b. It is understood by those skilled in the art that when the filling material 95b is made of an insulating material, such as silicon oxide, then forming the spacing dielectric layer on the surface of the side wall of each drain/source connection terminal hole 98 becomes an optional step, and only filling the drain/source connection terminal hole 98 directly with the filling material 95b is sufficient.
A part of the drain/source connection plug 94 exposed outside of the second hard mask layer 99 may serve as the drain/source connection terminal 91a/91b. An end of each drain/source connection plug 94 is connected to a corresponding drain/source region semiconductor strip 11/13 in a step-like structure. In the embodiments, the drain/source connection terminal subarray region with the first insulating material 95a and the drain/source region semiconductor strip 11/13 of the high zone F2 removed is the first-type drain/source connection terminal subarray region; the drain/source connection terminal subarray region without the first insulating material 95a and the drain/source region semiconductor strip 11/13 of the high zone F2 removed is the second-type drain/source connection terminal subarray region. Multiple drain/source connection terminals 91a/91b formed in the first-type drain/source connection terminal subarray region constitute the first-type drain/source connection terminal subarray, configured to be connected to the drain/source region semiconductor strips 11/13 of the low zone F1 (such as the drain/source region semiconductor strips 11/13 corresponding to the 5th-8th memory subarray layer 1a), respectively; multiple drain/source connection terminals 91a/91b formed in the second-type drain/source connection terminal subarray region constitute the second-type drain/source connection terminal subarray, configured to be connected to the drain/source region semiconductor strips 11/13 of the high zone F2 (such as the drain/source region semiconductor strips 11/13 corresponding to the 1st-4th memory subarray layer 1a), respectively. It is understood that the column of semiconductor strip structures 1b in which a corresponding drain/source region semiconductor strip 11/13 of the high zone F2 is located is in the same column as the column of semiconductor strip structures 1b in which a corresponding drain/source region semiconductor strip 11/13 of the low zone F1 is located.
Based on the above features of the memory block 10, the present disclosure further proposes a memory block 10 including a buried layer and a manufacturing method thereof. In some embodiments, referring to
It is understood by those skilled in the art that the low-resistance conductive structure 101 provided by the embodiments of the present disclosure may be any kind of conductive structure with a resistance value lower than that of monocrystalline silicon, polycrystalline silicon. The material of the low-resistance conductive structure 101 may be a metal, a metal silicide, a metal nitride, or a combination thereof, etc., and the specific material of the low-resistance conductive structure 101 is not limited herein.
Specifically, the low-resistance conductive structure 101 is embedded in the drain region semiconductor strip 11 and/or the source region semiconductor strip 13 of the semiconductor stacked strip structure 1c. By such a design, the drain region semiconductor strip 11 and/or the source region semiconductor strip 13 of the semiconductor stacked strip structure 1c has a low internal resistance, which may enhance the conductivity of the drain region semiconductor strip 11 and/or the source region semiconductor strip 13, thereby enhancing the conductivity of the semiconductor stacked structure 1c, enhancing the response speed of the memory array, and optimizing the performance of the memory block.
Specifically, in some embodiments, continuing to refer to
The drain region semiconductor strips 11, the channel semiconductor strips 12, and the source region semiconductor strips 13 that are in the same column are stacked to form a column of semiconductor stacked strip structure 1c. In the embodiments, the column of semiconductor stacked strip structure 1c is formed by stacking multiple drain region semiconductor strips 11, multiple channel semiconductor strips 12, and multiple source region semiconductor strips 13 that are in the same column. However, it may be appreciated by those skilled in the art that in the present disclosure, the memory array 1 may include only one memory subarray layer 1a, i.e., the column of semiconductor stacked strip structure 1c is formed by stacking one drain region semiconductor strip 11, one channel semiconductor strip 12, and one source region semiconductor strip 13 that are in the same column. The memory array 1 of the present disclosure is not limited to a three-dimensional memory array described by the above embodiments, including multiple memory cells distributed in a three-dimensional array; alternatively, the memory array 1 may be of a two-dimensional structure, such as a two-dimensional NOR Flash, with the source and drain located in the substrate, and a floating gate and a control gate located above between the source and drain, where the low-resistance conductive structure 101 is located, at least partially, in the source and/or the drain. This structure may be realized by processes such as etching, deposition, etc., and is not described herein.
It will be appreciated by those skilled in the art that each drain region semiconductor strip 11, channel semiconductor strip 12, and source region semiconductor strip 13 may be a semiconductor strip formed by processing the drain region semiconductor layer 11c, channel semiconductor layer 12c, and source region semiconductor layer 13c formed by epitaxial generation, respectively. Multiple gate strips 2 are arranged on each side of each column of drain region semiconductor strips 11, channel semiconductor strips 12, and source region semiconductor strips 13, respectively; the multiple gate strips 2 distributed on a side of each column of drain region semiconductor strips 11, channel semiconductor strips 12, and source region semiconductor strips 13 are spaced along the column direction; and each gate strip 2 extends along the height direction, such that corresponding parts of the multiple drain region semiconductor strips 11, channel semiconductor strips 12, and source region semiconductor strips 13 in the same column in the multiple memory subarray layers 1a share a same gate strip 2.
In some embodiments, each drain region semiconductor strip 11 and/or each source region semiconductor strip 13 in each column of semiconductor stacked strip structure 1c at a non-edge position includes a low-resistance conductive structure.
Specifically, the low-resistance conductive structure 101 is embedded in the drain region semiconductor strip 11 and/or source region semiconductor strip 13 in each column of semiconductor stacked strip structure 1c at a non-edge position; and the drain region semiconductor strip 11 and/or source region semiconductor strip 13 in the semiconductor stacked strip structure 1c at an edge position is not embedded with the low-resistance conductive structure 101. As described in the above embodiments, since the memory cell corresponding to the semiconductor stacked strip structure 1c at an edge position serves as a virtual memory cell in some embodiments, the drain region semiconductor strip 11 and/or the source region semiconductor strip 13 in the semiconductor stacked strip structure 1c at an edge position is not required to be arranged with the low-resistive conductive structure 101. Whereas in each column of semiconductor stacked strip structure 1c at a non-edge position, each drain region semiconductor strip 11 and/or source region semiconductor strip 13 includes the low-resistive conductive structure 101, such that each drain region semiconductor strip 11 and/or source region semiconductor strip 13 in each column of semiconductor stacked strip structure 1c at a non-edge position corresponding to an actual memory cell has a lower internal resistance, which may enhance the conductivity of each drain region semiconductor strip 11 and/or source region semiconductor strip 13, thereby enhancing the conductivity of the semiconductor stacked structure 1c, enhancing the response speed of the memory array and optimizing the performance of the memory block. Furthermore, it is more easily implemented in the manufacturing process and improves the yield rate due to the fact that it is not necessary to process the semiconductor stacked strip structure 1c at an edge position. Of course, it can be understood by those skilled in the art that, in some embodiments, each drain region semiconductor strip 11 and/or source region semiconductor strips 13 in the semiconductor stacked strip structure 1c at an edge position may be arranged with the low-resistance conductive structure 101.
The memory array 1 of the present disclosure is formed with multiple memory cells arranged in an array, and the multiple memory cells are included by the drain region semiconductor strips 11, the channel semiconductor strips 12, the source region semiconductor strips 13, and the gate strips 2. In particular, the memory array 1 of the present disclosure includes multiple memory subarray layers 1a stacked sequentially along the height direction. Each memory subarray layer 1a includes a layer of drain region semiconductor strips 11, a layer of channel semiconductor strips 12, a layer of source region semiconductor strips 13, and parts of gate strips 2 matching the above layers, such that each memory subarray layer 1a includes a layer of array-arranged memory cells along the height direction, and the stacked multiple memory subarray layers 1a constitute multiple layers of memory cells arrayed along the height direction.
In a specific embodiment, referring to
Specifically, the first semiconductor substructure 102a and the second semiconductor substructure 102b are two identical semiconductor substructures of the same column of semiconductor strip structure divided by the insulating isolation structure 102c along the column direction Y perpendicular to the substrate 81. The first semiconductor substructure 102a includes a first drain region semiconductor sub-strip 103a, a first channel semiconductor sub-strip 104a, and a first source region semiconductor sub-strip 105a; and the second semiconductor substructure 102b includes a second drain region semiconductor sub-strip 103b, a second channel semiconductor sub-strip 104b, and a second source region semiconductor sub-strip 105b. In addition, the first semiconductor substrate 102a and the second semiconductor substructure 102b further each include an interlayer isolation structure 112.
In a specific embodiment, referring to
It should be noted that the second drain/source region semiconductor layer structure 106b/107b is of a single-crystal silicon germanium (SiGe) semiconductor structure, and compared to other materials, the single-crystal silicon germanium (SiGe) semiconductor structure has a lattice structure similar to that of a single-crystal silicon (Si) semiconductor structure, capable of epitaxial growth on a single-crystal silicon (Si) semiconductor structure at a high quality, and the single-crystal silicon (Si) semiconductor structure is also capable of epitaxial growth on a single crystal silicon germanium (SiGe) semiconductor structure at a high quality. Therefore, the above material features are favorable for the second drain region semiconductor layer structure 106b to be arranged between the first drain region semiconductor layer structure 106a and the third drain region semiconductor layer structure 106c; and also for the second source region semiconductor layer structure 107b to be arranged between the first source region semiconductor layer structure 107a and the third source region semiconductor layer structure 107c.
In a specific embodiment, continuing to refer to
The lengths of the second drain/source region semiconductor layer structure 106b/107b may be greater than, less than, or equal to the lengths of the drain/source region filling space 108a/108b. The lengths of the second drain/source region semiconductor layer structure 106b/107b is not limited herein. The drain region low-resistance conductive layer structure 109a, within the drain region filling space 108a, may reduce the resistance of the first drain region semiconductor sub-strip 103a and the second drain region semiconductor sub-strip 103b, thereby enhancing the conductivity of the drain region semiconductor layer 11c; the source region low-resistance conductive layer structure 109a, within the source region filling space 108b, may reduce the resistance of the first source region semiconductor sub-strip 105a and the second source region semiconductor sub-strip 105b, thereby enhancing the conductivity of the source region semiconductor layer 13c.
In a specific embodiment, in the memory block 10, the drain region low-resistance conductive layer structure 109a and/or the source region low-resistance conductive layer structure 109a is a low-resistance conductive layer structure 109 made of a high-conductivity material. The high-conductivity material includes a metal and/or a metal-silicide material.
Specifically, the highly conductive material may be metal, metal silicide, metal nitride, or combinations thereof, etc. The specific material of the high-conductivity material is not limited herein, and may be any conductive material with a lower resistance than monocrystalline (doped) or polycrystalline (doped) silicon. In some embodiments, the high-conductivity material or the low-resistance conductive layer refers to the material type that is different from the source/drain material (the difference herein does not refer to the difference in material caused by doping) and has a lower resistance than the source/drain material. The low-resistance conductive layer structure 109 is prepared using the high-conductivity material, such that a large amount of charge is transmitted between the first drain region semiconductor layer structure 106a and the third drain region semiconductor layer structure 106c through the drain region low-resistance conductive layer structure 109a; and a large amount of charge is transmitted between the first source region semiconductor layer structure 107a and the third source region semiconductor layer structure 107c through the source region low-resistance conductive layer structure 109a, thereby reducing the resistance of the first drain/source region semiconductor sub-strips 103a/105a and the second drain/source region semiconductor sub-strips 103b/105b, thereby enhancing the electrical conductivity, enhancing the electrical conductivity, and enhancing the responsiveness of the memory block 10.
In a specific embodiment, continuing to referring to
It should be noted that, ideally, the conductive layer structure 110 may fill the drain region filling space 108a or the source region filling space 108b in its entirety.
Specifically, a first side of the first conductive layer structure 110a is connected to a surface of the second conductive layer structure 110b facing the insulating isolation structure 102c, a second side of the first conductive layer structure 110a is connected to the insulating isolation structure 102c, and the first side of the first conductive layer structure 110a and the second side of the first conductive layer structure 110a are opposite each other. A first side of the third conductive layer structure 110c is connected to a surface of the second conductive layer structure 110b facing the insulating isolation structure 102c, a second side of the third conductive layer structure 110c is connected to the insulating isolation structure 102c, and the first side of the third conductive layer structure 110c and the second side of the third conductive layer structure 110c are opposite each other. An upper surface of the first conductive layer structure 110a and a lower surface of the third conductive layer structure 110c are spaced apart from each other. During the operation of the memory, charges passing through the drain/source region low-resistance conductive layer structure 109a/109b may move between the corresponding first conductive layer structure 110a, second conductive layer structure 110b, and third conductive layer structure 110c to form a charge channel, thereby enhancing the conductivity of the second drain/source region semiconductor layer structure 106b/107b.
In addition, according to the different manufacturing methods described below, the drain region low-resistance conductive layer structure 109a or the source region low-resistance conductive layer structure 109b of the present disclosure may be formed into corresponding different structures according to the different manufacturing methods, and the structure of the drain region low-resistance conductive layer structure 109a or the source region low-resistance conductive layer structure 109b illustrated in
Specifically, referring to
It should be noted that the first conductive layer structure 110a, the second conductive layer structure 110b, the third conductive layer structure 110c, the fourth conductive layer structure 110d, and the fifth conductive layer structure 110e may be conductive layer structures connected together. In this manner, the process complexity of the first conductive layer structure 110a, the second conductive layer structure 110b, the third conductive layer structure 110c, the fourth conductive layer structure 110d, and the fifth conductive layer structure 110e during processing can be reduced, thereby increasing productivity.
In another specific embodiment, referring to
In addition, in the above embodiments, the first conductive layer structure 110a, the second conductive layer structure 110b, and the third conductive layer structure 110c may each further include a second low-resistance layer 110g, where the second low-resistance layer 110g is attached to a surface of the first low-resistance layer 110f; the material of the second low-resistance layer 110g includes titanium or tantalum, or the material of the second low-resistance layer 110g includes a combination layer of titanium and another metal, or a combination layer of tantalum and another metal.
It should be noted that the first conductive layer structure 110a, the second conductive layer structure 110b, and the third conductive layer structure 110c may be conductive layer structures connected together. That is, the first low-resistance layer 110f and the second low-resistance layer 110g may each be an integrated conductive layer structure. In this manner, the process complexity of the first conductive layer structure 110a, the second conductive layer structure 110b, and the third conductive layer structure 110c during processing may be reduced, and the production efficiency may be improved. For specific manufacturing processes, reference may be made to the following.
Alternatively, in further another specific embodiment, referring to
It is noted that an isolation layer may be arranged between the first conductive layer structure 110a, the second conductive layer structure 110b, and the third conductive layer structure 110c and the drain/source region semiconductor layer structure, to prevent the metal from diffusing in the silicon. The material of the isolation layer is not limited herein.
In a specific embodiment, the structure made by each of the methods described above has the first conductive layer structure 110a and the third conductive layer structure 110c spaced apart from each other so as to define a first space 111 in conjunction with the second conductive layer structure 110b to be filled with an insulating substance. In this manner, a morphologically complete and compact low-resistance conductive structure 101 is formed.
In a specific embodiment, continuing to refer to
It is noted that the memory block 10 further includes a drain/source connection terminal subarray 9a between each adjacent two columns of semiconductor stacked strip structures 1c. In the embodiments, the drain/source connection terminal subarray 9a is connected to a column of first semiconductor substructures 102a and a column of second semiconductor substructures 102b. The drain/source connection terminal subarray 9a includes multiple drain/source connection terminals 91a/91b, where each of the drain/source connection terminals 91a/91b is connected to a corresponding drain region semiconductor strip 11 or source region semiconductor strip 13, respectively, in a corresponding semiconductor stacked strip structure 1c.
Specifically, referring to
Under this structure, continuing to refer to
Specifically, continuing to referring to
In contrast to the memory block 10 shown in
That is, similar to the embodiment shown in
Furthermore, referring to
In this case, continuing to refer to
Furthermore, as described above, the correspondence between the drain/source connection terminal subarray 9a and the drain region semiconductor strip 11 and the source region semiconductor strip 13 in each column of semiconductor stacked strip structure 1c is similar to that of
That is, in the embodiments shown in
For example, for an 8-layer memory subarray layer 1a, each column of semiconductor stacked strip structure 1c includes 8 drain region semiconductor strips 11 and 4 source region semiconductor strips 13, for a total of 12 drain/source semiconductor strips. Therefore, it is necessary to form a 12-step ladder to lead out each drain/source region semiconductor strip separately.
In a specific embodiment, continuing to refer to
Specifically, each memory subarray layer 1a correspondingly includes a drain region semiconductor layer 11c, a source region semiconductor layer 13c, and a drain region semiconductor layer 11c that are spaced apart. In each memory subarray layer 1a, a channel semiconductor layer 12c is arranged between the drain region semiconductor layers lie and the source region semiconductor layers 13c adjacent to the drain region semiconductor layers 11c. As a result, each of the memory subarray layers 1a may correspond to a set of drain/source connection terminals 91a/91b in the drain/source connection terminals 9a. In addition, by means of the interlayer isolation layer 112 arranged on every two memory subarray layers 1a, the two adjacent memory subarray layers 1a may be isolated to prevent the crosstalk of signals from the different drain region semiconductor layers 11c caused by the drain region semiconductor layer 11c of the multiple memory subarray layers 1a contacting with each other, so as to protect the function of the adjacent memory subarray layer 1a for maintaining the performance of the memory block 10. The interlayer isolation layer 112 is made of an insulating oxide, such as silicon dioxide (SiO2). The insulating oxide as the interlayer isolation layer 112 is formed by replacing silicon germanium (SiGe) of the first single-crystal sacrificial semiconductor layer 82 and the second single-crystal sacrificial semiconductor layer 14, as described in the above embodiments.
In combination with the structure of the memory block 10 of the above embodiments, under the action of the low-resistance conductive structure 101, the resistance of the drain region semiconductor layer 11c and the source region semiconductor layer 13c in the memory block 10 is reduced, the conductivity is enhanced, the response speed is increased, and the performance is enhanced. Due to the enhanced electrical properties of the drain region semiconductor layer 11c and the source region semiconductor layer 13c, the distance for electrical signal conduction thereof may be longer, and therefore, comparing with the memory array 1a shown in
Based on the above memory block 10, the present disclosure provides a memory cell which corresponds to the smallest working unit of the memory block 10. Referring to
Specifically, continuing to refer to
In a specific embodiment, in the memory cell provided by the present disclosure, continuing to refer to
It is understood by those skilled in the art that since the memory cell is a part of the structure of the memory block 10, the specific structure and effect of action within the drain region portion 11′ and the source region portion 13′ within the memory cell are the same as those of the first drain/source region semiconductor sub-strip 103a/105a and the second drain/source region semiconductor sub-strip 103b/105b, which will not be repeated herein.
In a specific embodiment, continuing to refer to
It is understood by those skilled in the art that since the memory cell is a part of the structure of the memory block 10, the specific structure and effect of the drain region low-resistance conductive layer structure 109a and the source region low-resistance conductive layer structure 109b within the memory cell are similar to those of the drain region low-resistance conductive layer structure 109a and the source region low-resistance conductive layer structure 109b within the memory block 10, which will not be further described herein.
In a specific embodiment, in the memory cell provided by the present disclosure, continuing to refer to
It should be noted that, ideally, the conductive layer structure 110 may fill the drain region filling space 108a or the source region filling space 108b in its entirety. The specific effects of the conductive layer structure 110 in the memory cell are similar to the specific effects of the conductive layer structure in the memory block described above, and will not be repeated herein. According to the different manufacturing methods described below, the drain region low-resistance conductive layer structure 109a or the source region low-resistance conductive layer structure 109b in the memory cell provided by the present disclosure may be formed into corresponding different structures according to the different manufacturing methods, and the structure of the drain region low-resistance conductive layer structure 109a or the source region low-resistance conductive layer structure 109b illustrated in
Specifically, referring to
It should be noted that the first conductive layer structure 110a, the second conductive layer structure 110b, the third conductive layer structure 110c, the fourth conductive layer structure 110d, and the fifth conductive layer structure 110e may be conductive layer structures connected together. In this manner, the process complexity of the first conductive layer structure 110a, the second conductive layer structure 110b, the third conductive layer structure 110c, the fourth conductive layer structure 110d, and the fifth conductive layer structure 110e during processing can be reduced, thereby increasing productivity.
In another specific embodiment, referring to
In addition, in the above embodiments, the first conductive layer structure 110a, the second conductive layer structure 110b, and the third conductive layer structure 110c may further include a second low-resistance layer 110g, where the second low-resistance layer 110g is attached to a surface of the first low-resistance layer 110f; the material of the second low-resistance layer 110g includes titanium or tantalum, or the material of the second low-resistance layer 110g includes a combination layer of titanium and another metal, or a combination layer of tantalum and another metal. The first low-resistance layer has a lower electrical conductivity than the second low-resistance layer.
It should be noted that the first conductive layer structure 110a, the second conductive layer structure 110b, and the third conductive layer structure 110c may be conductive layer structures connected together. That is, the first low-resistance layer 110f and the second low-resistance layer 110g may each be an integrated conductive layer structure. In this manner, the process complexity of the first conductive layer structure 110a, the second conductive layer structure 110b, and the third conductive layer structure 110c during processing may be reduced, and the production efficiency may be improved. For specific manufacturing processes, reference may be made to the following.
Alternatively, in further another specific embodiment, referring to
It is noted that an isolation layer may be arranged between the first conductive layer structure 110a, the second conductive layer structure 110b, and the third conductive layer structure 110c and the drain/source region semiconductor layer structure, to prevent the metal from diffusing in the silicon. The material of the isolation layer is not limited herein.
Referring to
Referring to
Subsequently, the embodiments shown in
In a specific embodiment, step S51 may specifically include the following.
The substrate 81 may be made of silicon (Si).
Adjacent two memory subarray layers 1a share a common source region, and the formation of each two memory subarray layers 1a sharing a common source includes the following.
The first drain region semiconductor layer 11, the first channel semiconductor layer 12c1, and the source region semiconductor layer 13c form one memory subarray layer 1a; the source region semiconductor layer 13c, the second channel semiconductor layer 12c2, and the second drain region semiconductor layer 11c2 form another memory subarray layer 1a; and the source region semiconductor layer 13c is shared by the two memory subarray layers 1a.
Referring to
The first hard mask layer 83 may be made of silicon dioxide (SiO2) or silicon nitride (SiN).
Specifically, after the multiple memory subarray layers 1a are divided into multiple columns of semiconductor stacked strip structures 1c along the row direction X, the first drain/source semiconductor sublayer 113a, the second drain/source semiconductor sublayer 113b, and the third drain/source semiconductor sublayer 113c are divided into multiple columns of first drain/source semiconductor sublayer strips 114a, second drain/source semiconductor sublayer strips 114b, and third drain/source semiconductor sublayer strips 114c, respectively. Each drain region semiconductor strip 11 and/or each source region semiconductor strip 13 in the semiconductor stacked strip structure 1c includes a corresponding first drain/source semiconductor sublayer strip 114a, a second drain/source semiconductor sublayer strip 114b, and a third drain/source semiconductor sublayer strip 114c, respectively.
By etching, the semiconductor stacked strip structure 1c defines the isolation opening 115, thereby obtaining the semiconductor stacked strip structure 1c having the isolation opening 115, the first semiconductor substructure 102a, and the second semiconductor substructure 102b. The depth of the isolation opening 115 starts from the first hard mask layer 83, and is along the height direction Z up to the interior of the substrate 81. Specifically, after defining the isolation opening 115 in each column of semiconductor stacked strip structure 1c at a non-edge position to divide the corresponding semiconductor stacked strip structure 1c into the first semiconductor substructure 102a and the second semiconductor substructure 102b, each drain region semiconductor sub-strip and each source region semiconductor sub-strip in the first semiconductor substructure 102a includes a corresponding first drain/source semiconductor layer structure 106a/107a, a second drain/source semiconductor layer structure 106b/107b, and a third drain/source semiconductor layer structure 106c/107c, respectively; each drain region semiconductor sub-strip and each source region semiconductor sub-strip in the second semiconductor substructure 102b includes a corresponding first drain/source semiconductor layer structure 106a/107a, a second drain/source semiconductor layer structure 106b/107b, and a third drain/source semiconductor layer structure 106c/107c, respectively.
In a specific embodiment, step S53 may specifically include the following.
In a specific embodiment, in conjunction with
It is noted that the first sacrificial semiconductor layer 82, the second sacrificial semiconductor layer 14, and the second drain/source semiconductor layer structure 103b/105b may be made of the same material.
Specifically, the portion of each of the first sacrificial semiconductor layer 82, the second sacrificial semiconductor layer 14, and the second drain/source semiconductor layer structure 103b/105b in each of the first semiconductor substructure 102a and the second semiconductor substructure 102b are etched in a direction from the isolation opening 115 toward a corresponding one of the first semiconductor substructure 102a and the second semiconductor substructure 102b, to remove a portion of silicon germanium (SiGe) in the first sacrificial semiconductor layer 82, the second sacrificial semiconductor layer 14, and the second drain/source semiconductor layer structure 103b/105b. At the isolation opening 115, each of the first sacrificial semiconductor layer 82, the second sacrificial semiconductor layer 14, and the second drain/source semiconductor layer structure 103b/105b defines the first recessed groove 116, and the first recessed groove 116 is opened toward the isolation opening 115.
It will be appreciated by those skilled in the art that the first semiconductor substructure 102a and the second semiconductor substructure 102b each defines the first recessed groove 116 in each of the first sacrificial semiconductor layer 82, the second sacrificial semiconductor layer 14, and the second drain/source semiconductor layer structure 103b/105b at the location of the isolation opening 115. That is, the first semiconductor substructure 102a and the second semiconductor substructure 102b are simultaneously subjected to etching at the same height to define the first recessed grooves 116, respectively. Subsequent steps will all be performed simultaneously in the first semiconductor substructure 102a and the second semiconductor substructure 102b.
Specifically, the protective dielectric layer 117 may be made of silicon nitride (SiN). The protective dielectric layer 117 covers exposed surfaces of the first semiconductor substructure 102a and the second semiconductor substructure 102b by deposition, i.e., in the removed portions of the first sacrificial semiconductor layer 82 and the second sacrificial semiconductor layer 14, the protective dielectric layer 117 is formed in the shape of a groove as a first protective recess 118; the removed portions of the second drain/source semiconductor layer structure 103b/105b are filled with the protective dielectric layer 117; a surface of the isolation opening 115 is formed with the protective dielectric layer 117. Of course, in other embodiments, the protective dielectric layer 117 may further be formed on the first hard mask layer 83.
The protective dielectric layer 117 may be formed by chemical vapor deposition (CVD), which may specifically be plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD). The specific method of chemical vapor deposition is not limited herein.
Specifically, the method of removing the protective dielectric layer 117 in the first recessed grooves 116 corresponding to the first sacrificial semiconductor layer 82 and the second sacrificial semiconductor layer 14 is to etch the first semiconductor substructure 102a and the second semiconductor substructure 102b in the direction from the isolation opening 115 toward a corresponding one of the first semiconductor substructure 102a and the second semiconductor substructure 102b. In the process of removing the protective dielectric layer 117 in the first recessed grooves 116 corresponding to the first sacrificial semiconductor layer 82 and the second sacrificial semiconductor layer 14, the protective dielectric layer 117 on the surface of the isolation opening 115 and the protective dielectric layer 117 on the first hard mask layer 83 may further be removed. The protective dielectric layer 117 in the first recessed groove 116 that is removed is the first protective recess 118, to expose the residual part of the first sacrificial semiconductor layer 82 and second sacrificial semiconductor layer 14.
Specifically, silicon germanium (SiGe) remaining in the first sacrificial semiconductor layer 82 and the second sacrificial semiconductor layer 14 is removed by etching. The etching method may be dry etching or wet etching, which is not limited herein.
Steps S5311-S5314 aim to remove the silicon germanium (SiGe) of the first sacrificial semiconductor layer 82 and the second sacrificial semiconductor layer 14 while retaining a portion of the silicon germanium (SiGe) in the second drain/source semiconductor layer structure 103b/105b, and to define the first recessed groove 116 in the second drain/source semiconductor layer structure 103b/105b proximate the isolation opening 115. In this manner, the function of the second drain/source semiconductor layer 103b/105b in stabilizing the structure and enhancing the electrical conductivity in the memory cell structure may be maintained, and space may be reserved for the subsequent introduction of the low-resistance conductive structure 101.
Specifically, the insulating material of the insulating isolation layer 14′ may be an oxide, such as silicon dioxide (SiO2). The insulating isolation layer 14′ is covered on the exposed surfaces of the first semiconductor substructure 102a and the second semiconductor substructure 102b by deposition, i.e., the positions of the first sacrificial semiconductor layer 82 and the second sacrificial semiconductor layer 14 are filled with the insulating material, and the first sacrificial semiconductor layer 82 and the second sacrificial semiconductor layer 14 are replaced with the insulating isolation layer 14′; the insulating isolation layer 14′ is formed on the surface of the isolation opening 11; and the insulating isolation layer 14′ is formed on the first hard mask layer 83. The insulating isolation layer 14′ may be formed by atomic layer deposition (ALD), and the specific deposition method is not limited herein.
Specifically, the insulating isolation layer 14′ formed on the sidewall of the isolation opening 115 and the insulating isolation layer 14′ formed on the first hard mask layer 83 are removed by wet etching, and the insulating isolation layer 14′ for replacing the first sacrificial semiconductor layer 82 and the second sacrificial semiconductor layer 14 is retained. In the process of removing the insulating isolation layer 14′ formed on the sidewall of the isolation opening 115, a solution applied for wet etching may be a hydrofluoric acid (HF) solution, and the specific wet etching method is not limited herein.
Steps S5315-S5316 aim to form the insulating isolation layer 14′ with an oxide as an insulating material, for replacing the first sacrificial semiconductor layer 82 and the second sacrificial semiconductor layer 14 and spacing adjacent two layers memory subarray layers 1a that are not co-sourced, so as to enable each of two co-sourced memory subarray layers 1a to form an independent workspace, thereby preventing the memory cell from inter-cell signal crosstalk.
Specifically, the portion of each of the channel semiconductor sub-strips 104a/104b in each of the first semiconductor substructure 102a and the second semiconductor substructure 102b are etched in a direction from the surface of the isolation opening 115 toward the isolation wall 3 to remove the portions of the channel semiconductor sub-strips 104a/104b. The second recessed grooves 119 are defined in the portions of the channel semiconductor sub-strips 104a/104b that have been removed. In addition, since the etching process also acts on the oxide therefore a portion of the insulating isolation layer 14′ is also removed in the direction from the surface of the isolation opening 115 toward the isolation wall 3.
Specifically, the insulating material of the insulating isolation layer 119 may be an oxide, such as silicon dioxide (SiO2). The insulating isolation layer 119 is covered on the exposed surfaces of the first semiconductor substructure 102a and the second semiconductor substructure 102b by deposition, i.e., the insulating isolation layer 14′ is formed by filling the second recessed groove 119 with the insulating material; at the removed portion of the insulating isolation layer 14′, the insulating isolation layer 14′ is formed again; on the surface of the isolation opening 115, the insulating isolation layer 14′ is formed; and on the first hard mask layer 83, the insulating isolation layer 14′ is formed. The insulating isolation layer 14′ may be formed by atomic layer deposition (ALD), and the specific deposition method is not limited herein.
In a specific embodiment, step S532 may specifically include the following.
Specifically, the insulating isolation layer 14′ formed on the sidewall of the isolation opening 115 is removed by wet etching. A solution applied for wet etching in the process of removing the insulating isolation layer 115 formed on the sidewall of the isolation opening 115 may be a hydrofluoric acid (HF) solution, and the specific wet etching method is not limited herein.
Specifically, the protective dielectric layer 117 in the first recessed groove 116 is removed by wet etching to expose the second drain/source region semiconductor layer structure 106b/107b.
Specifically, the silicon germanium (SiGe) material of the exposed second drain/source semiconductor layer structure 106b/107b is removed by wet etching in a direction from the isolation opening toward the isolation wall 3.
In a specific embodiment, step S533 may specifically include three different ways: S533a, S533b and S533c, respectively.
Referring to
Specifically, with continued reference to
It should be noted that the temperature of the heat treatment is determined by the reaction temperature required for different metals to react with the silicon material and is not limited herein.
Specifically, with continued reference to
Specifically, with continued reference to in
Referring to
Specifically, with continued reference to
Specifically, with continued reference to
In some embodiments, the titanium (Ti) or tantalum (Ta) material is deposited on its metal nitride, i.e., when the first low-resistance layer 110f is made of titanium nitride (TiN), the material of the second low-resistance layer 110g corresponds to the titanium (Ti) metal 120; and when the first low-resistance layer 110f is made of titanium nitride (TaN), the material of the second low-resistance layer 110g corresponds to the titanium (Ta) metal 120. The first low-resistance layer may improve the drain resistance on one hand, and on the other hand, provide a more suitable deposition surface for the deposition of the second low-resistance layer 110g (if any).
Specifically, with continued reference to
Specifically, with continued reference to
It should be noted that only the first low-resistance layer 110f may be deposited on the inner surface of the drain/source filled space 108a/108b, i.e., step S5331b may be directly followed by step S5333b and the low-resistance conductive structural body 101 may be formed by a subsequent step. In an embodiment corresponding to this case, etching is performed in a direction from the isolation opening toward a corresponding one of the first semiconductor substructure and the second semiconductor substructure, for removing residual titanium nitride (TiN) or tantalum nitride (TaN) material on the sidewall of the isolation opening instead of the second low-resistance layer 110g.
Referring to
Specifically, the metal, such as tungsten (W), is deposited within the drain/source region filling space 108a/108b and on the sidewall of the isolation opening 115. The method of deposition may be chemical vapor deposition (CVD) or physical vapor deposition (PVD), and the specific deposition method is not limited herein.
Specifically, with continued reference to
Specifically, with continued reference to
The memory block 10 provided in the present disclosure each the low-resistance conductive structure 101. The source/drain region semiconductor layer 11c/13c having the low-resistance conductive structure 101 has a higher electron mobility, and thus is more conductive and has a lower resistance, which may lead to an elevated power utilization rate, a lower heat generation, and an elevated response speed of the memory block. In addition, due to the elevated power utilization rate, the drain/source connection terminal subarray for renewing the voltage in the memory block may be reduced in number or removed, and the drain/source connection terminal subarray 9a of the semiconductor stacked strip structure 1c in the memory block 10 may be made to lead out from the edge of the stepped structure only, thereby increasing the space utilization rate of the memory block and saving the cost of materials.
The above is only some embodiments of the present disclosure, and is not intended to limit the scope of the present disclosure. Any equivalent structure or equivalent process transformation using the contents and the accompanying drawings of the present disclosure, or any direct or indirect application in other related technical fields, is included in the scope of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202310187788.0 | Feb 2023 | CN | national |
