Patent Application
20070037345
The invention further relates to a memory cell array including plurality of memory cells such as, for example, DRAM (dynamic random access memory) cells, as well as a method of forming the memory cell array.
Memory cells of a dynamic random access memory (DRAM) generally include a storage capacitor for storing an electrical charge, which represents information to be stored and an access transistor connected with the storage capacitor. The access transistor includes first and a second source/drain regions, a channel connecting the first and second source/drain regions as well as a gate electrode controlling an electrical current flowing between the first and second source/drain regions. The transistor usually is at least partially formed in a semiconductor substrate. The portion in which the transistor is formed generally is denoted as the active area. The gate electrode forms part of a word line, and it is electrically isolated from the channel by a gate dielectric. By addressing the access transistor via the corresponding word line, the information stored in the storage capacitor is read out. In particular, the information is read out to a corresponding bit line via a bit line contact.
In the currently used DRAM cells, the storage capacitor can be implemented as a trench capacitor in which the two capacitor electrodes are disposed in a trench that extends in a substrate in a direction perpendicular to the substrate surface.
In another implementation of the DRAM memory cell, the electrical charge is stored in a stacked capacitor, which is formed above the surface of the substrate. A problem associated with DRAM memory cells including stacked capacitors is that it is necessary to electrically isolate adjacent active areas, which are assigned to one row of memory cells, from each other.
In addition, a DRAM cell array having a higher packaging density is generally desirable. For example U.S. Pat. No. 6,545,904, the disclosure of which is incorporated herein by reference in its entirety, discloses a memory cell including an access transistor and a storage capacitor, which can be formed so as to implement a 6F2 (6 F×F) DRAM array. In particular, two neighboring access transistors are arranged so that they have a common bit line contact. In addition, neighboring access transistors formed on a single active area line are electrically isolated from each other by an isolation gate line.
Moreover, DE 199 28 781 C1 discloses a 6 F2 memory cell in which two adjacent memory cells share one common bit line contact. Two neighboring pairs of memory cells which are formed in one active area line are separated and electrically isolated from each other by a groove which is filled with an isolating material.
In addition, H. S. Kim at al., “An outstanding and highly manufacturable 80 nm DRAM technology”, IEDM 2003, discloses a memory cell array in which two adjacent memory cells share one common bit line contact. The storage capacitor is implemented as a stacked capacitor. Neighboring active areas, which are assigned to one row of active areas, are electrically insulated from each other by an isolation groove, the length of this isolation groove being very large.
Moreover, when scaling down the structural feature size F of the memory cell for reducing the area needed for a memory cell, the distance between the heavily doped source/drain regions shrinks resulting in a problem with the data retention time, i.e., the time during which information is recognizably stored in the storage capacitor. To maintain the distance between the first and the second source/drain regions while reducing the typical feature size, recessed channel array transistors have been proposed.
In accordance with one embodiment of the invention, a method of forming a memory cell array comprises the following steps: providing a semiconductor substrate including a surface; defining a plurality of isolation trenches in the surface of the semiconductor substrate that laterally confine a plurality of active areas in which transistors are to be formed, one active area being laterally confined by two isolation trenches, respectively; filling the isolation trenches with an isolating material; providing a plurality of word lines intersecting the active areas, each of the word lines being insulated from the active areas by a gate insulating material; providing a plurality of isolation grooves, the isolation grooves being configured to insulate neighboring active areas from each other, the isolation grooves intersecting the isolation trenches; providing a plurality of transistors which are at least partially formed in the active areas, each of the transistors comprising a first and a second source/drain region, a channel connecting the first and second source/drain region and a gate electrode forming part of a corresponding one of the word lines; providing a plurality of storage capacitors on the surface of the semiconductor substrate, each of the storage capacitors comprising a storage electrode, a counter electrode and a capacitor dielectric; connecting each of the storage electrodes with a corresponding one of the first source/drain regions; providing a plurality of bit lines, a plurality of second source/drain regions being connected with a corresponding one of the bit lines. The step of providing the isolation grooves further comprises the steps of covering predetermined portions of the substrate surface with a masking material, etching the semiconductor substrate at portions of the substrate surface that are not covered with word lines or with the masking material, and filling the isolation grooves with an isolating material.
Initially, isolation trenches are patterned and filled with an insulating material, thereby defining active area lines. In particular, the isolation trenches are patterned as straight lines, resulting in the active area lines being formed as straight lines. After defining the word lines incorporating a plurality of gate electrodes, the isolation grooves are formed by etching the semiconductor substrate material using the gate electrodes as an etching mask. As a consequence, the active area segments are isolated from each other by a self-aligned etching step. Thus, advantageously, an isolation groove having a small width can be provided. As a result, the packaging density of the memory cells can be increased. The isolation grooves are formed so as to intersect the isolation trenches. In other words, the isolation grooves are not parallel with the isolation trenches. For example, the isolation trenches can be perpendicular with respect to the isolation grooves.
In addition, according to the present invention the first source/drain regions are formed at a position adjacent to the isolation groove. Advantageously, the first source/drain regions are formed after the step of defining the isolation grooves and filling the isolation grooves with an insulating material. Moreover, it is preferred that two memory cells are formed in one active area segment, the two memory cells sharing one common bit line contact.
According to the present invention, it is preferred that the word lines are covered with an isolating layer at a top side and the lateral sides thereof. In addition, it is preferred that this isolating layer is removed at least from the lateral sides of the word lines. Thereafter, a capacitor contact is formed at a position between the isolation groove and the remaining portion of the isolating layer.
Moreover, it is more preferable that the isolating layer, which is present on the top side of the word lines, comprises first and a second layers, where the second layer is provided on top of the first layer, the first layer being in contact with the gate electrode, and where the second layer can be selectively etched with respect to the first layer. Subsequently, an etching step is performed to selectively etch the second layer, so as to form the capacitor contact having well defined horizontal boundaries.
In accordance with another embodiment of the present invention, a memory cell array comprises memory cells, each of the memory cells comprising a storage capacitor and a transistor, and a semiconductor substrate, wherein active areas, isolation trenches and isolation grooves are formed in the semiconductor substrate. Each of the active areas includes a length along a first direction and a width along a second direction, the length being larger than the width. The isolation trenches are adjacent to the active areas and extend in the first direction, while the isolation grooves are adjacent to the active areas and extend in the second direction. The isolation trenches and the isolation grooves are configured to electrically isolate neighboring active areas from each other. The transistors are at least partially formed in the active areas and electrically couple corresponding storage capacitors to corresponding bit lines via bit line contacts, the transistors being addressed by the word lines. The following relation holds between the length L of the active areas and the distance D between neighboring active areas, the distance being measured in the first direction: D<0.287*L.
Due to the small distance between neighboring active areas of the memory cell array of the present invention, the packaging density of the memory cell array can advantageously be increased.
In addition, it is preferred to implement the storage capacitors as stacked capacitors, which are formed above the surface of the substrate. In particular, it is preferred to arrange the storage capacitors in a checkerboard pattern in which the capacitors are arranged in rows, the capacitors of the rows having an uneven row number being arranged in a first grid, the capacitors of the rows having an even row number being arranged in a second grid, and the first and the second grid being offset to each other, so that the capacitors of the even rows are disposed at half of the pitch of the capacitors of the uneven rows and vice versa. An advantage is thus obtained, in which a checkerboard layout is easier to implement in terms of the lithographical steps employed. In addition, by using such a pattern of capacitors, the packaging density of the capacitors can be further increased.
In accordance with a further embodiment of the present invention, a memory cell comprises a semiconductor substrate including a surface, a storage capacitor comprising a storage electrode, a capacitor dielectric and a counter electrode, the storage capacitor being formed above the surface of the semiconductor substrate, a transistor comprising a first and a second source/drain region, a channel connecting the first and second source/drain region and a gate electrode that is configured to control the conductivity of the channel, the first and the second source/drain regions forming part of the semiconductor substrate and a first direction being defined by the direction of the channel, and a bit line contact for connecting the second source/drain region with a corresponding bit line. The storage electrode of the storage capacitor is connected with the first source/drain region via a capacitor contact, the capacitor contact comprising a vertical portion extending perpendicular with respect to the substrate surface and a horizontal portion extending in the first direction parallel to the substrate surface. The bit line contact comprises only a vertical portion extending perpendicular with respect to the substrate surface.
By providing capacitor contacts having such an angled shape, the geometric arrangement of the capacitors and the connection thereof with the transistors is further simplified.
The above and still further objects, features and advantages of the present invention will become apparent upon consideration of the following detailed description of specific embodiments thereof, wherein like numerals designate like components in the drawings.
In the following description of the invention, reference is made to the accompanying drawings, in which are illustrated exemplary embodiments. It is noted that directional terminology such as “top”, “bottom”, “front”, “back”, “leading”, “trailing”, etc., is used with reference to the orientation of the figures being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used solely for purposes of illustration of the embodiments in the figures and in no way is the invention to be considered limiting to such exemplary orientations of the figures. It is to be understood that other embodiments may be utilized and structural or logical changes can be made without departing from the scope of the present invention. The following description of exemplary embodiments, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
In accordance with the present invention, a memory cell array is formed by first providing a semiconductor substrate, such as a silicon substrate, which can be p-doped. In a first step, the active area lines are defined by patterning isolation trenches. For example, isolation trenches 12 can be photolithographically patterned using a mask having a lines/spaces pattern. In particular, the line width and the width of the spaces can be 1 F, wherein F denotes the minimal structural feature size or ground rule of the technology employed. For example, F can be 100 nm, and less, in particular 80 nm, 75 nm, 65 nm or even smaller dimensions. The isolation trenches 12 are etched so as to have a depth of approximately 220 nm or greater, if F is 80 nm. This depth can potentially be reduced for smaller ground rules. Thereafter, the isolation trenches 12 are filled, for example, by performing a thermal oxidation step for providing a silicon dioxide layer (not shown), optionally, depositing a thin silicon nitride layer (not shown), followed by a silicon dioxide layer (not shown). Finally, the isolation trenches are completely filled with an isolating material 32. Then, a planarizing step is performed.
A plan view on the resulting structure is shown in
In the next step, implantation is performed to provide the doped well portions. Then, a silicon dioxide layer 86 forming a gate oxide layer is deposited, followed by the layer stack for forming the gate electrode. In particular, the gate electrode 85 is made of a layer stack including a tungsten silicide/polysilicon bilayer of a polysilicon layer having a thickness of 60 nm followed by a WSix layer having a thickness of 40 nm for the 80 nm ground rule. Thereafter, a silicon nitride layer 80 having a thickness of approximately 100 nm is deposited at a ground rule of 80 nm. In the next step, the word lines are photolithographically patterned using a mask having a lines/spaces pattern. In particular, the word lines are patterned so that they have a line width of 1 F and a distance of 1.6 F. Thereafter, a sidewall oxide is thermally grown on the sidewalls of the word lines. In addition, a Si3N4 spacer 81 is formed, for example, by conformally depositing a silicon nitride layer on the whole surface, followed by an anisotropic etching step for removing the horizontal portions of the silicon nitride layer, leaving the vertical portions thereof, which form the spacer 81. In particular, the thickness of the spacer is approximately 0.6 F.
Thereafter, a photoresist material 31 is applied on the resulting surface and photolithographically patterned using a mask having a lines/spaces pattern. In particular, the photoresist material is patterned so as to cover every second opening between adjacent word lines and part of the adjacent word lines, while leaving every second opening 11a between neighboring word lines and a portion of the adjacent word lines uncovered. The resulting structure is shown in
As can be seen from
In particular, every second gap between some neighboring gate electrodes is covered with the photoresist material 31, and every second gap between other neighboring gate electrodes is uncovered. At the covered gap the bit line contact is to be formed, whereas at the uncovered gap 11a the capacitor contact is to be formed.
In the cross-sectional view between II and II, active areas 12 are provided, and isolation trenches 2 laterally delimit each of the active areas 12. The isolation trenches 2 are filled with an isolating material 32. A word line 8 is provided, the word line being isolated from the active area 12 by a gate-isolating layer 86. The word line is covered with a Si3N4 cap layer 80.
In addition,
A photoresist layer 31 is provided and patterned so as to form stripes that extend along the second direction. As can be taken from
Taking the stripes of the photoresist material 31 as an etching mask, an anisotropic etching step for etching silicon selectively with respect to SiO2 is performed. As a consequence, part of the silicon nitride cap layer 80 and of the silicon nitride spacers 81 is etched. In addition, the isolation groove 11 is etched in the silicon substrate 1 as is shown in
As can be seen, an isolation groove 11 is formed in the gap between two gate electrodes 85. In addition, part of the Si3N4 cap layer 80 and the Si3N4 spacer 81 which is directly adjacent to the isolation groove 11 is etched. Thereby, the opening 90a is formed in the Si3N4 cap layer 80. In part of the opening 90a the horizontal portion of the capacitor contact will be formed. As can be seen, the isolation groove 11 is formed in a self-aligned manner with respect to the gate electrodes 85.
Thereafter, an isotropic Si3N4 etching step, which is selective with respect to Si and SiO2, is performed. This etching step can be a dry or a wet etching step. In addition, optionally, an anti-punch implant for providing the implanted portion 88 can be performed. In particular, B, BF2 or In can be used as a dopant. The p-doped portion 88 will prevent a leakage current from flowing between neighboring first source/drain regions, which are to be formed adjacent to the isolation groove 11. The resulting structure is shown in
As can be seen, now the diameter of the opening 90b formed in the silicon nitride material 81 is enlarged with respect to the isolation groove 11. In addition, the diameter of the opening for 91 for forming the bit line contact is enlarged as well.
For providing the isolation groove and the capacitor contacts, first an anisotropic Si etching step is performed that is selective with respect to SiO2 and Si3N4. By this etching step, the SiOxNy layer 87 is etched as well, stopping on the Si3N4 layer 80. For example, if the SiOxNy 87 layer has an excess of silicon, it can be etched in aqueous ammonia, i.e. NH4OH/H2O. Thereafter, a short isotropic Si etching step, which is selective with respect to SiO2, Si3N4 and SiON is performed. Then, the photoresist material 31 is removed. The resulting structure is shown in
Thereafter, an isotropic etching step for etching SiON selectively with respect to Si, SiO2 and Si3N4 is performed. This etching step can be a dry or a wet etching step. Then, optionally, an implantation step for providing a p-doped portion 88, for example with B, BF2 or In can be performed. The resulting structure is shown in
In the next step, according to the first and second embodiments of the present invention, which have been described with reference to
The resulting structure is shown in
In the next step, an oxidation step (e.g., a thermal oxidation step) is performed. For example, a thermal oxidation step can be performed at a temperature higher than 800° C. in a chlorine containing or chloric ambient environment. As a consequence, a silicon dioxide layer 35 is formed on the polysilicon portions. In addition, GeO2 and GeOCl2, both of which are not stable, are formed on top of the Ge material. To be more specific, the GeO2 and GeOCl2 thus formed desorbs and is solved from the surface of the Ge layer, e.g., in a manner as described in the Journal of Electronic Materials, Vol. 33, No. 4, 2004, the disclosure of which is incorporated herein by reference in its entirety. In order to remove the stable phase GeO2 which might also be formed, a rinse in dilute HCl/H2O can be performed, as is also described in CRC Handbook of Chemistry and Physics, 67th edition, R C Weast, p. B92, the disclosure of which is incorporated herein by reference in its entirety. Thereafter, an etching step in H2O2 is performed so as to remove the remaining Ge material 34. Thereafter, an anisotropic Si etching step is performed so as to remove the remaining horizontal portion of the polysilicon layer 33a from the opening 90b. In addition, optionally, an additional implantation step can be performed so as to increase the doped portion 88.
The resulting structure is shown in
In the next step, a SiO2 layer is deposited so as to provide a SiO2 filling 32 in the region above the isolation groove 11. Moreover, a SiO2 layer 36 is provided on the surface of the structure shown in
In the next step, a metal layer 37 for forming the bit lines is deposited, followed by deposition of a Si3N4 layer 38. Thereafter, the MO layer stack is patterned using a mask having a lines/spaces pattern so as to form lines that are parallel to the active areas and perpendicular with respect to the word lines. An etching step is performed, followed by steps for forming a Si3N4 spacer. In particular, a silicon nitride layer is conformally deposited and, thereafter, it is anisotropically etched so as to remove the horizontal portions thereof, thereby forming a Si3N4 spacer 39. The resulting structure is shown in
As can be seen from
In the next step, a further silicon dioxide filling 51 is provided, and a CMP (chemical mechanical polishing) step is performed so as to obtain a planarized surface. This SiO2 filling 51 fills the gap between adjacent bit lines 37. Since the bit lines 37 are not located above the active areas so as to cover them entirely, as can also be taken from the cross-sectional view between VI and VI in
In particular,
The bit lines 60, 60′ are arranged perpendicular with respect to the word lines 8, 8′, and the bit lines 60 are parallel to each other. Each of the bit lines 60 is connected with a plurality of second source/drain regions of the memory cells 100 via a bit line contact 61.
The memory cell arrays 70, 70′ are each coupled to respective groups of bit lines 60, 60′ and respective groups of word lines 8, 8′. The two groups of bit lines 60, 60′ are coupled, one from each of the memory arrays 70, 70′, to sense amplifiers 71. The sense amplifiers 71 include peripheral circuitry, i.e., circuitry employed in support of the memory cell arrays 70, 70′ and generally are formed outside of peripheries of the memory arrays 70, 70′.
In operation, one memory cell 100 is selected, for example, by activating one word line 8. The word line 8 is coupled to a respective gate electrode of a respective one of the transistors 16. The bit line 60 is coupled to the first source/drain region of one of these transistors 16 via the bit line contact 61. The transistor 16 is then turned on, coupling charge stored in the capacitor 4 to the associated bit line 60. The sense amplifier 71 then senses the charge coupled from the capacitor 4 to the bit line 60. The sense amplifier 71 compares that signal to a reference signal such as the reference charge Qref or a reference signal that is obtained by sensing a corresponding bit line 60′, without a voltage being applied to the corresponding word line 8′, amplifies the resulting signal and latches the amplified signal from appropriate duration. This allows data represented by the charge stored in the capacitor 4 to be accessed external to the memory arrays 100, 100′ and also allows the capacitor 4 to store charge representative of the data from the memory cell 100 back into the memory cell 100. One skilled in the art will clearly recognize that alternative array architectures, such as a vertically twisted bit line array architecture, can also be used in the present invention.
While the invention has been described in detail and with reference to specific embodiments thereof, it will be apparent to one skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope thereof. Accordingly, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
