Patent Application
20050276093
This application is a continuation of International Patent Application Serial No. PCT/DE2003/003589, filed Oct. 29, 2003, which published in German on May 13, 2004 as WO 2004/040644, and is incorporated herein by reference in its entirety.
The invention relates to a memory cell, a memory cell arrangement, a patterning arrangement and a method for fabricating a memory cell.
On account of rapid development in computer technology, ever greater quantities of data need to be stored. For silicon microtechnology, this means the need for ongoing miniaturization increases the integration density of a semiconductor memory in a semiconductor substrate.
One important concept in the development of semiconductor memories is the concept of the DRAM (dynamic random access memory) memory cell. A DRAM is a dynamic semiconductor memory which, as memory cell, has one capacitor per bit in its memory matrix. The binary storage of information is effected by charging this capacitor. A memory cell is addressed via a switching transistor which couples the capacitor to a bit line. To read or program the memory cell, the word line is brought to a sufficiently high electrical potential, so that the switching transistor becomes conductive and the memory cell is coupled to the bit line. During programming, the capacitor is charged or discharged depending on the memory information items to be stored (logic 0 or 1). When reading the information, the stored charge on the bit line generates a voltage change which can be detected and is a characteristic measure of the information item stored in the memory cell.
On account of the low capacitance of the storage transistor of a memory cell and on account of inevitable losses of current, it is necessary to periodically refresh the charge contents of the capacitor.
A DRAM memory cell is usually designed as an integrated semiconductor circuit. When developing a DRAM memory arrangement with increasingly small dimensions, i.e. with ever greater storage densities, the problem arises that the size of each component of a DRAM memory cell in each dimension is at least the value F, F being the minimum feature size which can be achieved in a particular technology generation. Moreover, the storage capacitor is difficult to scale. This restricts the extent to which DRAM memory cells can be miniaturized.
A further important concept in semiconductor memories is what is known as the FRAM (ferroelectric random access memory) concept.
According to one implementation, an FRAM memory cell is an MOS field-effect transistor in which a ferroelectric layer is provided instead of the gate-insulating layer. A preferential direction for the permanent ferroelectric dipole moments in the ferroelectric layer is defined, i.e. the FRAM memory cell is programmed, by means of a suitably selected gate voltage. The electrical conductivity of the channel region adjoining the ferroelectric layer is influenced in a characteristic way as a function of what preferential direction for the ferroelectric dipoles has been set in the ferroelectric layer as a result of previous programming by application of a suitable gate voltage. In other words, the intensity of the electric current between the two source/drain regions between which the channel region is arranged depends on the state of the ferroelectric dipoles of the ferroelectric layer as a result of a preceding programming event.
According to an alternative concept for an FRAM memory cell, the same structure as in the DRAM memory cell described above is used, with the exception that a ferroelectric (e.g. lead zirconate titanate, Pb(Zr1-xTix)O3, PZT) is used instead of a dielectric between the capacitor electrodes. It can be concluded from the hystersis curve of a ferroelectric that the ferroelectric has a positive or negative permanent polarization depending on whether a positive or negative field strength (or voltage) is applied during programming. The memory cell is read by the application of a positive voltage to the bit line. If the ferroelectric has a negative polarization, the polarization is reversed, so that a charge packet flows to the bit line. If the permanent polarization is positive, the polarization changes only slightly, and consequently scarcely any charge flows to the bit line.
The problem described above in connection with the DRAM memory cell whereby the minimum feature size which can be achieved is limited by the minimum one-dimensional feature resolution F which can be achieved within a particular semiconductor technology generation also arises when forming an FRAM memory cell.
Furthermore, with increasing miniaturization of a conventional semiconductor memory cell based on a MOSFET, the problem arises whereby in particular the length of the conducting channel decreases as a result, leading to disruptive short-channel effects. Therefore, conventional concepts for an integrated memory cell are increasingly encountering fundamental physical problems.
Nanotubes, in particular carbon nanotubes, are considered one possible successor to conventional semiconductor electronics. By way of example, Harris, P. J. F. (1999) “Carbon Nanotubes and Related Structures—New Materials for the Twenty-first Century.”, Cambridge University Press, Cambridge, pp. 1 to 15, 111 to 155, provides an overview of this technology.
A carbon nanotube is a single-walled or multiwalled tube-like carbon compound. In the case of a multiwalled nanotube, at least one inner nanotube is coaxially surrounded by an outer nanotube. Single-walled nanotubes typically have diameters of approximately 1 nm, whereas the length of a nanotube may be several hundred nm. The ends of a nanotube are often closed off by means of in each case half a fullerene molecule. Nanotubes often have a good electrical conductivity, which makes nanotubes suitable for constructing circuits with dimensions in the nanometer range. On account of the electrical conductivity of nanotubes and on account of the possibility of adjusting this conductivity (for example by applying an external electric field or by doping the nanotube with boron nitride), nanotubes are suitable for a wide range of applications, for example for electrical coupling in integrated circuits, for components used in microelectronics and as electron emitters.
In addition to carbon nanotubes, nanotubes made from other materials, for example tungsten sulfide and other chalcogenides, are also known.
As well as nanotubes, nanostructures in the form of nanorods are also known. Nanorods likewise have a diameter in the nanometer range and may be several micrometers long. Typical materials for nanorods are the semiconductors silicon, germanium, indium phosphide and gallium arsenide.
Both nanotubes and nanorods can be deposited from the vapor phase by means of catalytic processes. An overview of the technology of nanostructures is given, for example, by Roth, S. (2001) “Leuchtdioden aus Nanostäcbchen”, [Light-emitting diodes formed by nanorods], Physikalische Blätter 57(3):17-18.
It is known from Suh, J. S., Lee, J. S. (1999) “Highly ordered two-dimensional carbon nanotube arrays” Applied Physical Letters 75(14): 2047-2049, and Lee, J. S., Gu, G. H., Kim, H., Jeong, K. S., Bae, J., Suh, J. S. (2001) “Growth of Carbon Nanotubes on Anodic Aluminum Oxide Templates: Fabrication of a Tube-in-Tube and Linearly Joint Tube” Chem. Mater. 13(7): 2387-2388, that highly ordered, two-dimensional patterns of carbon nanotubes can be grown in an aluminum oxide template. A substrate made from aluminum oxide with a two-dimensional arrangement of hexagonal pores is used for this purpose, which pores serve as a template for the growth of carbon nanotubes. In accordance with the process described in Suh et al. and Lee et al., cobalt is deposited in the pores as a catalyst for the growth of nanotubes on the base layer. Subsequently, carbon nanotubes are grown in the pores by the introduction of acetylene, with both aluminum and cobalt catalytically assisting the growth.
It is known from DE 100 36 897 C1 to introduce a through-hole into a thick gate electrode layer and to grow a vertical nanoelement in this hole. This produces a vertical field-effect transistor with the nanoelement as channel region, it being possible to control the electrical conductivity of the channel region by means of the gate electrode region that surrounds the nanoelement approximately along its entire longitudinal extent.
DE 198 05 076 A1 discloses a method for fabricating a semiconductor component, in which a copolymer triple block is formed with a first copolymer as inner column, a second copolymer as outer column and a third copolymer surrounding the second copolymer.
DE 100 36 897 C1 discloses a field-effect transistor, a circuit arrangement and a method for fabricating a field-effect transistor, in which a vertical nanoelement forms a channel of the field-effect transistor.
The invention is based on the problem of providing a memory cell having a storage capacitor, which memory cell can be fabricated in miniaturized form, and in which memory cell short-channel effects are avoided in a field-effect transistor contained in the memory cell.
The problem is solved by a memory cell, a memory cell arrangement, a patterning arrangement and a method for fabricating a memory cell.
The invention provides a memory cell having a vertical switching transistor and a storage capacitor; the vertical switching transistor having a semiconducting nanostructure which has grown on at least part of the storage capacitor.
Furthermore, the invention provides a memory cell arrangement having a plurality of memory cells having the features described above.
Furthermore, the invention provides a method for fabricating a memory cell, in which a vertical switching transistor and a storage capacitor are formed; a semiconducting nanostructure of the vertical switching transistor which has grown on at least part of the storage capacitor being formed.
Exemplary embodiments are illustrated in the figures and explained in more detail below.
In the drawings:
The invention provides a memory cell having a vertical switching transistor and a storage capacitor; the vertical switching transistor having a semiconducting nanostructure which has grown on at least part of the storage capacitor.
Furthermore, the invention provides a memory cell arrangement having a plurality of memory cells having the features described above.
Furthermore, the invention provides a method for fabricating a memory cell, in which a vertical switching transistor and a storage capacitor are formed; a semiconducting nanostructure of the vertical switching transistor which has grown on at least part of the storage capacitor being formed.
The invention also provides a patterning arrangement having a nanostructure which extends substantially orthogonally with respect to the surface of a substrate and is arranged at least partially outside the substrate; having material that is to be patterned on the part of the nanostructure which is arranged outside the substrate; having an etchant feed device, which is designed in such a manner that it can be used to direct etchant for etching material that is to be patterned onto the nanostructure covered with material that is to be patterned at a predetermined angle with respect to the nanostructure, in such a manner that only those subregions of the material to be patterned which are in the shadow of the nanostructure with respect to the etchant are protected from being removed as a result of the etching.
The memory cell according to the invention can clearly be used as a DRAM memory cell or as an FRAM memory cell. The vertical switching transistor can be used to select a memory cell of the invention in a memory cell arrangement, so that the information stored in the storage capacitor can be read or programmed. The vertical switching transistor has a semiconducting nanostructure, for example a carbon nanotube, a carbon-nitrogen nanotube or a carbon-boron-nitrogen nanotube. The memory cell according to the invention can be fabricated in miniaturized form by using a nanostructure in the vertical switching transistor. By way of example, a vertical carbon nanotube which can be used as nanostructure has a dimension in cross section of one or a few nanometers, so that in principle it is possible in accordance with the invention to form a memory cell which only takes up this order of magnitude of space. Since the switching transistor having the semiconducting nanostructure is formed as a vertical transistor, it is simultaneously possible to effect miniaturization while avoiding short-channel effects. In its configuration as a carbon nanotube, the nanostructure may have an extent of hundreds of nanometers or even 1 μm in the vertical direction, and therefore the channel region as part of the nanostructure can be made sufficiently long to avoid disruptive short-channel effects.
It is preferable for the vertical switching transistor and the storage capacitor to be formed at least partially in and/or at least partially on a substrate.
The substrate is preferably a semiconductor substrate and in particular a silicon substrate.
The nanostructure may extend substantially orthogonally with respect to the surface of the substrate. It is preferable for a first end portion of the nanostructure to be arranged within the substrate and for a second end portion of the nanostructure to be arranged outside the substrate.
As a result of a subregion of the nanostructure being formed vertically outside the substrate, it is possible for this part of the nanostructure to serve as a “template” for the formation and in particular the selective removal of material on the nanostructure and/or on the substrate. Clearly, by way of example, an etchant can be directed onto the nanostructure and the substrate at a predetermined angle, with that region on the nanotube or on the substrate which is in the shadow of the nanotube with respect to the etchant being protected from etching. With this idea according to the invention, it is possible to form a wide range of structures in semiconductor technology.
It is preferable for the vertical switching transistor to be a field-effect transistor. In this case, the first portion of the nanostructure may form a first source/drain region, the second end portion of the nanostructure may form a second source/drain region and an intermediate region of the nanostructure, arranged between the two end portions, may form a channel region of the vertical switching transistor.
Furthermore, a dielectric layer may be formed between the first end portion of the nanostructure and the substrate, the first end portion of the nanostructure forming a first electrically conductive capacitor element, the dielectric layer forming a capacitor dielectric and the substrate forming a second electrically conductive capacitor element of the storage capacitor.
According to this design, the nanostructure performs the function both of a component of the vertical switching transistor and of a first conductive capacitor element of the storage capacitor. The first electrically conductive capacitor element of the storage capacitor configured as an integrated component is the analog of a capacitor plate of a conventional capacitor. By virtue of the nanostructure performing a dual function, as a component of the vertical switching transistor and of the capacitor element, electrical contact-connection is simplified and there is no need for a separate element, and consequently the memory cell according to the invention can be fabricated with a low level of outlay.
A layer of a ferroelectric material may be provided instead of the dielectric layer. According to this configuration, the memory cell according to the invention can be used as an FRAM memory cell having the functionality described above.
Catalyst material for catalyzing the formation of the nanostructure may be arranged between at least a part of the dielectric layer and the nanostructure.
It is possible to predetermine the spatial growth of the nanostructures by means of the catalyst material. Therefore, the provision of an ordered arrangement of regions of catalyst material, which are not necessarily cohesive, makes it possible to allow ordered growth of the nanostructure. It should be noted that in particular if the nanostructure is designed as a carbon nanotube, iron, cobalt or nickel is a good choice of catalyst material.
Furthermore, at least part of the intermediate region of the nanostructure may be surrounded by an electrically insulating ring structure which forms the gate insulation layer of the vertical transistor, and at least part of the electrically insulating ring structure may be surrounded by a first electrically conductive region which forms the gate electrode of the vertical switching transistor and the word line.
Since the semiconducting nanostructure is surrounded by an electrically insulating ring structure in the vicinity of its intermediate region, a gate insulating layer which is surrounded by the first electrically conductive region functioning as gate electrode is provided. The conductivity of the nanostructure can be influenced in a characteristic way in the intermediate region of the nanostructure, functioning as channel region, as a result of the application of a suitable voltage to the electrically conductive region, so that the nanostructure together with the electrically insulating ring structure and the first electrically conductive region performs the functionality of a field-effect transistor. On account of an electrostatic peak effect, the amplitude of an electric field generated by the application of an electric voltage to the gate electrode can be made particularly high in the vicinity of the nanostructure by the use of an annular gate electrode, so that particularly accurate control of the electrical conductivity of the channel region is possible.
It should be noted that the vertically grown nanostructure can also function as a shadow mask for the formation of the first electrically conductive region. Therefore, the components mentioned are formed by means of a self-aligning process, allowing these components to be formed with a low level of outlay.
It is preferable for the second end portion of the nanotube to be surrounded by a second electrically conductive region which forms the bit line. The nanostructure also functions as a shadow mask during the formation of the bit line, as described in more detail below.
The semiconducting nanostructure may include a semiconducting nanotube, a bundle of semiconducting nanotubes or a semiconducting nanorod. A semiconducting nanostructure formed as a nanorod may include silicon, germanium, indium phosphide and/or gallium arsenide. If the nanostructure is formed as a semiconducting nanotube, this may be a semiconducting carbon nanotube, a semiconducting carbon-boron nanotube or a semiconducting carbon-nitrogen nanotube.
The memory cell may be formed exclusively from dielectric material, metallic material and the material of the nanostructure. The substrate may consist of polycrystalline or amorphous material.
In other words, the memory cell according to the invention may consist only of electrically conductive material, dielectric material and material of the nanostructure (preferably a carbon nanotube) . In this case, the memory cell can be fabricated without the need for expensive semiconductor technology processes. A further important advantage in this context is that a polycrystalline or amorphous material, i.e. a material which is not in single-crystal form, can be used as substrate for fabrication of the memory cell. This avoids the need for an expensive single-crystal substrate (for example a silicon wafer) in the fabrication of the memory cell. According to the invention, in principle any desired starting substrate can be used.
The memory cell arrangement according to the invention, which has a plurality of memory cells according to the invention, preferably in an arrangement substantially in matrix form, is a memory cell arrangement with a particularly high integration density. Configurations of the memory cell also apply to the memory cell arrangement.
The text which follows describes the method according to the invention for producing a memory cell. Configurations of the memory cell also apply to the method for fabricating the memory cell.
According to one refinement of the method according to the invention for fabricating a memory cell, the vertical switching transistor and the storage capacitor are formed at least partially in and/or on a substrate.
The nanostructure may be formed substantially orthogonally with respect to the surface of the substrate.
A first end portion of the nanostructure may be formed within the substrate, and a second end portion of the nanostructure may be formed outside the substrate.
The first end portion of the nanostructure may preferably be formed as a first source/drain region, the second end portion of the nanostructure may preferably be formed as a second source/drain region, and an intermediate region of the nanostructure arranged between the two end portions may preferably be formed as a channel region of the vertical switching transistor, which is designed as a field-effect transistor.
A dielectric layer may be formed between the first end portion of the nanostructure and the substrate, the first end portion of the nanostructure being formed as a first electrically conductive capacitor element, the dielectric layer being formed as a capacitor dielectric and the substrate being formed as a second electrically conductive capacitor element of the storage capacitor.
In the method, catalyst material for catalyzing the formation of the nanostructure may be formed at least between part of the dielectric layer and the nanostructure.
Furthermore, at least part of the intermediate region of the nanostructure may be surrounded by an electrically insulating ring structure which forms the gate insulation layer of the vertical transistor, and at least part of the electrically insulating ring structure may be surrounded by a first electrically conductive region which forms the gate electrode of the vertical switching transistor and the word line.
The second end portion of the nanotube may be surrounded by a second electrically conductive region, which forms the bit line.
In particular, the word line and/or the bit line and/or the gate electrode may be formed by a part of the nanostructure which is uncovered or covered with a layer being covered with electrically conductive material and an etchant for etching the electrically conductive material being directed onto the nanostructure covered with the electrically conductive material at a predetermined angle with respect to the nanostructure, in such a manner that only those subregions of the electrically conductive material which are in the shadow of the nanostructure with respect to the etchant are protected from being removed as a result of the etching.
The method according to the invention described in particular has the advantage that the number of lithography steps required to form the memory cell is reduced compared to the prior art. This is based, inter alia, on the fact that the vertically oriented nanostructure can be used as a shadow mask during directional etching of various layers, in particular when forming word and bit lines or when forming the electrically insulating ring structure as a gate insulating layer.
It is possible in the manner described to obtain a DRAM memory cell which takes up an area of just 4F2 on a substrate, F being the minimum feature size which can be achieved for a particular technology generation. This increases the integration density compared to the prior art. Furthermore, on account of the vertical arrangement of the memory cell according to the invention, it is possible for a plurality of layers of memory cells to be arranged stacked on top of one another, in order thereby to achieve three-dimensional integration of memory cells, which further increases the integration density. It should be noted in particular that the concept of the invention can also be used to form an FRAM memory cell. For this purpose, the dielectric layer of the capacitor dielectric is to be formed from a ferroelectric material.
The DRAM/FRAM concept of the invention has the advantages of allowing self-aligning, stacked formation of the vertical switching transistor on the storage capacitor, that the memory cell can be formed on a substrate which is not necessarily crystalline silicon, that the memory cell arrangement of the invention can be stacked in three dimensions, that the area taken up by a memory cell on the surface of a substrate is reduced to 4F2, that it is possible to produce the memory cell according to the invention by means of a single lithographic method step (cf. description below), that it is possible to realize a transistor architecture with an annular gate insulating region, with all the gate electrodes automatically being coupled so as to form a self-aligning word line.
One basic concept of the invention is that the growth of the nanostructure can be realized in an etched trench, which serves as a template for the growth, using the CVD (chemical vapor deposition) process, it being possible to define a seed position for the growth of nanotubes in three dimensions by means of the targeted application of catalyst material. A further aspect of the invention is that of using a nanostructure as an electrically conductive element of an integrated capacitor. Another aspect is based on the use of a vertical transistor having a nanostructure. A further aspect is the growth of a nanostructure with a high aspect ratio and the use of this nanostructure as a shadow mask (i.e. evidently as an auxiliary structure) for forming the annular transistor gate (gate insulating layer and gate electrode) and for forming word and bit lines. A further aspect of the invention is that a vertically oriented nanostructure can be used for the self-aligned, stacked formation of integrated components, for example of a storage capacitor and a vertical switching transistor in a DRAM or FRAM memory cell.
The following text, referring to
To obtain the layer sequence 100 shown in
To obtain the layer sequence 106 shown in
To obtain the layer sequence 108 shown in
To obtain the layer sequence 110 shown in
To obtain the layer sequence 113 shown in
To obtain the layer sequence 116 shown in
To obtain the layer sequence 119 shown in
To obtain the layer sequence 122 shown in
To obtain the layer sequence 126 shown in
To obtain the layer sequence 130 shown in
To obtain the layer sequence 133 shown in
To obtain the layer sequence 135 shown in
To obtain the layer sequence 137 shown in
The further method steps involved in forming the memory cell according to the invention are described with reference to
In a similar way to in the method step involved in the transition from
To obtain the memory cell 145 shown in
The text which follows describes the functionality of the memory cell 145 shown in
The memory cell 145 has a vertical switching transistor and a storage capacitor, the vertical switching transistor including the semiconducting carbon nanotube 120 which has been grown on part of the storage capacitor. The vertical switching transistor and the storage capacitor are arranged partially in and partially on the doped silicon substrate 101. The first end portion 120a of the carbon nanotube 120 is arranged within the doped silicon substrate 101, and the second end portion 120b of the carbon nanotube 120 is arranged outside the substrate 101. The vertical switching transistor is designed as a field-effect transistor, with the first source/drain region of the vertical transistor, designed as a field-effect transistor, being the first end portion 120a of the carbon nanotube 120, the second end portion 120b of the carbon nanotube forming the second source/drain region of the vertical switching transistor, and the intermediate region 120c, arranged between the two end portions 120a, 120b, of the carbon nanotube 120 forming the channel region of the vertical switching transistor. The intermediate region 120c of the carbon nanotube 120 is surrounded by an electrically insulating ring structure, formed by the first silicon dioxide layer 123, which forms the gate insulating layer of the vertical switching transistor. That region of the first silicon dioxide layer 123 which forms the electrically insulating ring structure is surrounded by the first titanium nitride layer 124, which forms the gate electrode of the vertical switching transistor and the word line. The second end portion 120b of the carbon nanotube 120 is partially surrounded by the electrically conductive second titanium nitride layer 139, which forms the bit line of the memory cell. The storage capacitor of the memory cell 145 is formed by two electrically conductive capacitor elements (which in the integrated stacked capacitor form the analog of the capacitor plates of a conventional capacitor) and by a dielectric layer as capacitor dielectric between the two electrically conductive capacitor elements. The first end portion 120a of the carbon nanotube 120 forms the first electrically conductive capacitor element, the doped silicon substrate 101 forms the second electrically conductive capacitor element, and the subregion of the dielectric layer 114 which separates the first end portion 120a of the carbon nanotube 120 from the doped silicon substrate 101 forms the capacitor dielectric.
The conductivity of the carbon nanotube 120, in particular in the intermediate region 120c, is influenced in a characteristic way, on account of the field effect, by the application of a suitable voltage to the first titanium nitride layer 124, which functions as a word line, and consequently by applying a suitable voltage to the first titanium nitride layer 124 it is possible to select the memory cell 145 shown in
The presence of electric charge in the storage capacitor can be interpreted as a state with a logic 1, whereas a state in which there is no electric charge stored in the storage capacitor can be interpreted as a logic 0. If the information stored in the memory cell 145 is to be read, the vertical switching transistor is brought into a conducting state by the application of a suitable voltage to the word line 124, so that any charge carriers which may be stored in the storage capacitor flow onto the bit line 139, where a corresponding electrical signal can be detected. This signal is characteristic of the information stored in the storage capacitor.
The following text, referring to
Starting from the layer sequence 106 shown in
The following text describes a preferred exemplary embodiment of the patterning arrangement according to the invention with reference to
The patterning arrangement 210 has first and second carbon nanotubes 212, 213, which extend substantially orthogonally with respect to the surface of a substrate 211 and are arranged partly outside the substrate 211. Furthermore, the patterning arrangement includes material 214 that is to be patterned on that part of the carbon nanotubes 212, 213 which is arranged outside the substrate 211. Furthermore, the patterning arrangement 210 may include further layers 215, 216, 217, by which the first and second carbon nanotubes 212, 213 may be partially surrounded. Furthermore, the patterning arrangement 210 has an etchant feed device 218, which is designed in such a manner that it can be used to direct etchant for etching material 214 that is to be patterned onto the carbon nanotubes 212, 213 covered with material 214 that is to be patterned at a predeterminable angle α with respect to the carbon nanotube 212 or 213, in such a manner that only those subregions of the material 214 to be patterned which are in the shadow of the carbon nanotubes 212, 213 with respect to the etchant are protected from removal as a result of etching.
The carbon nanotubes 212, 213 evidently serve as a mask, which mask determines which regions of the material 214 to be patterned are removed. On account of the geometric conditions shown in
The following text, referring to
The following text refers to
To obtain the layer sequence 300 shown in
To obtain the layer sequence 310 shown in
To obtain the layer sequence 320 shown in
To obtain the layer sequence 330 shown in
To obtain the layer sequence 340 shown in
To obtain the layer sequence 350 shown in
The following text refers to
The memory cell 400 has a polycrystalline silicon substrate 401, on which a first silicon dioxide layer 402 has been formed. A thin first titanium nitride layer 403 has been applied to the first silicon dioxide layer 402. A second silicon dioxide layer 404 has been applied to the first titanium nitride layer 403. The layers 402 to 404 and a surface region of the silicon substrate 401 are subjected to a suitable etching process, so that a through-hole is etched through the layers 404 to 402, which through-hole extends all the way into a surface region of the silicon substrate 401. An electrically insulating third silicon dioxide layer 405 has been formed along the inner wall of the hole. A carbon nanotube 406 has been grown in the hole. A second titanium nitride layer 407 has been applied to the layer sequence obtained in this way.
In the memory cell 400, a region of the silicon substrate 401, as first electrically conductive capacitor element, a region of the third silicon dioxide layer 405, as capacitor dielectric, and a region of the carbon nanotube 406, as second electrically conductive capacitor element, form a storage capacitor.
Furthermore, a switching field-effect transistor is formed from a central region of the carbon nanotube 406 as channel region, a lower portion, as seen in
| Number | Date | Country | Kind |
|---|---|---|---|
| 102 50 834.8 | Oct 2002 | DE | national |
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/DE03/03589 | Oct 2003 | US |
| Child | 11119531 | Apr 2005 | US |
