Claims
- 1. A non-volatile semiconductor memory device formed on a semiconductor substrate of a first conductivity type, said semiconductor memory device comprising:
- a plurality of recessed portions formed on a surface of said semiconductor substrate, said recessed portions having sidewalls and a bottom at which said semiconductor substrate is exposed;
- a gate oxide film directly formed on a surface of said semiconductor substrate other than said recessed portions;
- a floating gate electrode formed on said gate oxide film;
- a source region and a drain region of a second conductivity type each formed in said semiconductor substrate at said bottom of one of said recessed portions and on opposing sides of said floating gate electrode;
- an intergate insulation film formed on said semiconductor substrate to cover a top surface and sidewalls of said floating gate electrode, said sidewalls of said recessed portions, and said source region and said drain region;
- a control gate electrode formed on said intergate insulation film, wherein said intergate insulation film is in direct contact with said sidewalls of said recessed portions so that said sidewalls of said semiconductor substrate adjacent to said intergate insulation film each forms a channel region of a field effect transistor.
- 2. The non-volatile semiconductor memory device according to claim 1 wherein said intergate insulation film is in direct contact with one of said sidewalls of said recessed portions at a first side of said floating gate electrode and having one of said source region and drain region interposed between said intergate insulation film and said sidewall at a second side of said floating gate electrode opposing said first side, thereby selectively forming a channel region of a field effect transistor adjacent to said first side of said floating gate electrode.
- 3. The nonvolatile semiconductor memory device according to claim 1 wherein a memory cell is formed from a data memory section having two-layer gate construction that includes a floating gate and a control gate and two series select transistors formed at said exposed side wall portions of said semiconductor substrate, by ion injection of impurities forming a diffused impurity layer perpendicularly into said semiconductor substrate.
- 4. The nonvolatile semiconductor memory device according to claim 1 wherein a memory cell is formed from a data memory section having two-layer gate construction that includes a floating gate and a control gate and a series select transistor formed at said exposed side wall portions of said semiconductor substrate, by ion injection of impurities forming a diffused impurity layer into said semiconductor substrate at an oblique angle, to form said diffused layer in the surface of said side wall at only one side of said floating gate.
Priority Claims (1)
Number |
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6-277455 |
Nov 1994 |
JPX |
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Parent Case Info
This is a continuation of application Ser. No. 08/887,408, filed Jul. 2, 1997 and Ser. No. 08/556,078, which was filed on Nov. 13, 1995 and now abandoned.
US Referenced Citations (6)
Foreign Referenced Citations (1)
Number |
Date |
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4233278 |
Aug 1992 |
JPX |
Related Publications (1)
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556078 |
Nov 1995 |
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Continuations (1)
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Parent |
887408 |
Jul 1997 |
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