Patent Application
20060261418
This disclosure relates to nitride read only memory (NROM) and other ONO (oxide nitride oxide) or other microelectronic cells or structures and, more particularly, to cells or structures having buried bitlines (BBs) or other embedded structures.
The present disclosure relates to nitride read only memory (NROM) or other ONO (oxide nitride oxide) cells or other microelectronic structures with buried lines generally and to a method of fabrication thereof and resulting structure(s) in particular.
Dual bit memory cells are known in the art. One such memory cell is the NROM (nitride read only memory) cell 10, shown in
NROM cells are described in many patents, for example in U.S. Pat. No. 6,649,972. As shown in
A common problem is the integrity of bit line oxides 26. As can be seen in
The following patents and patent applications note their attempt to solve these issues and to improve scaling. US 2004/0157393 to Hwang describes a manufacturing process for a non-volatile memory cell of the SONOS type (a type of ONO) which attempts to reduce or minimize the undesirable effects of small dimension components. U.S. Pat. No. 6,686,242 B2 to Willer et al. allegedly describes an NROM cell which arguably can be implemented within a 4F2 area.
The above scaling by minimizing the BL side diffusion has two problems associated with it. The first is the high BL resistance and the second is the close relations between the NROM cell performance and the BL dose, energy and side diffusion. Any attempt to improve the BL resistance may end with a lengthy development cycle to re-optimize the cell. This disclosure addresses the above problems. A more complete description of NROM and similar ONO cells and devices, as well as processes for their development may be found at “Non Volatile Memory Technology”, 2005 published by Saifun Semiconductor and materials presented at and through http://siliconnexus.com, both incorporated by reference herein in their entirety.
Glossary
Unless otherwise noted, or as may be evident from the context of their usage, any terms, abbreviations, acronyms or scientific symbols and notations used herein are to be given their ordinary meaning in the technical discipline to which the disclosure most nearly pertains. The following terms, abbreviations and acronyms may be used throughout the descriptions presented herein and should generally be given the following meaning unless contradicted or elaborated upon by other descriptions set forth herein. Some of the terms set forth below may be registered trademarks (®).
In addition to the above, some abbreviations that may be used herein, or in the provisional application from which this non-provisional application claims priority, include:
Further and additional descriptions and explanations of terms, structures, systems and methods may be found in the publication NROM Technology, 2005 published by Saifun Semiconductors and at the website www.siliconnexus.com, both being incorporated herein in their entirety by reference.
It is a general object of the disclosure to provide improved techniques for manufacturing memory cells.
According to this disclosure, a method of making a memory cell comprises: forming a buried bitline (BB) in a substrate in at least two separate implantation steps. The method may further comprise performing a pocket implant step. The pocket implant step may be performed before the buried bitline implantation steps. The pocket implant step may be performed through a layer of polysilicon.
According to this disclosure, an NROM memory cell comprises: a semiconductor substrate; an ONO layer disposed on the substrate; a polysilicon layer disposed over the ONO layer; a pocket implant disposed in the substrate at a location under an opening in the polysilicon layer; a first buried bitline (BB) implant disposed in the substrate at the location; and a second buried bitline (BB) implant disposed in the substrate at the location.
According to a feature of this disclosure, the pocket implant has a first width (W1) and a first depth (D1); the first BB implant has a second width (W2) and a second depth (D2); the third BB implant has a third width (W3) and a third depth (D3); the second width (W2) is less than the first width (W1), and the third width (W3) is less than or equal to the second width (W2); and the second depth (D2) is greater than the first depth (D1), and the third depth (D3) is greater than the second depth (D2).
According to a feature of this disclosure, the pocket implant may comprise boron; the first RB implant may comprise arsenic; and the second BB implant may comprise arsenic.
According to a feature of this disclosure, the first BB implant provides for pocket implant (PI) to bitline (BL) edge optimization; and the second BB implant provides for controlling and optimizing the BL resistance.
A buried bitline (BB) formed having one or more dopant concentration area(s) having a feature size less than the minimum feature size provided for (such as contemplated or permitted) under the process design rules for fabricating microelectronic devices, such dopant concentration having areas of higher (or lower) concentration in an otherwise doped region.
Reference will be made in detail to embodiments of the disclosure, examples of which may be illustrated in the accompanying drawing figures. The figures are intended to be illustrative, not limiting. Although the disclosure is generally described in the context of these embodiments, it should be understood that it is not intended to limit the disclosure to these particular embodiments.
Certain elements in selected ones of the figures may be illustrated not-to-scale, for illustrative clarity. The cross-sectional views, if any, presented herein may be in the form of “slices”, or “near-sighted” cross-sectional views, omitting certain background lines which would otherwise be visible in a true cross-sectional view, for illustrative clarity. A group of related figures, such as
In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the disclosure. However, it will be understood by those skilled in the art that the teachings of the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the teachings of the present disclosure.
Materials (such as silicon dioxide) may be referred to by their formal and/or common names, as well as by their chemical formula. Regarding chemical formulas, numbers may be presented in normal font rather than as subscripts. For example, silicon dioxide may be referred simply as “oxide”, chemical formula SiO2.
In the description that follows, exemplary dimensions may be presented for an illustrative embodiment of the teachings of the disclosure. The dimensions should not be interpreted as limiting. They are included to provide a sense of proportion. Generally speaking, it is the relationship between various elements, where they are located, their contrasting compositions, and sometimes their relative sizes that is of significance.
In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the disclosure. However, it will be understood by those skilled in the art that the teachings of the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the teachings of the present disclosure.
Advanced NROM Structure and Method of Fabrication
Reference is now made to
After preparation of a substrate 30 (
A mask may be laid down and ONO layer 32 may be removed (step 102) from the area of the chip designated for CMOS operation, after which the gate oxides of the periphery may be grown and a threshold voltage doping may be implanted for the CMOS periphery. It will be appreciated that the operations of step 102 may be high thermal budget operations. Moreover, as will be seen hereinbelow, they are effectively the last high thermal budget operations in the present process.
In step 104, a first polysilicon layer 31 may be laid down over the entire chip. A nitride hard mask 36 may then be deposited (step 106) in a column pattern covering the areas of the memory array not destined to be bit lines.
An etch may be performed (step 108) to generate bit line openings 37 by removing the areas of polysilicon layer between columns of nitride hard mask layer 36. The etch may be performed in multiple ways.
In one embodiment, it is a polysilicon etch, set to over-etch, for example by 20-50%. The over-etching may then etch away the oxide and nitride layers. For example, if the polysilicon is 70 nm thick and the over-etch is 20%, with a 4/1 poly to oxide etch rate difference, then the over-etch is approximately 3-4 nm, which will reduce a top oxide layer (of 10 nm) to less than 6 nm. If the over-etch is 50%, then it may consume the entire top oxide layer and even consume part of the nitride layer. The over-etch may be set to remove all but the bottom oxide layer.
In another embodiment, the etch may be performed in two steps, a first polysilicon etch to remove all but the bottom oxide layer and a second oxide etch to remove the bottom oxide. The latter may be a very short etch, to remove, for example 2-5 nm of the bottom oxide. Although the etch may also etch silicon substrate 30, it typically may etch only a slight amount (about 0.2-0.5 nm) and thus, may have a minimal affect on the silicon quality. This embodiment may provide a more uniform oxide thickness across the wafer. The latter may improve control of future trajectories of implants into the silicon (steps 110 and 114) and hence, better control of the overlap of the threshold and pocket implants to the bit line implant.
Optionally, the array may now be oxidized (step 109), to create a sidewall oxide 40 to cover the now exposed polysilicon 34. An exemplary thickness may be between 1 to 10 nm, for example 5 nm. The oxidation may oxidize other parts of the array, such as the bottom oxide 39 (if present) or the exposed silicon of substrate 30. For the former, bottom oxide 39 may become thicker, such as from 1-5 nm, for example 2 nm thicker. For the latter, the oxidation may react with the exposed silicon, annealing any damage, such as due to the etching of silicon substrate 30. The latter embodiment may provide a better controlled bottom oxide 39 for implanting the bit lines, as described hereinbelow.
A pocket implant 41 (
In step 112, spacers 42 may be generated on the sides of polysilicon columns 34. For example, spacers 42 may be generated by deposition of an oxide liner, such as of 12 nm, and an anisotropic etch, to create the spacer shape. Alternatively, the liner may be left as it is without forming a spacer
Spacers 42 may decrease the width of bit line openings, labeled 37′ in
Once spacers 42 have been formed, bit lines 50 may be implanted (step 114), followed by a rapid thermal anneal (RTA). In one exemplary embodiment, the bit line implant is of Arsenic of 1.5-3×1015/cm2 at 10-20 Kev and with an angle of 0 or 7% to the bit line.
In step 116, an oxide filler 52 may be deposited on the chip. As can be seen in
In step 120, nitride hard mask 36 may be removed, typically via a nitride wet etch, leaving exposed polysilicon surface above polysilicon elements 34. A second polysilicon layer 54 and a silicide layer 55 may then be deposited (step 122) on the entire wafer. Second polysilicon layer 54 may come into electrical contact with polysilicon elements 34 where the latter are exposed. Layers 54 and 55 may then be etched (step 124) into word lines 56 (
In another embodiment, the step of depositing silicide layer 55 may be replaced with a salicide (self aligned silicidation) process after word line patterning and CMOS spacer etch.
The layout of polysilicon elements 34 and second polysilicon layer 54 may be seen more clearly in
Together, polysilicon elements 34 and word lines 56 may form the gates of each NROM cell. In addition, the polysilicon layers may form the gates, and some interconnections, in the CMOS periphery.
A sidewall oxide 58 (
In step 128, an anti-punchthrough implant 59 may be generated between bit lines 50, where portions 34′ of first polysilicon elements 34 were removed. An anti-punchthrough implant may be of Boron (B) of 10-50 Kev at 5-20×1012/cm2. Alternatively, the anti-punchthrough implant may comprise a multiplicity of implants with different energies and doses in the same location. For example, there might be three consecutive implants of Boron, of 5×1012 at 15 Kev, 3×1012 at 25 Kev and 3×1012 at 35 Kev. Alternatively, the Boron may be replaced by BF2 or Indium, or compounds/alloys containing Boron and/or Indium and/or other p type dopants.
Finally, oxide spacers may be deposited (step 130) for the transistors CMOS periphery. The deposition may cover the entire wafer and may fill or partially fill between word lines 56, providing an insulation between word lines 56.
DPP with Double BB Implant
To improve the optimization of the pocket implant (PI) and the bitline (BL) optimization, it is desired to decouple, as much as possible, the PI-to-BL junction edge and overlap (OL) under the poly, from the BL resistance considerations.
In the process described hereinabove, the BL implant is performed in one step (step 114), after forming (generating) oxide spacers 42 (step 112) on the sides of poly columns 34, and through a reduced-size opening 37′ between adjacent poly columns 34. (Sidewall oxidation 40 omitted from this portion of the discussion.)
According to this embodiment of the disclosure, generally, the buried bitline (BB) implant is performed into two separate steps (in addition to the PI implant)—a first BB implant step that is similar to the process described hereinabove, and a second BB implant which is performed after forming another (a second) spacer in the opening through which the bitline implant is performed. The first BB implant is generally for PI-to-BL edge optimization. The second BB implant generally controls the BL resistance.
The two buried bitline (BB) implantation steps may be performed at the same or with different concentrations, at the same or with different dopants, and at the same or with different energies than one another. Generally, the first bitline implant is designated “BB Imp #1”, and the second bitline implant is designated “BB Imp #2”. For example,
BB Imp #1—1.0-1.5×15 cm2, 10-20 Kev, Arsenic (As)
then a spacer, followed by
BB Imp #2—1-3×1015 cm2, 10-40 Kev, Arsenic (As)
(In the previous example, a single bitline implant was performed with Arsenic at 1.5-3×1015 cm2, 10-20 Kev.)
Thus, a buried bitline (BB) may be formed having a region of higher dopant concentration at one or more portions (such as in the center) of a doped bitline, and such higher concentration region(s) may have a width dimension which is less than the minimum line-width or feature size provided for by the design rules for fabrication of the microelectronics device. Such multiple concentration of dopant in the buried bitline being referred to as a “double buried bitline” (although more than two concentrations or areas of differing concentration are specifically intended and contemplated).
It can be observed, from
According to this embodiment of the disclosure, the overlap (OL) of BL under poly and the PI-to-BL transition can be optimized for retention, programming and erase. And the BL resistance can be optimized almost independent of the PI to BL transition.
Generally, a process of this embodiment requires one or more extra spacer(s) and one or more extra implant(s), as contrasted with the previously described embodiment.
An exemplary process flow is now described. Reference is made to
In a manner which may be similar to that of the previous embodiment, starting with a semiconductor (typically silicon) substrate 602, first, in a step 502, an ONO layer 604 is deposited, using conventional techniques. The ONO layer 604 may have an overall thickness of approximately 10-25 nm (nanometers), such as 18 nM, as follows, although the scope of the disclosure is not limited in this respect:
the bottom oxide layer may be from 3 to 6 mm, for example 4 nm thick;
the middle nitride layer may be from 3 to 8 nm, for example 4 nm thick; and
the top oxide layer may be from 5 to 15 nm, for example 10 nm thick.
In a manner similar to that of the previous embodiment, ONO or parts of the ONO, may be removed from the periphery; growth of periphery gate oxides and implant VT implants may also be performed as discussed hereinabove (step 102), but are omitted from this process flow, for illustrative clarity, although the scope of the disclosure is not limited in this respect.
Next, in a step 504 (compare step 104), a first layer of polysilicon 606 is deposited, using conventional techniques. The first layer of polysilicon (“poly”) may have an exemplary thickness of approximately 30 nm to 100 nm, for example 50 nm, although the scope of the disclosure is not limited in this respect.
Next (as in the previous embodiment), in a step 506 (compare 106), a hard mask 608 is deposited and is patterned. The hard mask 608 may comprise silicon nitride (“nitride”), and may have an exemplary thickness of approximately 50 to 150 nm, for example 50 nm, although the scope of the disclosure is not limited in this respect.
Next (as in the previous embodiment), in a step 508 (compare 108) bit line openings 610 are etched. to have openings 610 at positions where pocket implants and bit line implants will be formed (implanted) in the underlying substrate 602, as discussed hereinbelow. Etching of the hard mask 608 and usually polysilicon 606 is suitably stopped (such as using selective etching) on the bottom oxide layer of the ONO layer 604, using conventional techniques, although the scope of the disclosure is not limited in this respect.
Next (as in the previous embodiment), in a step 510 (compare 110), a pocket implant 612 is implanted through the ONO 604, in an area of the substrate 602 under the opening 610, using conventional techniques, although the scope of the disclosure is not limited in this respect. An exemplary pocket implant 612 may be of 0.5-6×1013/cm2 (dose of the dopant per unit area) and energy of 10-20 Kev (as in the previous example), 0-25° tilt, boron (B), although the scope of the disclosure is not limited in this respect. The resulting structure is shown in
Next (as in the previous embodiment), in a step 512 (compare 112), first spacers 642 are formed on the inside walls of the opening 610 extending through the hard mask 608 and the poly 606. Supposing that the opening 610 has a dimension F (minimum feature size), the first spacers 642 usually reduce the size of the opening such as to F minus two times the spacer thickness. The first spacers 642 may be of nitride or oxide or poly or other suitable material, and may have an exemplary thickness of approximately 10-20 nm, such as 12 nm. Therefore, the resulting opening 610′ (reduced-size opening 610) measures F−24 nm (F−(2×12 nm)), although the scope of the disclosure is not limited in this respect. Thus, the resulting opening has a dimension (width, in this case), which is less than the minimum feature size (F) provided for (such as contemplated or permitted) under the process design rules. The resulting structure is shown in
Generally, the purpose of the spacer 642 is to achieve an opening having a size which is less than F, the minimum feature size which can be achieved using lithographic techniques. So, if the original opening 610 has the minimum achievable feature size of F, and it is desired to do a self-aligned implant using the feature, by depositing material (the spacer) on the inner walls of the opening, an opening 610′ having a feature size of <F (less than F) can be achieved. The resulting structure is shown in
By way of example, F 65 nm, the opening 610′ measures 41 nm across (left-to-right as viewed in the Figure). The pocket implant 612 is centered under the opening 610′, and measures 65 nm across, and 15 nm deep (vertical, into the substrate, as viewed in the Figure.) The pocket implant 612 is wider across than the opening 610′.
Next, in a step 514, a first buried bitline implant (BL IMP #1) is performed. The first buried bitline implant is labeled 614 (
As mentioned above, this first buried bitline implant (BL IMP #1) may or may not be through the ONO bottom oxide or through the ONO nitride and bottom oxide. If the bottom oxide was removed during forming the openings in the poly 606, an oxidation step may be performed to protect the bare silicon, as discussed above, although the scope of the disclosure is not limited in this respect. The resulting structure is shown in
By way of example, the first bitline implant 614 measures 40 nm across, and 25 nm deep (vertical, into the substrate, as viewed in
Next, in a step 540, second spacers 652 are formed within the opening 610′, generally on the exposed surfaces of the first spacers 642, using conventional processes. The second spacers 642 may be of nitride or oxide, or other materials, and may have an exemplary thickness of approximately 5-12 nm. Therefore, the resulting opening 610″ between word lines 634 measures F minus 24 nm (twice the thickness of the first spacers), minus 10-24 nm (twice the thickness of the second spacers 652), although the scope of the disclosure is not limited in this respect.
Next, in a step 542, a second buried bitline implant (BL IMP #2) is performed. The second buried bitline implant is labeled 616 (
If the bottom oxide layer of the ONO 604 is still in place (as shown), the second bitline implant is performed through the bottom layer of the ONO. The resulting structure is shown in
By way of example, the second bitline implant 616 measures 30 nm across, and 50 nm deep (vertical, into the substrate, as viewed in the
By using the techniques of this disclosure, a double buried bitline (BB) may be formed within the substrate 602, aligned under an opening 610 (610′, 610″) between poly structures 634 and having the following relative dimensions and geometry:
a pocket implant 612 having a first width (W1) and a first depth (D1);
a first BB implant 614 which is vertically aligned with the pocket implant and having a second width (W2) which is less than the first width (W2<W1), such as less than 90% of the width of the pocket implant, including less than 80%, less than 70% less than 60% and approximately 50% less.
the first BB implant 614 has a second depth (D2) which may be greater than the first depth (D1), such as at least 10% greater, including at least 25% greater, at least 50% greater, at least 75% greater and approximately 100% greater.
a second BB implant 616 which is vertically aligned with the first BB implant and having a third width (W3) which may be less than the second width (W3<W2), such as less than 90% of the width of the first BB implant, including less than 80%, less than 70% less than 60% and approximately 50% less.
the second BB implant 616 has a third depth (D3) which may be greater than the second depth (D2), such as at least 10% greater, including at least 25% greater, at least 50% greater, at least 75% greater and approximately 100% greater.
Finally, an oxide fill 652 is deposited and may be chem-mech polished, or otherwise planarized or reduced in cross-sectional height, followed by removal of the Nitride Hard Mask depositing a second polysilicon layer 654 and a silicide layer 655, using conventional techniques. Generally, all of the final processing steps 116-130, described hereinabove (designated in
This embodiment is generally a simple addition to the previously-described process, and the optimization that can be achieved generally justifies the extra process steps (two sidewall spacers rather than one, two bitline implants rather than one).
Another Embodiment (Implant Through Poly)
The two embodiments described above (
In this embodiment, generally, the pocket implant is made through the poly, before being opened. Then, two bitline (BL) implants are performed, in a manner similar to that of the previous (
To improve the optimization of the pocket implant (PI) and the bitline (BL) optimization, it is desired to decouple, as much as possible, the PI-to-BL junction edge and overlap (OL) under the poly, from the BL resistance considerations.
In the process described hereinabove (
According to this embodiment of the disclosure, generally, the buried bitline (BB) implant is performed into two separate steps (in addition to the PI implant)—a first BB implant step that is similar to the process described hereinabove, and a second BB implant which is performed after forming another (a second) spacer in the opening through which the bitline implant is performed. The first BB implant is generally for PI-to-BL edge optimization. The second BB implant generally controls the BL resistance.
The two buried bitline (BB) implantation steps may be performed at the same or with different concentrations, at the same or with different dopants, and at the same or with different energies than one another. Generally, the first bitline implant is designated “BB Imp #1”, and the second bitline implant is designated “BB Imp #2”. For example,
BB Imp #1—1.0-1.5×1015 cm, 10-20 Kev, Arsenic (As)
then a spacer, followed by
BB Imp #2—1-3×1015 cm2, 10-40 Kev, Arsenic (As)
(In the previous example, a single bitline implant was performed with Arsenic at 1.5-3×1015 cm2, 10-20 Kev.)
Thus, a buried bitline (BB) may be formed having a region of higher dopant concentration at one or more portions (such as in the center) of a doped bitline, and such higher concentration region(s) may have a width dimension which is less than the minimum line-width or feature size provided for by the design rules for fabrication of the microelectronics device. Such multiple concentration of dopant in the buried bitline being referred to as a “double buried bitline” (although more than two concentrations or areas of differing concentration are specifically intended and contemplated).
It can be observed, from
According to this embodiment of the disclosure, the overlap (OL) of BL under poly and the PI-to-BL transition can be optimized for retention, programming and erase. And the BL resistance can be optimized almost independent of the PI to BL transition.
Generally, a process of this embodiment requires one or more extra spacer(s) and one or more extra implant(s), as contrasted with the previously described embodiment.
An exemplary process flow is now described. Reference is made to
In a manner which may be similar to that of the previous embodiments, starting with a semiconductor (typically silicon) substrate 802, first, in a step 702, an ONO layer 804 is deposited, using conventional techniques. The ONO layer 804 may have an overall thickness of approximately 10-25 nm, such as 18 nm, as follows, although the scope of the disclosure is not limited in this respect:
the bottom oxide layer may be from 3 to 6 nm, for example 4 nm thick;
the middle nitride layer may be from 3 to 8 nm, for example 4 nm thick; and
the top oxide layer may be from 5 to 15 nm, for example 10 nm thick.
In a manner similar to that of the previous embodiment, ONO or parts of the ONO, may be removed from the periphery; growth of periphery gate oxides and implant VT implants may also be performed as discussed hereinabove, but are omitted from this process flow, for illustrative clarity, although the scope of the disclosure is not limited in this respect.
Next, in a step 704, a first layer of polysilicon 806 is deposited, using conventional techniques. The first layer of polysilicon (“poly”) may have an exemplary thickness of approximately 30 nm to 100 nm, for example 50 nm, although the scope of the disclosure is not limited in this respect.
Next, in a step 706, a hard mask 808 is deposited and is patterned (etched) to have openings 810 at positions where pocket implants (P1) and bit line (BL) implants will be formed (implanted) in the underlying substrate 802, as discussed hereinbelow. Etching of the hard mask 808 is suitably stopped (such as using selective etching) on the underlying poly 806, using conventional techniques. The hard mask 808 may comprise silicon nitride (“nitride”), and may have an exemplary thickness of approximately 50 to 150 nm, for example 50 nm, although the scope of the disclosure is not limited in this respect.
Here is where the present embodiment deviates from the previously-described embodiments—namely, pocket implant is performed through the poly, as described hereinbelow.
Next, in a step 710, a pocket implant 812 is implanted, through the poly 806 and through the ONO 804, in an area of the substrate 802 under the opening 810, using conventional techniques, although the scope of the disclosure is not limited in this respect.
Notice that, in this embodiment, the steps 108 (etch bit line openings) and 109 (sidewall oxidation) of the previous embodiment are not performed before the step of pocket implant (step 710), although the scope of the disclosure is not limited in this respect.
An exemplary pocket implant 812 may be of 0.5-6×1013/cm2 (dose of the dopant per unit area) and energy of 10-20 Kev (as in the previous example), no tilt, boron (B), although the scope of the disclosure is not limited in this respect. Generally, the energy depends on the poly thickness. The pocket implant 812 may be BF2 or Indium (less likely in this case due to the required deep trajectory that is required), as well as boron (B). The resulting structure is shown in
Next, in a step 712, first spacers 842 are formed on the inside walls of the opening 810 in the hard mask 808. Supposing that the opening 810 has a dimension F (minimum feature size), the spacers usually reduce the size of the opening such as to F minus two times the spacer thickness. The first spacers 842 may be of nitride or oxide, and may have an exemplary thickness of approximately 10-20 nm or 12 nm as an example: Therefore, the resulting opening 810′ in the mask 808 measures F−24 nm (F−(2×12 nm)), although the scope of the disclosure is not limited in this respect. Thus, the resulting opening has a dimension (width, in this case), which is less than the minimum feature size provided for (such as contemplated or permitted) under the process design rules. The resulting structure is shown in
There is now disclosed one type of a departure from the previously described method. In the previously-described method, the (only) spacer 42 is formed on the opening 37 which expectedly extends through both the nitride mask 36 and the poly 31. In this embodiment, there is no opening in the poly 806 (yet), so the first spacer 842 is formed only on the sidewalls of the opening 810 in the nitride mask, although the scope of the disclosure is not limited in this respect.
Generally, the purpose of the spacer 842 is to achieve an opening having a size which is less than F, the minimum feature size which can be achieved using lithographic techniques. So, if the original opening 810 has the minimum achievable feature size of F, and it is desired to do a self-aligned implant using the feature, by depositing material (the spacer) on the inner walls of the opening, an opening 810′ having a feature size of <F (less than F) can be achieved. The resulting structure is shown in
By way of example, F=65 nm, the opening 810′ measures 41 nm across (left-to-right as viewed in the Figure). The pocket implant 812 may be centered under the opening 810, and measures 65 nm across, and 15 nm deep (vertical, into the substrate, as viewed in the Figure.) The pocket implant 812 is wider across than the opening 810.
Next, in a step 708, the poly 806 and the underlying ON layer is etched to create an opening 810″, using conventional techniques, leaving the bottom oxide in place (as described hereinabove). The modified (etched) poly 806 and ONO 804 are designated 806′ and 804′, respectively, in
The bottom oxide layer of the ONO layer 804 may be left in place, as discussed hereinabove, although it is shown removed in the Figure (
Sidewall oxidation of the polysilicon structures 834 may or may not be performed, as discussed hereinabove, but is omitted from this process flow (as well as from the Figure) for illustrative clarity, although the scope of the disclosure is not limited in this respect.
Next, in a step 714, a first buried bitline implant (BL IMP #1) is performed. The first buried bitline implant is labeled 814 (
As mentioned above, this first buried bitline implant (BL IMP #1) may or may not be through the ONO bottom oxide. If the bottom oxide was removed during forming the openings in the poly 806, an oxidation step may be performed to protect the bare silicon, as discussed above, although the scope of the disclosure is not limited in this respect. The resulting structure is shown in
By way of example, the first bitline implant 814 measures 40 nm across, and 25 nm deep (vertical, into the substrate, as viewed in
Next, in a step 740, second spacers 852 are formed within the opening 810″, including on the first spacers 842 as well as extending downward into the opening 810″ and on the on the sidewalls of the poly structures 834, using conventional processes. The second spacers 842 may be of nitride or oxide, or other materials, and may have an exemplary thickness of approximately 5-12 nm: Therefore, the resulting opening 810′″ between word lines 834 measures F minus 24 nm (twice the thickness of the first spacers), minus 10-24 nm (twice the thickness of the second spacers 852), although the scope of the disclosure is not limited in this respect.
Next, in a step 742, a second buried bitline implant (BL IMP #2) is performed. The second buried bitline implant is labeled 816 (
If the bottom oxide layer of the ONO 804 is still in place, the second bitline implant is performed through the bottom layer of the ONO. The resulting structure is shown in
By way of example, the second bitline implant 816 measures 30 nm across, and 50 nm deep (vertical, into the substrate, as viewed in the
By using the techniques of this disclosure, a double buried bitline (BB) may be formed within the substrate 802, aligned under an opening 814′ between poly structures 834 and having the following relative dimensions and geometry:
a pocket implant 812 having a first width (W1) and a first depth (D1);
a first BB implant 814 which is vertically aligned with the pocket implant and having a second width (W2) which is less than the first width (W2<W1), such as less than 90% of the width of the pocket implant, including less than 80%, less than 70% less than 60% and approximately 50% less.
the first BB implant 814 has a second depth (D2) which may be greater than the first depth (D1), such as at least 10% greater, including at least 25% greater, at least 50% greater, at least 75% greater and approximately 100% greater.
a second BB implant 816 which is vertically aligned with the first BB implant and having a third width (W3) which may be less than the second width (W3<W2), such as less than 90% of the width of the first BB implant, including less than 80%, less than 70% less than 60% and approximately 50% less.
the second BB implant 816 has a third depth (D3) which may be greater than the second depth (D2), such as at least 10% greater, including at least 25% greater, at least 50% greater, at least 75% greater and approximately 100% greater.
Finally, an oxide fill 852 is deposited and may be chem-mech polished, or otherwise planarized or reduced in cross-sectional height, followed by removal of the Nitride Hard Mask and depositing a second polysilicon layer 854 and a silicide layer 855, using conventional techniques. Generally, all of the final processing steps 116-130, described hereinabove (designated in
This embodiment is generally a simple addition to the previously-described process (
While a number of exemplary aspects and embodiments have been discussed above, those of skill in the art will recognize certain modifications, permutations, additions and sub-combinations thereof. It is therefore intended that the following appended claims and claims hereafter introduced be interpreted to include all such modifications, permutations, additions and sub-combinations.
This is a non-provisional filing of U.S. Provisional Application No. 60/773,673, filed 16 Feb. 2006 by Boaz Eitan. This is a continuation-in-part of U.S. patent application Ser. No. 11/247,733 filed 10 Oct. 2005, which claims priority from U.S. Provisional Application No. 60/618,165 filed 14 Oct. 2004.
| Number | Date | Country | |
|---|---|---|---|
| 60773673 | Feb 2006 | US | |
| 60618165 | Oct 2004 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 11247733 | Oct 2005 | US |
| Child | 11461989 | Aug 2006 | US |
