Patent Application
20100070676
Memory devices typically have several independently accessible arrays of memory cells for storing information commonly known as ‘banks’. The memory banks, along with other support logic, are fabricated on a semiconductor substrate to yield a memory device. Logic common to all banks is typically arranged in a central part of the substrate. The common logic controls access to different ones of the banks during memory operations such as reads and writes. Each different bank is conventionally coupled to the common logic via a separate, dedicated data bus. Data is read from and written to the different banks over the dedicated buses. Each bus coupled to a memory bank has a width corresponding to the width of the bank, e.g., 32 bits. To increase the capacity of a memory device, more banks are usually added to the device. However, a new bus is also conventionally added for each new bank for coupling the new banks to the common logic of the memory device. The overall bus size and power approximately doubles each time the number of memory banks included in a memory device doubles.
In one embodiment, a memory device comprises a plurality of memory banks. At least two of the memory banks share the same bus. Logic is coupled to the memory banks via the different buses. The logic controls access to the memory banks. A bi-directional tri-state buffer is interposed between adjacent memory banks along the same bus so that each bus is segmented into a plurality of sections, each bus section being coupled to one or more different ones of the memory banks.
Of course, the present invention is not limited to the above features and advantages. Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.
Broadly, the banks 104 may be arranged in any manner. The common logic 106 is coupled to the memory banks 106 via the different buses 108-112 (Step 202). A bi-directional tri-state buffer 114 is interposed between adjacent ones of the memory banks 104 along the same bus, segmenting each bus 108-112 into a plurality of sections (Step 204). Each bus section is coupled to one or more different ones of the memory banks 104. In the embodiment illustrated in
In more detail, the common logic 106 includes control logic 124 for determining which bank 104 is to be accessed during a memory operation and what type of operation is being performed. The control logic 124 then activates each bi-directional tri-state buffer 114 interposed between the common logic 106 and the target bank 104 to be accessed. For purely illustrative purposes only, consider a write operation directed to BANK0. The control logic 124 activates each bi-directional tri-state buffer 114 interposed between the common logic 106 and BANK0 along the first bus 108. Broadly, the control logic 124 ensures that a non-contentious data path is provided between the common logic 106 and the memory banks 104 during memory operations.
In one embodiment, the control logic 124 receives information indicating which bank 104 (BANK) is to be accessed during a memory operation and whether the memory operation is a read (R) or write (W). This information may be internally generated by the memory device 100, e.g., by master control logic (not shown) included in the memory device 100. Alternatively, the bank and read/write information may be provided to the control logic 124 from an external memory controller (not shown). Either way, the control logic 124 uses the bank and read/write information to determine which bi-directional tri-state buffers 114 are to be activated during a particular memory operation and which ones are not.
The control logic 124 also deactivates each bi-directional tri-state buffer 114 not disposed along the data path of interest. In one embodiment, the control logic 124 deactivates each bi-directional tri-state buffer 114 located further from the common logic 106 than the target memory bank 104 along the bus that couples the logic 106 to the target bank 104. Each bi-directional tri-state buffer 114 disposed along the other buses may also be deactivated. Consider another purely illustrative example where a read operation is directed to BANK3. The control logic 124 deactivates the bi-directional tri-state buffer 114 interposed between BANK2 and BANK3 along the second data bus 110, preventing data contention between BANK2 and BANK 3 and reducing capacitive loading on the second bus 110 during the read operation. The bi-directional tri-state buffers 114 disposed along the other data buses may also be deactivated. By deactivating the bi-directional tri-state buffers 114 not disposed along the desired data path, the common logic 124 prevents data contention and reduces capacitive loading on the buses 108-112.
The common logic 124 is also coupled to a global data bus (DQ) of the memory device 100. The global data bus is the main data interface between the memory device 100 and devices (not shown) external to the memory device 100. The common logic 124 controls data flow between the global data bus and the memory banks 104 during memory operations. To this end, the common logic 124 includes a multiplexer circuit 126 and a plurality of buffer circuits 128-134. The control logic 124 generates a control signal (CTRL) which is applied to the multiplexer circuit 126. The control signal determines which common logic buffer circuit 128-134 is coupled to the multiplexer circuit 126 during a particular memory operation. The buffer circuit selected depends on which bank 104 is being accessed during the operation. Operation of the common logic buffer circuits 128-134 is controlled similarly to the bi-directional tri-state buffers 114 to minimize data contention and capacitive loading.
In one embodiment, the control logic 124 generates read and write control signals (r/w) that are applied to the common logic buffer circuits 128-134 and to the bi-directional tri-state buffers 114. The state of the read and write control signals is set based on which bank 104 is being accessed and what type of memory operation is being performed. In one embodiment, the read and write control signals are programmed based on the bank (BANK) and read/write (R/W) information provided to the control logic 124 as previously described above.
During a write operation, data present on the global data bus is written to one of the memory banks 104. The common logic 124 enables a data path between the target memory bank 104 and the global data bus by directing the multiplexer circuit 126 to couple the global data bus to the appropriate buffer circuit (e.g., the first buffer circuit 128 when BANK0 is the target memory bank 104). The control logic 124 activates the appropriate buffer circuit by enabling the corresponding write control signal, coupling the buffer circuit to the proper data bus (the first data bus 108 in this example). The control logic 124 also activates each bi-directional tri-state buffer 114 interposed between the common logic 106 and the target bank 104 (BANK0 in this example). I/O (input/output) circuitry 136 associated with the target bank 104 senses the data on the activated bus (the first bus 108 in this example) and writes the data to the addressed memory array location.
During a read operation, data is read from one of the memory banks 104 and driven onto the global data bus. The control logic 124 enables a path between the target memory device 104 and the global data bus by directing the multiplexer circuit 126 to couple the global data bus to the appropriate buffer circuit (e.g., the second buffer circuit 130 when BANK3 is the target memory bank 104). The control logic 124 activates the appropriate buffer circuit by enabling the corresponding read control signal, coupling the buffer circuit to the proper data bus (the second data bus 110 in this example). The control logic 124 also activates each bi-directional tri-state buffer 114 interposed between the common logic 106 and the target bank 104 (BANK3 in this example). In this example, the bi-directional tri-state buffer 114 interposed between BANK2 and BANK3 is deactivated to prevent data contention and reduce capacitive loading on the second data bus 110. The I/O circuitry 136 associated with BANK3 senses the data read out of the bank 104 and drives the sensed data onto the activated bus (the second bus 110 in this example). The data is then driven from the global data bus off-chip.
Broadly, the control logic 124 maintains proper operation of the memory device 100 by programming the read and write buffer control signals (r/w) and controlling the multiplexer circuit 126 based on the bank (BANK) and read/write (R/W) information provided to the control logic 124. This way, the memory banks 104 can share different ones of the data buses 108-112 without causing data contention or degrading memory device performance. Sharing the data buses 108-112 between two or more of the memory banks 104 reduces the overall area of the memory device 100, reduces power consumption and improves performance because fewer bus lines are present to cause capacitive coupling.
According to the embodiment illustrated in
The common logic 106 controls bus access as described above. According to the embodiment shown in
In response, each bi-directional tri-state buffer 114 interposed between the common logic 106 and the target memory bank 104 along the bus that couples the bank 104 to the logic 106 is activated. Each bi-directional tri-state buffer 114 disposed further from the common logic 106 than the target memory bank 104 along the bus that couples the logic 106 to the target bank 104 is deactivated to prevent data contention and reduce capacitive coupling. Each bi-directional tri-state buffer 114 disposed along the other buses may also be deactivated. This way, the target memory bank 104 is coupled to the global data bus (DQ) through the common logic 106 using a shared data bus. Data can be written to or read from the memory device 100 via this path.
Regardless, the bi-directional tri-state buffers 114 are interposed between adjacent ones of the memory banks 104 coupled to the same bus. According to this embodiment, a first one of the bi-directional tri-state buffers 114 is interposed between BANK0/BANK2 and BANK1/BANK3 because BANK0, BANK1, BANK2 and BANK3 share the same bus 500 even though they are in different rows. A second one of the bi-directional tri-state buffers 114 is similarly interposed between BANK5/BANK7 and BANK4/BANK6. The common logic 106 controls bus access as described above. According to the embodiment shown in
In response, each bi-directional tri-state buffer 114 interposed between the common logic 106 and the target memory bank 104 along the bus that couples the bank 104 to the logic 106 is activated. Each bi-directional tri-state buffer 114 disposed further from the common logic 106 than the target memory bank 104 along the bus that couples the logic 106 to the target bank 104 is deactivated to prevent data contention and reduce capacitive coupling. Each bi-directional tri-state buffer 114 disposed along the other buses may also be deactivated. This way, different ones of the memory banks 104 can be coupled to the global data bus (DQ) via the common logic 106 using shared data buses 500, 502 that are segmented into a plurality of sections 508-514 by the bi-directional tri-state buffers 114 disposed along the respective buses 500, 502.
The bi-directional tri-state buffers 114 are shown in more detail in
The embodiment illustrated in
The buffer element 520 has additional circuitry 604, 606 for controlling when the read and write driver circuitry 600, 602 is enabled, respectively. During a read operation, a first circuit 604 enables the read driver circuitry 600 when the target memory bank 104 is coupled to the same bus as the buffer element 520 and the buffer element 520 is interposed between the target bank 104 and the common logic 106, i.e., the buffer element 520 is disposed in the desired data path. Under these conditions, the common logic 106 activates the read control signal (rx) applied to the buffer element 520 of the rth bi-directional tri-state buffer 114. In response, a first inverter 608 and NOR gate 610 of the first circuit 604 activates an n-FET device N1 of the read driver circuitry 600. A second inverter 612 of the first circuit 604 causes the output of a NAND gate 614 of the first circuit 604 to be a function of the state of the first data line port (rwdlna).
One bit of data to be read from the target memory bank 104 is present on the first data line port. When this data bit is a logic one, the NAND gate 614 outputs a logic zero to a p-FET device P1 of the read driver circuitry 600. The p-FET device P1 in turn drives the second data line port (rwdlnb) to a logic one state. The n-FET device N1 of the read driver circuitry 600 similarly drives the second data line port to a logic zero state when the first data line port is at a logic zero state. The common logic 106 deactivates the write control signal (wx) applied to the buffer element 520 during read operations to disable the write driver circuitry 602, preventing data contention between the first and second data line ports.
During write operations, a second circuit 606 enables the write driver circuitry 602 when the buffer element 520 is interposed in the data path of interest, i.e., between the target memory bank 104 and the common logic 106. Under these conditions, the common logic 106 deactivates the read control signal (rx) and activates the write control signal (wx). In response, a first inverter 616 and NOR gate 618 of the second circuit 606 activates an n-FET device N2 of the write driver circuitry 602. A second inverter 620 of the second circuit 606 causes the output of a NAND gate 622 of the second circuit 606 to be a function of the state of the second data line port (rwdlnb).
One bit of data to be written to the target memory bank 104 is present on the second data line port. When this data bit is a logic one, the NAND gate 622 of the second circuit 606 outputs a logic zero to a p-FET device P2 of the write driver circuitry 602. The p-FET device P2 correspondingly drives the first data line port (rwdlna) to a logic one state. The n-FET device N2 of the write driver circuitry 602 similarly drives the first data line port to a logic zero state when the second data line port is at a logic zero state. A keeper circuit 624 stores the current bit of data output by the write driver circuitry 602 in the buffer element 520. The read control signal (rx) is disabled during write operations to disable the read driver circuitry 600, preventing data contention between the first and second data line ports.
With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.
