MEMORY DEVICE AND MANUFACTURING METHOD OF THE MEMORY DEVICE

Abstract

A memory device includes isolation layers and gate structures alternately stacked on a lower structure and a tunnel isolation layer penetrating the isolation layers and the gate structures. The memory device also includes a channel layer formed along an inner wall of the tunnel isolation layer and a core plug formed along an inner wall of the channel layer. Each of the gate structures includes: a floating gate surrounding an outer wall of the tunnel isolation layer; a first dielectric layer surrounding an outer wall of the floating gate; a second dielectric layer surrounding an outer wall of the first dielectric layer; a third dielectric layer surrounding an outer wall of the second dielectric layer; and a gate line formed between the isolation layers, the gate line filling a region surrounded at least in part by the third dielectric layer.

Description

Claims

1. A memory device comprising: isolation layers and gate structures, alternately stacked on a lower structure;a tunnel isolation layer penetrating the isolation layers and the gate structures;a channel layer formed along an inner wall of the tunnel isolation layer; anda core plug formed along an inner wall of the channel layer,wherein each of the gate structures includes:a floating gate surrounding an outer wall of the tunnel isolation layer;a first dielectric layer surrounding an outer wall of the floating gate;a second dielectric layer surrounding an outer wall of the first dielectric layer;a third dielectric layer surrounding an outer wall of the second dielectric layer; anda gate line formed between the isolation layers, the gate line filling a region surrounded at least in part by the third dielectric layer.

2. The memory device of claim 1, wherein the core plug is formed in a cylindrical shape, the channel layer is formed in a tubular shape surrounding a side surface of the core plug, andthe tunnel isolation layer is formed in a tubular shape surrounding a side surface of the channel layer.

3. The memory device of claim 1, wherein: the core plug is formed of an isolation material,the channel layer is formed of poly-silicon, andthe tunnel isolation layer is formed of silicon oxide.

4. The memory device of claim 1, wherein the floating gate is formed in a tubular shape surrounding the tunnel isolation layer.

5. The memory device of claim 1, wherein the floating gate comprises a material capable of storing electrons.

6. The memory device of claim 1, wherein the floating gate comprises at least one of titanium nitride (TiN) and tantalum nitride (TaN).

7. The memory device of claim 1, wherein the first dielectric layer comprises a material having a permittivity lower than a permittivity of each of the second and third dielectric layers.

8. The memory device of claim 1, wherein the first dielectric layer comprises a material having an energy band gap higher than an energy band gap of the second dielectric layer.

9. The memory device of claim 1, wherein the first dielectric layer comprises a silicon oxide.

10. The memory device of claim 1, wherein: the second dielectric layer has a permittivity higher than a permittivity of the first dielectric layer and a permittivity of the third dielectric layers, andthe second dielectric layer has an energy band gap lower than an energy band gap of the first dielectric layer and lower than an energy band gap of the third dielectric layer.

11. The memory device of claim 1, wherein the second dielectric layer comprises at least one of silicon nitride, hafnium oxide, zirconium oxide, zirconium silicate, and hafnium silicate.

12. The memory device of claim 1, wherein the third dielectric layer comprises an aluminum oxide.

13. The memory device of claim 1, wherein the gate line is a select line or a word line, which is connected to a memory block.

14. The memory device of claim 1, wherein the gate line comprises a conductive layer or a semiconductor layer.

15. The memory device of claim 1, wherein the gate line comprises at least one of tungsten (W), tungsten nitride (WN), titanium nitride, molybdenum (Mo), cobalt (Co), nickel (Ni), silicon (Si), and poly-silicon (Poly-Si).

16. The memory device of claim 1, further comprising a barrier layer formed between the gate line and the third dielectric layer.

17. The memory device of claim 16, wherein the barrier layer comprises tungsten nitride (WN) or titanium nitride (TiN).

18. A method of manufacturing a memory device, the method comprising: alternately stacking isolation layers and sacrificial layers on a lower structure;forming a vertical hole penetrating the isolation layers and the sacrificial layers;forming first recesses by removing portions of the sacrificial layers exposed by the vertical hole;forming a first dielectric layer along a respective inner wall of the sacrificial layers exposed through the first recesses;forming a floating gate inside a respective first recess in which the first dielectric layer is formed;forming a cell plug inside the vertical hole;forming second recesses by removing portions of the sacrificial layers to expose outer walls of the first dielectric layers;forming a second dielectric layer on a respective outer wall of the first dielectric layers;forming a third dielectric layer in a respective second recess along a respective outer wall of the second dielectric layers and along respective surfaces of the isolation layers; andforming a gate line inside a respective second recess in which the third dielectric layer is formed.

19. The method of claim 18, wherein forming the first dielectric layer comprises performing a radical oxidation process.

20. The method of claim 18, wherein forming the second dielectric layer and forming the third dielectric layer comprise performing a thermal atomic layer deposition process.

21. The method of claim 18, wherein the third dielectric layer is formed to have a permittivity higher than a permittivity of the first dielectric layer.

22. The method of claim 18, wherein the floating gate is formed to include at least one of titanium nitride (TiN) and tantalum nitride (TaN).

23. The method of claim 18, wherein the first dielectric layer is formed to have an energy band gap higher than an energy band gap of the second dielectric layer.

24. The method of claim 18, wherein the first dielectric layer is formed of a silicon oxide.

25. The method of claim 18, wherein the second dielectric layer is formed of at least one of silicon nitride, hafnium oxide, zirconium oxide, zirconium silicate, and hafnium silicate.

26. The method of claim 18, wherein the third dielectric layer is formed of an aluminum oxide.

27. The method of claim 18, further comprising forming a barrier layer along an inner wall of the third dielectric layer after forming of the third dielectric layer and before forming of the gate line.