MEMORY DEVICE AND OPERATING METHOD THEREOF

Abstract

A memory device includes a target memory block and a peripheral circuit configured to float local word lines which are coupled to the target memory block while an erase voltage rises to a target level, apply a first voltage to the local word lines after the erase voltage reaches the target level, and apply one or more group voltages to the local word lines after applying the first voltage.

Description

Claims

1. A memory device comprising: a target memory block; anda peripheral circuit configured to float local word lines which are coupled to the target memory block while an erase voltage rises to a target level, apply a first voltage to the local word lines after the erase voltage reaches the target level, and apply one or more group voltages to the local word lines after applying the first voltage.

2. The memory device according to claim 1, wherein the first voltage is higher than each of the one or more group voltages.

3. The memory device according to claim 1, wherein the peripheral circuit floats the local word lines by applying a second voltage as a block select signal corresponding to the target memory block, and applying a third voltage to global word lines which are configured to be coupled to the local word lines in response to the block select signal.

4. The memory device according to claim 3, wherein the second voltage is lower than the third voltage.

5. The memory device according to claim 3, wherein the first voltage is lower than the second voltage and the third voltage.

6. The memory device according to claim 1, wherein the peripheral circuit applies the one or more group voltages to respective local word line groups, into which the local word lines are grouped.

7. The memory device according to claim 1, wherein the peripheral circuit is further configured to float, when floating the local word lines, local select lines which are coupled to the target memory block.

8. The memory device according to claim 7, wherein the peripheral circuit is further configured to keep the local select lines floated during the applying of the first voltage and the one or more group voltages.

9. A memory device comprising: a voltage supply circuit configured to supply one or more group voltages and a first voltage; anda decoder configured to, while performing an erase operation on a target memory block: apply the first voltage to local word lines which are coupled to the target memory block, and apply the one or more group voltages to the local word lines after applying the first voltage.

10. The memory device according to claim 9, wherein the voltage supply circuit is further configured to apply, during the erase operation, an erase voltage to a source line of the target memory block before applying the first voltage, andwherein the local word lines are floated during a rising period of the erase voltage.

11. The memory device according to claim 9, wherein the first voltage is higher than the one or more group voltages.

12. A method for operating a memory device, comprising: floating local word lines which are coupled to a target memory block, during a rising period of an erase voltage;applying a first voltage to the local word lines after the rising period; andapplying one or more group voltages to the local word lines after applying the first voltage.

13. The method according to claim 12, wherein the first voltage is higher than the one or more group voltages.

14. The method according to claim 12, wherein the floating of the local word lines comprises: applying a second voltage as a block select signal corresponding to the target memory block; andapplying a third voltage to global word lines which are configured to be coupled to the local word lines in response to the block select signal.

15. The method according to claim 14, wherein the second voltage is lower than the third voltage.

16. The method according to claim 14, wherein the first voltage is lower than the second voltage and the third voltage.

17. The method according to claim 12, wherein the one or more group voltages are applied to respective local word line groups, into which the local word lines are grouped.

18. The method according to claim 12, further comprising: floating, during the floating of the local word lines, local select lines which are coupled to the target memory block; and,keeping the local select lines floated during the applying of the first voltage and the one or more group voltages.