Patent Grant
11031401
The present invention relates to semiconductor memory technology. More specifically, the present invention relates to a semiconductor memory device comprising of an electrically floating body transistor.
Semiconductor memory devices are used extensively to store data. Memory devices can be characterized according to two general types: volatile and non-volatile. Volatile memory devices such as static random access memory (SRAM) and dynamic random access memory (DRAM) lose data that is stored therein when power is not continuously supplied thereto.
DRAM based on the electrically floating body effect has been proposed, both on silicon on insulator (SOI) substrate (see for example “A Capacitor-less 1T-DRAM Cell”, S. Okhonin et al., pp. 85-87, IEEE Electron Device Letters, vol. 23, no. 2, February 2002 (“Okhonin”) and “Memory Design Using One-Transistor Gain Cell on SOI”, T. Ohsawa et al., pp. 152-153, Tech. Digest, 2002 IEEE International Solid-State Circuits Conference, February 2002 (“Ohsawa”), which are hereby incorporated herein, in their entireties, by reference thereto) and on bulk silicon substrate (see, for example, “Further Insight Into the Physics and Modeling of Floating-Body Capacitorless DRAMs”, A. Villaret et al., pp. 2447-2454, IEEE Transactions on Electron Devices, vol. 52, no. 11, November 2005 (“Villaret”), “Scaled 1T-Bulk Devices Built with CMOS 90 nm Technology for Low-cost eDRAM Applications”, R. Ranica, et al., pp. 38-41, Tech. Digest, Symposium on VLSI Technology, 2005 (“Ranica”), and “Simulation of Intrinsic Bipolar Transistor Mechanisms for future capacitor-less eDRAM on bulk substrate”, R. Pulicani et al., pp. 966-969, 2010 17th IEEE International Conference on Electronics, Circuits, and Systems, December 2010 (“Pulicani”), which are hereby incorporated herein, in their entireties, by reference thereto). Such memory eliminates the capacitor used in the conventional 1T/1C memory cell, and thus is easier to scale to smaller feature size. In addition, such memory allows for a smaller cell size compared to the conventional 1T/1C memory cell. Similar to the 1T/1C DRAM memory cell, the floating body DRAM memory cell only has one stable state in a memory cell, and thus requires periodic refresh operations to restore the state of the memory cell.
A bi-stable floating body memory cell, where more than one stable state exists for each memory cell, has been described in U.S. Patent Application Publication No. 2010/00246284 to Widj aj a et al., titled “Semiconductor Memory Having Floating Body Transistor and Method of Operating” (“Widjaja-1”) and U.S. Patent Application Publication No. 2010/0034041, “Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle” (“Widjaja-2”), which are both hereby incorporated herein, in their entireties, by reference thereto.
Previous disclosures on floating body memory cell formed on bulk silicon substrate requires a buried well layer and insulating layers to isolate a floating body region.
In one aspect of the present invention, a semiconductor memory cell includes: a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; a first region in electrical contact with the floating body region; a second region in electrical contact with said floating body region and spaced apart from the first region; a gate positioned between the first and second regions; a first insulating region located above the floating body region; second insulating regions adjacent to the floating body region; a buried layer region located below the floating body region and the second insulating regions and spaced from the second insulating regions so as not to contact the second insulating regions, wherein the floating body region is bounded by the first insulating region above the floating body region, the second insulating regions adjacent to the floating body region, and a depletion region formed as a result of an application of a back bias to the buried layer region.
In at least one embodiment, the semiconductor memory cell further comprises a substrate region, wherein the buried layer region is positioned between the substrate region and the floating body region.
In at least one embodiment, the first region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; the second region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; the floating body region has a second conductivity type selected from a p-type conductivity type and an n-type conductivity type and different from the first conductivity type; and the buried layer region has the first conductivity type.
In at least one embodiment, the back bias is applied to the buried layer region as a constant positive voltage bias or pulsed positive bias.
In at least one embodiment, the buried layer region is configured to inject charge into or extract charge out of the floating body region to maintain the state of the memory cell.
In at least one embodiment, the floating body region, the first region, the second region, the gate, the first insulating region, the second insulating regions and the buried layer form a memory device, and the semiconductor memory cell further comprises an access transistor connected in series with the memory device.
In another aspect of the present invention, a semiconductor memory cell includes: a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; a gate positioned between the first and second regions; a first insulating region located above the floating body region; second insulating regions adjacent to the floating body region; a buried layer region located below the floating body region and the second insulating regions and spaced from the second insulating regions so as not to contact the second insulating regions, wherein the floating body region is bounded by the first insulating region above the floating body region, the second insulating regions adjacent to the floating body region, and a top boundary of depletion region formed to the buried layer region as a result of an application of a back bias, and wherein application of the back bias results in at least two stable floating body charge levels.
In at least one embodiment, the semiconductor memory cell further includes a substrate region, wherein the buried layer region is positioned between the substrate region and the floating body region.
In at least one embodiment, the first region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; the second region has the first conductivity type; the floating body region has a second conductivity type selected from a p-type conductivity type and an n-type conductivity type and different from the first conductivity type; and the buried layer region has the first conductivity type.
In at least one embodiment, the back bias is applied to the buried layer region as a constant positive voltage bias or pulsed positive voltage.
In at least one embodiment, the buried layer region is configured to inject charge into or extract charge out of the floating body region to maintain the state of the memory cell.
In at least one embodiment, the floating body region, the first region, the second region, the gate, the first insulating region, the second insulating regions and the buried layer form a memory device, and the semiconductor memory cell further includes an access transistor connected in series with the memory device.
In another aspect of the present invention, a semiconductor memory array includes at least two memory cells, wherein each memory cell includes: a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; a gate positioned between the first and second regions; a first insulating region located above the floating body region; second insulating regions adjacent to the floating body region; a buried layer region located below the floating body region and the second insulating regions, wherein at least one of the second insulating regions adjacent to the floating body region insulates the memory cell from an adjacent memory cell.
In at least one embodiment, the semiconductor memory cells each further include a substrate region, wherein the buried layer region is positioned between the substrate region and the floating body region.
In at least one embodiment, the first region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; the second region has the first conductivity type; the floating body region has a second conductivity type selected from a p-type conductivity type and an n-type conductivity type and different from the first conductivity type; and the buried layer region has the first conductivity type.
In at least one embodiment, the back bias is applied to the buried layer region as a constant positive voltage bias or pulsed positive voltage.
In at least one embodiment, the buried layer region is configured to inject charge into or extract charge out of the floating body region to maintain the state of the memory cell.
In at least one embodiment, the floating body region, the first region, the second region, the gate, the first insulating region, the second insulating regions and the buried layer form a memory device, and the semiconductor memory cell further comprises an access transistor connected in series with the memory device.
In another aspect of the present invention, a floating body memory cell is formed on bulk silicon substrate (or other semiconductor materials) which is isolated by a depletion region formed through application of a bias condition on a back bias region.
These and other features of the invention will become apparent to those persons skilled in the art upon reading the details of the devices and methods as more fully described below.
Before the present devices and methods are described, it is to be understood that this invention is not limited to particular embodiments described, as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting, since the scope of the present invention will be limited only by the appended claims.
Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limits of that range is also specifically disclosed. Each smaller range between any stated value or intervening value in a stated range and any other stated or intervening value in that stated range is encompassed within the invention. The upper and lower limits of these smaller ranges may independently be included or excluded in the range, and each range where either, neither or both limits are included in the smaller ranges is also encompassed within the invention, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included in the invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although any methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention, the preferred methods and materials are now described. All publications mentioned herein are incorporated herein by reference to disclose and describe the methods and/or materials in connection with which the publications are cited.
It must be noted that as used herein and in the appended claims, the singular forms “a”, “an”, and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a memory cell” includes a plurality of such memory cells and reference to “the region” includes reference to one or more regions and equivalents thereof known to those skilled in the art, and so forth.
The publications discussed herein are provided solely for their disclosure prior to the filing date of the present application. The dates of publication provided may be different from the actual publication dates which may need to be independently confirmed.
A schematic cross-sectional view of a memory device 50, according to an embodiment of the present invention, is shown in
Memory cell 50 also comprises a buried layer region 22 of a second conductivity type, such as n-type, for example; a floating body region 24 of the first conductivity type, such as p-type, for example; and source/drain regions 16 and 18 of the second conductivity type, such as n-type, for example. Buried layer 22 may be formed by an ion implantation process on the material of substrate 12. Alternatively, buried layer 22 can be grown epitaxially on top of substrate 12.
The floating body region 24 of the first conductivity is bounded on top by surface 14, source line region 16, drain region 18, and insulating layer 62, and on the bottom by buried layer 22. Floating body 24 may be the portion of the original substrate 12 above buried layer 22 if buried layer 22 is implanted. Alternatively, floating body 24 may be epitaxially grown. Depending on how buried layer 22 and floating body 24 are formed, floating body 24 may have the same doping as substrate 12 in some embodiments or a different doping, if desired in other embodiments.
A source line region 16 having a second conductivity type, such as n-type, for example, is provided in floating body region 24, so as to bound a portion of the top of the floating body region in a manner discussed above, and is exposed at surface 14. Source line region 16 may be formed by an implantation process on the material making up substrate 12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion or a selective epitaxial growth process could be used to form source line region 16.
A bit line region 18 having a second conductivity type, such as n-type, for example, is also provided in floating body region 24, so as to bound a portion of the top of the floating body region in a manner discussed above, and is exposed at cell surface 14. Bit line region 18 may be formed by an implantation process on the material making up substrate 12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion or a selective epitaxial growth process could be used to form bit line region 18.
A gate 60 is positioned in between the source line region 16 and the drain region 18, above the floating body region 24. The gate 60 is insulated from the floating body region 24 by an insulating layer 62. Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate 60 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and/or their nitrides.
Insulating layers 26 (like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example, though other insulating materials may be used. The bottom of insulating layer 26 may reside inside the buried region 22 allowing buried region 22 to be continuous as shown in
Memory cell 50 may comprise the regions 17 and 19 of the first conductivity type. The regions 17 and 19 of the first conductivity type can be pocket region as shown in
Cell 50 includes several terminals: word line (WL) terminal 70 electrically connected to gate 60, bit line (BL) terminal 74 electrically connected to bit line region 18, source line (SL) terminal 72 electrically connected to source line region 16, buried well (BW) terminal 76 electrically connected to buried layer 22, and substrate terminal 78 electrically connected to the substrate 12. The doping concentration of the halo region 17 and/or 19 is such that the built-in electric field potential between the halo region 17 and the source region 16 and/or between the halo region 19 and the drain region 18 is high enough to result in lower potential for band-to-band tunneling across the halo region and the source/drain region. To harness the lower potential for band-to-band tunneling, the doping concentration of the first conductivity type region 17 and/or 19 should be high, and is preferentially greater than 5×1018 but not to exceed 5×1019/cm3.
Several operations can be performed by memory cell 50 such as holding, read, write logic-1 and write logic-0 operations, and have been described for example in U.S. Patent Application Publication No. 2010/00246284 to Widjaja et al., titled “Semiconductor Memory Having Floating Body Transistor and Method of Operating” (“Widjaja-1”) and U.S. Patent Application Publication No. 2010/0034041, “Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle” (“Widjaja-2”), which are both hereby incorporated herein, in their entireties, by reference thereto. In prior art, the lower limit of the drain region 18 voltage for writing logic-1 operation using impact ionization is approximately 1.2 V, greater than the band-gap of silicon semiconductor. However, due to the inherent energy band-bending, the write logic-1 voltage of the memory cell 50 can be scaled to a voltage less than 1.2V through the formation of high concentration halo region 17 and/or 19, where band-to-band tunneling is intrinsically present at low voltage of the drain region 18.
The unselected BL terminals 74 are at 0.0 volts, the unselected SL terminals 72 are at 0.0 volts, the unselected WL terminals 70 are at +0.4 volts, about +1.2 volts is applied to the unselected BW terminals 76, and about 0.0 volts is applied to the unselected substrate terminals 78. However, these voltage levels may vary while maintaining the relative relationships between voltage levels as generally described above.
Memory cell 150 includes a substrate 12 of a first conductivity type such as p-type, for example. Substrate 12 is typically made of silicon, but may additionally or alternatively comprise, for example, germanium, silicon germanium, gallium arsenide, carbon nanotubes, and/or other semiconductor materials. In some embodiments of the invention, substrate 12 can be the bulk material of the semiconductor wafer.
Memory cell 150 also comprises a buried layer region 22 of a second conductivity type, such as n-type, for example, and a floating body region 24 of the first conductivity type, such as p-type, for example. Buried layer 22 may be formed by an ion implantation process on the material of substrate 12. Alternatively, buried layer 22 can be grown epitaxially on top of substrate 12.
The floating body region 24 of the first conductivity type is bounded on top by channel region 23, source line region 16, and drain region 18, and on the bottom by buried layer 22. Floating body 24 may be the portion of the original substrate 12 above buried layer 22 if buried layer 22 is implanted. Alternatively, floating body 24 may be epitaxially grown. Depending on how buried layer 22 and floating body 24 are formed, floating body 24 may have the same doping as substrate 12 in some embodiments or a different doping, if desired in other embodiments.
A gate 60 is positioned in between the source line region 16 and the drain region 18, above the channel region 23. The gate 60 is insulated from the floating body region 24 by an insulating layer 62. Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate 60 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides, where the gate electrode 60 has a high work function. Also, high work function gate materials such as valence-band edge metal or p-type polysilicon may be used to form the gate 60. The high work function of the gate electrode 60 will fully deplete the majority carrier of the channel region 23 near the surface when zero voltage is applied to the gate electrode 60, turning off the conduction path between the source region 16 and the drain region 18.
Insulating layers 26 (like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example, though other insulating materials may be used. The bottom of insulating layer 26 may reside inside the buried region 22 allowing buried region 22 to be continuous as shown in
Cell 150 includes several terminals: word line (WL) terminal 70 electrically connected to gate 60, bit line (BL) terminal 74 electrically connected to bit line region 18, source line (SL) terminal 72 electrically connected to source line region 16, buried well (BW) terminal 76 electrically connected to buried layer 22, and substrate terminal 78 electrically connected to the substrate 12. The states of the memory cell 150 are determined from the charge stored in the floating body region 24. If the floating body region 24 is positively charged, the conductivity of the memory cell 150 (for example the current flow from the BL terminal 74 to the SL terminal 72) will be higher than if the floating body region is neutral. The high conductivity state will be referred to as the logic-1 state, while the low conductivity state will be referred to as the logic-0 state._The same operations performed on memory cell 50 can be performed on memory cell 150 such as holding, read, write logic-1 and write logic-0 operations. The drain voltage applied during write logic-1 state using impact ionization mechanism can be reduced on junctionless memory cell transistor 150, because of the higher impact ionization generation on junctionless transistor, for example as described in “Low subthreshold slope in junctionless multi gate transistors”, C.-W. Lee et al., pp. 102106, Applied Physics Letter 96, 2010 (“Lee”), which is hereby incorporated herein, in its entirety, by reference thereto. In one particular non-limiting embodiment, about +1.0 volts is applied to the selected BL terminal 74a, about 0.0 volts is applied to the selected SL terminal 72a, about 0.0 volts is applied to the selected WL terminal 70a, about +1.2 volts is applied to BW terminal 76a, and about 0.0 volts is applied to terminal 78a. The unselected BL terminals 74 are at 0.0 volts, the unselected SL terminals 72 are at 0.0 volts, the unselected WL terminals 70 are at 0.0 volts, about +1.2 volts is applied to the unselected BW terminals 76, and about 0.0 volts is applied to the unselected substrate terminals 78. However, these voltage levels may vary while maintaining the relative relationships between voltage levels as generally described above.
A gate 60 is positioned in between the source line region 16 and the drain region 18, but does not fully overlay the floating body region 24, where the gate region 60 is spaced from the source region 16, forming the gap region 25, for example as described in U.S. patent application Ser. No. 13/244,899 to Y. Widjaja, titled “Asymmetric Semiconductor Memory Device Having Electrically Floating Body Transistor” (“Widjaja-3”), which is hereby incorporated herein, in its entirety, by reference thereto.
Insulating layers 26 (like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example, though other insulating materials may be used. The bottom of insulating layer 26 may reside inside the buried region 22 allowing buried region 22 to be continuous as shown in
Cell 250 includes several terminals: word line (WL) terminal 70 electrically connected to gate 60, bit line (BL) terminal 74 electrically connected to bit line region 18, source line (SL) terminal 72 electrically connected to source line region 16, buried well (BW) terminal 76 electrically connected to buried layer 22, and substrate terminal 78 electrically connected to the substrate 12.
Memory cell 250 conduction utilizes channel length modulation through the gate 60, as described for example in “Impact Ionization MOS (I-MOS)—Part I: Device and Circuit Simulations”, K. Gopalakrishnan, et al., pp. 69-76, IEEE Transactions on Electron Devices, vol. 52, no. 1, January 2005 (“Gopalakrishnan”), which is hereby incorporated herein, in its entirety, by reference thereto. At low gate bias, no inversion is formed in the channel area underneath the gate 60. As the potential of the gate 60 is increased, an inversion layer forms underneath the gate 60. A strong electric field is developed across the gap region 25, sufficient to generate impact ionization.
The states of the memory cell 250 are determined from the charge stored in the floating body region 24. If the floating body region 24 is positively charged, the gate voltage where an inversion layer is formed under the gate 60 (often referred to as the threshold voltage), is lower than that if the floating body region 24 is neutral. The memory state having a lower threshold voltage will be referred to as the logic-1 state, while the memory state having a higher threshold voltage will be referred to as the logic-0 state.
In many, but not necessarily all, of the figures where array 280 appears, representative memory cell 250a will be representative of a “selected” memory cell 250 when the operation being described has one (or more in some embodiments) selected memory cells 250. In such figures, representative memory cell 250b will be representative of an unselected memory cell 250 sharing the same row as selected representative memory cell 250a, representative memory cell 250c will be representative of an unselected memory cell 250 sharing the same column as selected representative memory cell 250a, and representative memory cell 250d will be representative of a memory cell 250 sharing neither a row nor a column with selected representative memory cell 250a.
Present in
Each of the source lines 72a through 72n is associated with a single row of memory cells 250 and is coupled to the source line region 16 of each memory cell 250 in that row. Each of the bit lines 74a through 74p is associated with a single column of memory cells 250 and is coupled to the bit line region 18 of each memory cell 250 in that column.
Several operations can be performed on memory cell 250 such as holding, read, write logic-1 and write logic-0 operations.
In one embodiment the bias conditions for the holding operation on memory cell 250 are: about 0.0 volts is applied to WL terminal 70, about 0.0 volts is applied to BL terminal 74, about +0.4 volts is applied to SL terminal 72, a positive voltage, for example, about +1.0 volts is applied to BW terminal 76, and about 0.0 volts is applied to the substrate terminal 78. In other embodiments, different voltages may be applied to the various terminals of memory cell 250 and the exemplary voltages described are not limiting.
The region where the product β×(M−1) approaches 1 and is characterized by hole current moving into the floating body region is similar to the reverse base current region that has been described for example in “A New Static Memory Cell Based on Reverse Base Current (RBC) Effect of Bipolar Transistor”, K. Sakui et al., pp. 44-47, International Electron Devices Meeting, 1988 (“Sakui-1”), “A New Static Memory Cell Based on the Reverse Base Current Effect of Bipolar Transistors”, K. Sakui et al., pp. 1215-1217, IEEE Transactions on Electron Devices, vol. 36, no. 6, June 1989 (“Sakui-2”), “On Bistable Behavior and Open-Base Breakdown of Bipolar Transistors in the Avalanche Regime—Modeling and Applications”, M. Reisch, pp. 1398-1409, IEEE Transactions on Electron Devices, vol. 39, no. 6, June 1992 (“Reisch”), which are hereby incorporated herein, in their entireties, by reference thereto.
The latching behavior based on the reverse base current region has also been described in a biristor (i.e. bi-stable resistor) for example in “Bistable resistor (Biristor)—Gateless Silicon Nanowire Memory”, J.-W. Han and Y.-K. Choi, pp. 171-172, 2010 Symposium on VLSI Technology, Digest of Technical Papers, 2010 “(“J.-W., Han”), which is hereby incorporated herein, in its entirety, by reference thereto. In a two-terminal biristor device, a refresh operation is still required. J.-W. Han describes a 200 ms data retention for the silicon nanowire biristor memory. As will be described, the holding operation does not require any interruptions to the memory cell 250 access. As a result, the holding operation can be performed for as long as a positive bias is applied to the buried well region 22 through BW terminal 76.
If floating body 24 is neutrally charged, a state corresponding to logic-0, no (or low) electron flow will occur from the drain region 18 to the buried well region 22. As a result, no impact ionization occurs and memory cells in the logic-0 state will remain in the logic-0 state.
In the holding operation described with regards to
The holding operation results in the floating body memory cell having two stable states: the logic-0 state and the logic-1 state separated by an energy barrier, which are represented by VFB0, VFB1, and YTS, respectively.
The values of the floating body 24 potential where the current changes direction, i.e. VFB0, VFB1, and VTS, can be modulated by the potential applied to the BW terminal 76. These values are also temperature dependent.
The holding/standby operation also results in a larger memory window by increasing the amount of charge that can be stored in the floating body 24. Without the holding/standby operation, the maximum potential that can be stored in the floating body 24 is limited to the flat band voltage VFB as the junction leakage current to regions 16 and 18 increases exponentially at floating body potential greater than VFB. However, by applying a positive voltage to substrate terminal 78, the bipolar action results in a hole current flowing into the floating body 24, compensating for the junction leakage current between floating body 24 and regions 16 and 18. As a result, the maximum charge VMC stored in floating body 24 can be increased by applying a positive bias to the substrate terminal 78 as shown in
Floating body DRAM cells described in Ranica-1, Ranica-2, Villaret, and Pulicani only exhibit one stable state, which is often assigned as logic-0 state. Villaret describes the intrinsic bipolar transistors enhance the data retention of logic-1 state, by drawing the electrons which otherwise would recombine with the holes stored in the floating body region. However, only one stable state is observed because there is no hole injection into the floating body region to compensate for the charge leakage and recombination.
The charge stored in the floating body region 24 will modulate the threshold gate voltage to form an inversion layer in the channel region underneath the gate. The gate voltage during the read operation is selected such that inversion layer is formed when the memory cell 250 is in logic-1 state (i.e. when the floating body region 24 is positively charged) and no inversion layer is formed when the memory cell 250 is in logic-0 state (i.e. when the floating body region 24 is neutral). As Gopalakrishnan describes, memory cell 250 has a steep subthreshold slope, resulting in low leakage current from the unselected cells. As a result, the sensing operation of the state of the memory cell 250 may be performed faster.
In one particular non-limiting embodiment, about +0.4 volts is applied to the selected WL terminal 70a, about +1.0 volts is applied to the selected BL terminal 74a, about +0.4 volts is applied to the selected SL terminal 72a, about +1.0 volts is applied to the selected BW terminal 76a, and about 0.0 volts is applied to the selected substrate terminal 78a. However, these voltage levels may vary while maintaining the relative relationships between voltage levels as generally described above.
Removing the slight positive voltage that is applied to the selected SL terminal 72 removes the potential well that allows for positive charge storage in the floating body region 24. As a result, holes will be evacuated from the floating body region 24 and will flow to the source region 16.
In one particular non-limiting embodiment, about 0.0 volts is applied to the selected WL terminal 70a, about 0.0 volts is applied to the selected BL terminal 74a, about 0.0 volts is applied to the selected SL terminal 72a, about 0.0 volts is applied to the selected BW terminal 76a, and about 0.0 volts is applied to the selected substrate terminal 78a. However, these voltage levels may vary while maintaining the relative relationships between voltage levels as generally described above.
The positive voltage applied to the gate 60 of the memory cell 250 has to be sufficiently high to create an inversion layer underneath the gate 60, regardless of the state of the memory cell 250. This will result in an inversion layer at the same potential level as the voltage that is applied to the bit line region 18. Hence, a strong electric field will be developed across the gap region 25, which results in hole injection into the floating body region 24 as a result of impact ionization.
In one particular non-limiting embodiment, about +1.0 volts is applied to the selected WL terminal 70a, about +1.8 volts is applied to the selected BL terminal 74a, about +0.4 volts is applied to the selected SL terminal 72a, about +1.0 volts is applied to the selected BW terminal 76a, and about 0.0 volts is applied to the selected substrate terminal 78a. However, these voltage levels may vary while maintaining the relative relationships between voltage levels as generally described above.
The negative-voltage on the gate 60 (connected to WL terminal 70) and the positive voltage on bit line region 18 (connected to BL terminal 74) create a strong electric field (for example, about 106 V/cm in silicon, as described in Sze, p. 104) between the bit line region 18 and the floating body region 24 in the proximity of gate 60. This bends the energy band sharply upward near the gate and bit line junction overlap region, causing electrons to tunnel from the valence band to the conduction band, leaving holes in the valence band. The electrons which tunnel across the energy band become the drain leakage current, while the holes are injected into floating body region 24 and become the hole charge that creates the logic-1 state.
In one particular non-limiting embodiment, about −1.0 volts is applied to the selected WL terminal 70a, about +1.0 volts is applied to the selected BL terminal 74a, about +0.4 volts is applied to the selected SL terminal 72a, about +1.0 volts is applied to the selected BW terminal 76a, and about 0.0 volts is applied to the selected substrate terminal 78a. However, these voltage levels may vary while maintaining the relative relationships between voltage levels as generally described above.
A schematic cross-sectional view of a memory device 350 according to another embodiment of the present invention is shown in
Memory cell 350 also comprises a buried layer region 22 of a second conductivity type, such as n-type, for example; a floating body region 24 of the first conductivity type, such as p-type, for example; and source/drain regions 16 and 18 of the second conductivity type, such as n-type, for example.
Buried layer 22 may be formed by an ion implantation process on the material of substrate 12. Alternatively, buried layer 22 can also be grown epitaxially on top of substrate 12.
The floating body region 24 of the first conductivity type is bounded on top by surface 14, source line region 16, drain region 18, and insulating layer 62. Floating body 24 may be the portion of the original substrate 12 above buried layer 22 if buried layer 22 is implanted. Alternatively, floating body 24 may be epitaxially grown. Depending on how buried layer 22 and floating body 24 are formed, floating body 24 may have the same doping as substrate 12 in some embodiments or a different doping, if desired in other embodiments.
A source line region 16 having a second conductivity type, such as n-type, for example, is provided in floating body region 24, so as to bound a portion of the top of the floating body region in a manner discussed above, and is exposed at surface 14. Source line region 16 may be formed by an implantation process on the material making up substrate 12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion or a selective epitaxial growth process could be used to form source line region 16.
A bit line region 18 having a second conductivity type, such as n-type, for example, is also provided in floating body region 24, so as to bound a portion of the top of the floating body region in a manner discussed above, and is exposed at cell surface 14. Bit line region 18 may be formed by an implantation process on the material making up substrate 12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion or a selective epitaxial growth process could be used to form bit line region 18.
A gate 60 is positioned in between the source line region 16 and the drain region 18, above the floating body region 24. The gate 60 is insulated from the floating body region 24 by an insulating layer 62. Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate 60 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and/or their nitrides.
Insulating layers 26 (like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example, though other insulating materials may be used. The bottom of insulating layer 26 resides above the buried layer region 22. As can be seen in
Cell 350 includes several terminals: word line (WL) terminal 70 electrically connected to gate 60, bit line (BL) terminal 74 electrically connected to bit line region 18, source line (SL) terminal 72 electrically connected to source line region 16, buried well (BW) terminal 76 electrically connected to buried layer 22, and substrate terminal 78 electrically connected to the substrate 12.
In one embodiment, the bias conditions applied to the memory cell 350 (e.g., to establish the depletion region, as well as to establish a holding condition as described in the Widjaja references incorporated herein) are: about 0V is applied to the WL terminal 70, SL terminal 72, BL terminal 74, substrate terminal 78, and about +3.0V is applied to the BW terminal 76. These example bias conditions are provided for an n-type memory cell 350 (where the source region 16 and drain region 18 are of n-type conductivity, the floating body region 24 is of p-type conductivity, the buried layer region 22 is of n-type conductivity, and the substrate region 12 is of p-type conductivity). In other embodiments, different voltages may be applied to the various terminals of memory cell 350 and the exemplary voltages described are not limiting.
The operation of the memory cell 350 as a capacitorless DRAM has been described in Okhonin, Ohsawa, Villaret, Ranica, and Pulicani, while a holding operation to form a bi-stable memory cell, analogous to an SRAM cell, has been described in Widjaja-1 and Widjaja-2. A write logic-0 operation according to another embodiment of the present invention may be performed by removing the potential applied to the buried layer region 22. The removal of the back bias to the buried layer region 22 will in turn result in the removal of the depletion region 23, causing any charges stored in the floating region 24 to be removed, either through charge sharing to adjacent memory cells 350, or to the substrate 12. This write logic-0 operation is performed in parallel to all the cells connected to the same BW terminal 76. A parallel write logic-0 operation may also be used to accelerate the testing of the memory device. In order to write arbitrary binary data to different memory cells 350, a write logic-0 operation is first performed on all the memory cells to be written, followed by one or more write logic-1 operations on the memory cells that must be written to logic-1.
Memory cell 450 comprises a memory device 450M having a buried layer region 22, located below the insulating region 26, similar to the memory cell 350 illustrated in
The drain region 18 of the memory device 450M is connected to the source region 19 of the access device 450A through a conductive element 94. The conductive element 94 may be formed of, but not limited to, tungsten or silicided silicon.
In addition to the SL terminal 72 and BL terminal 74, memory cell 450 also includes word line 1 (WL1) terminal 70, which is electrically connected to the gate 60 of the memory device 450M, word line 2 (WL2) terminal 71, which is electrically connected to the gate 64 of the access transistor 450A, buried well (BW) terminal 76, which is electrically connected to the buried well region 22 of the memory device 450M, and substrate (SUB) terminal 78, which is connected to the substrate region 12.
As illustrated in
A write logic-0 operation according to another embodiment of the present invention may be performed by removing the potential applied to the buried layer region 22. The removal of the back bias to the buried layer region 22 will in turn result in the removal of the depletion region 23, causing any charges stored in the floating region 24 to be removed, either through charge sharing to adjacent memory cells 450, or to the substrate 12. This write logic-0 operation is performed in parallel to all the cells connected to the same BW terminal 76. A parallel write logic-0 operation may also be used to accelerate the testing of the memory device. In order to write arbitrary binary data to different memory cells 450, a write logic-0 operation is first performed on all the memory cells to be written, followed by one or more write logic-1 operations on the memory cells that must be written to logic-1.
This application is a continuation of co-pending U.S. application Ser. No. 16/106,643, filed on Aug. 21, 2018, which is a continuation of U.S. application Ser. No. 15/797,461, filed Oct. 30, 2017, now U.S. Pat. No. 10,103,149, which is a continuation of U.S. application Ser. No. 15/218,287, filed on Jul. 25, 2016, now U.S. Pat. No. 9,831,247; which is a continuation of U.S. application Ser. No. 14/685,827, filed on Apr. 14, 2015, now U.S. Pat. No. 9,431,401; which is a divisional application of U.S. application Ser. No. 14/203,235, filed Mar. 10, 2014, now U.S. Pat. No. 9,029,922, which claims the benefit of U.S. Provisional Application No. 61/775,521, filed Mar. 9, 2013 and U.S. Provisional Application No. 61/816,153, filed Apr. 25, 2013, each of which applications and patents are hereby incorporated herein, in their entireties, by reference thereto.
| Number | Name | Date | Kind |
|---|---|---|---|
| 4300212 | Simko | Nov 1981 | A |
| 4385308 | Uchida | May 1983 | A |
| 4959812 | Momodoni et al. | Sep 1990 | A |
| 5519831 | Holzhammer | May 1996 | A |
| 5581504 | Chang et al. | Dec 1996 | A |
| 5748538 | Lee et al. | May 1998 | A |
| 5767549 | Chen et al. | Jun 1998 | A |
| 5999444 | Fujiwara et al. | Dec 1999 | A |
| 6005818 | Ferrant et al. | Dec 1999 | A |
| 6064100 | Wen | May 2000 | A |
| 6141248 | Forbes et al. | Oct 2000 | A |
| 6163048 | Hirose et al. | Dec 2000 | A |
| 6166407 | Ohta | Dec 2000 | A |
| 6243293 | Van Houdt et al. | Jun 2001 | B1 |
| 6341087 | Kunikiyo et al. | Jan 2002 | B1 |
| 6356485 | Proebsting et al. | Mar 2002 | B1 |
| 6376876 | Shin et al. | Apr 2002 | B1 |
| 6542411 | Tanikawa et al. | Apr 2003 | B2 |
| 6614684 | Shukuri et al. | Sep 2003 | B1 |
| 6625057 | Iwata | Sep 2003 | B2 |
| 6661042 | Hsu | Dec 2003 | B2 |
| 6686624 | Hsu | Feb 2004 | B2 |
| 6724657 | Shukuri et al. | Apr 2004 | B2 |
| 6791882 | Seki et al. | Sep 2004 | B2 |
| 6801452 | Miwa et al. | Oct 2004 | B2 |
| 6845042 | Ichige et al. | Jan 2005 | B2 |
| 6870751 | van Brocklin et al. | Mar 2005 | B2 |
| 6885581 | Nemati et al. | Apr 2005 | B2 |
| 6912150 | Portman et al. | Jun 2005 | B2 |
| 6913964 | Hsu | Jul 2005 | B2 |
| 6925006 | Fazan et al. | Aug 2005 | B2 |
| 6954377 | Choi et al. | Oct 2005 | B2 |
| 6969662 | Fazan et al. | Nov 2005 | B2 |
| 7085156 | Ferrant et al. | Aug 2006 | B2 |
| 7118986 | Steigerwalt et al. | Oct 2006 | B2 |
| 7170807 | Fazan et al. | Jan 2007 | B2 |
| 7209384 | Kim | Apr 2007 | B1 |
| 7224019 | Hieda et al. | May 2007 | B2 |
| 7259420 | Anderson et al. | Aug 2007 | B2 |
| 7259992 | Shirota | Aug 2007 | B2 |
| 7280399 | Fazan et al. | Oct 2007 | B2 |
| 7285820 | Park et al. | Oct 2007 | B2 |
| 7301803 | Okhonin et al. | Nov 2007 | B2 |
| 7301838 | Waller et al. | Nov 2007 | B2 |
| 7329580 | Cho et al. | Feb 2008 | B2 |
| 7440333 | Hsia et al. | Oct 2008 | B2 |
| 7447068 | Tsai et al. | Nov 2008 | B2 |
| 7450423 | Lai et al. | Nov 2008 | B2 |
| 7473611 | Cho et al. | Jan 2009 | B2 |
| 7498630 | Ichige et al. | Mar 2009 | B2 |
| 7504302 | Matthew et al. | Mar 2009 | B2 |
| 7541636 | Ranica et al. | Jun 2009 | B2 |
| 7542345 | Okhonin et al. | Jun 2009 | B2 |
| 7579241 | Hieda et al. | Aug 2009 | B2 |
| 7609551 | Shino et al. | Oct 2009 | B2 |
| 7622761 | Park et al. | Nov 2009 | B2 |
| 7701763 | Roohparvar | Apr 2010 | B2 |
| 7733693 | Ferrant et al. | Jun 2010 | B2 |
| 7759715 | Bhattacharyya | Jul 2010 | B2 |
| 7760548 | Widjaja | Jul 2010 | B2 |
| 7847338 | Widjaja | Dec 2010 | B2 |
| 7933139 | Lung | Apr 2011 | B2 |
| 7933140 | Wang et al. | Apr 2011 | B2 |
| 8014200 | Widjaja | Sep 2011 | B2 |
| 8036033 | Widjaja | Oct 2011 | B2 |
| 8059459 | Widjaja | Nov 2011 | B2 |
| 8077536 | Widjaja | Dec 2011 | B2 |
| 8116130 | Ratnakumar et al. | Feb 2012 | B1 |
| 8130547 | Widjaja et al. | Mar 2012 | B2 |
| 8130548 | Widjaja et al. | Mar 2012 | B2 |
| 8159868 | Widjaja | Apr 2012 | B2 |
| 8159878 | Widjaja | Apr 2012 | B2 |
| 8174886 | Widjaja et al. | May 2012 | B2 |
| 8194451 | Widjaja | Jun 2012 | B2 |
| 8194471 | Widjaja et al. | Jun 2012 | B2 |
| 8208302 | Widjaja | Jun 2012 | B2 |
| 8243499 | Widjaja | Aug 2012 | B2 |
| 8264875 | Widjaja et al. | Sep 2012 | B2 |
| 8264876 | Widjaja et al. | Sep 2012 | B2 |
| 8294193 | Widjaja | Oct 2012 | B2 |
| 8298875 | Or-Bach et al. | Oct 2012 | B1 |
| 8391066 | Widjaja | Mar 2013 | B2 |
| 8472249 | Widjaja | Jun 2013 | B2 |
| 8514622 | Widjaja | Aug 2013 | B2 |
| 8514623 | Widjaja et al. | Aug 2013 | B2 |
| 8531881 | Widjaja | Sep 2013 | B2 |
| 8559257 | Widjaja | Oct 2013 | B2 |
| 8570803 | Widjaja | Oct 2013 | B2 |
| 8582359 | Widjaja | Nov 2013 | B2 |
| 8654583 | Widjaja | Feb 2014 | B2 |
| 8711622 | Widjaja | Apr 2014 | B2 |
| 8767458 | Widjaja | Jul 2014 | B2 |
| 8837247 | Widjaja | Sep 2014 | B2 |
| 8923052 | Widjaja | Dec 2014 | B2 |
| 8934296 | Widjaja | Jan 2015 | B2 |
| 8937834 | Widjaja et al. | Jan 2015 | B2 |
| 8957458 | Widjaja | Feb 2015 | B2 |
| 8995186 | Widjaja | Mar 2015 | B2 |
| 9001581 | Widjaja | Apr 2015 | B2 |
| 9025358 | Widjaja | May 2015 | B2 |
| 9029922 | Han et al. | May 2015 | B2 |
| 9030872 | Widjaja et al. | May 2015 | B2 |
| 9087580 | Widjaja | Jul 2015 | B2 |
| 9153309 | Widjaja et al. | Oct 2015 | B2 |
| 9153333 | Widjaja | Oct 2015 | B2 |
| 9208840 | Widjaja et al. | Dec 2015 | B2 |
| 9208880 | Louie et al. | Dec 2015 | B2 |
| 9209188 | Widjaja | Dec 2015 | B2 |
| 9230651 | Widjaja et al. | Jan 2016 | B2 |
| 9230965 | Widjaja | Jan 2016 | B2 |
| 9236382 | Widjaja et al. | Jan 2016 | B2 |
| 9257179 | Widjaja | Feb 2016 | B2 |
| 9391079 | Widjaja | Jul 2016 | B2 |
| 9401206 | Widjaja | Jul 2016 | B2 |
| 9431401 | Han et al. | Aug 2016 | B2 |
| 9460790 | Widjaja | Oct 2016 | B2 |
| 9484082 | Widjaja | Nov 2016 | B2 |
| 9490012 | Widjaja | Nov 2016 | B2 |
| 9514803 | Widjaja et al. | Dec 2016 | B2 |
| 9524970 | Widjaja | Dec 2016 | B2 |
| 9576962 | Widjaja et al. | Feb 2017 | B2 |
| 9589963 | Widjaja | Mar 2017 | B2 |
| 9601493 | Widjaja | Mar 2017 | B2 |
| 9614080 | Widjaja | Apr 2017 | B2 |
| 9646693 | Widjaja | May 2017 | B2 |
| 9653467 | Widjaja et al. | May 2017 | B2 |
| 9666275 | Widjaja | May 2017 | B2 |
| 9679648 | Widjaja | Jun 2017 | B2 |
| 9704870 | Widjaja | Jul 2017 | B2 |
| 9715932 | Widjaja | Jul 2017 | B2 |
| 9747983 | Widjaja | Aug 2017 | B2 |
| 9761311 | Widjaja | Sep 2017 | B2 |
| 9761589 | Widjaja | Sep 2017 | B2 |
| 9793277 | Widjaja et al. | Oct 2017 | B2 |
| 9812203 | Widjaja | Nov 2017 | B2 |
| 9812456 | Widjaja | Nov 2017 | B2 |
| 9831247 | Han et al. | Nov 2017 | B2 |
| 9847131 | Widjaja | Dec 2017 | B2 |
| 9905564 | Widjaja et al. | Feb 2018 | B2 |
| 9922711 | Widjaja | Mar 2018 | B2 |
| 9922981 | Widjaja | Mar 2018 | B2 |
| 9928910 | Widjaja | Mar 2018 | B2 |
| 9960166 | Widjaja | May 2018 | B2 |
| 9978450 | Widjaja | May 2018 | B2 |
| 10008266 | Widjaja | Jun 2018 | B1 |
| 10026479 | Louie et al. | Jul 2018 | B2 |
| 10032514 | Widjaja | Jul 2018 | B2 |
| 10032776 | Widjaja et al. | Jul 2018 | B2 |
| 10056387 | Widjaja | Aug 2018 | B2 |
| 10074653 | Widjaja | Sep 2018 | B2 |
| 10079236 | Widjaja | Sep 2018 | B2 |
| 10103149 | Han | Oct 2018 | B2 |
| 10109349 | Widjaja | Oct 2018 | B2 |
| 10141315 | Widjaja et al. | Nov 2018 | B2 |
| 10163907 | Widjaja et al. | Dec 2018 | B2 |
| 10181471 | Widjaja et al. | Jan 2019 | B2 |
| 10192872 | Widjaja et al. | Jan 2019 | B2 |
| 10204684 | Widjaja | Feb 2019 | B2 |
| 10204908 | Widjaja | Feb 2019 | B2 |
| 10210934 | Widjaja | Feb 2019 | B2 |
| 10211209 | Widjaja | Feb 2019 | B2 |
| 10242739 | Widjaja | Mar 2019 | B2 |
| 10249368 | Widjaja | Apr 2019 | B2 |
| 10340006 | Widjaja | Jul 2019 | B2 |
| 10340276 | Widjaja et al. | Jul 2019 | B2 |
| 10347636 | Widjaja | Jul 2019 | B2 |
| 10373685 | Louie et al. | Aug 2019 | B2 |
| 10388378 | Widjaja | Aug 2019 | B2 |
| 10403361 | Widjaja | Sep 2019 | B2 |
| 10453847 | Widjaja et al. | Oct 2019 | B2 |
| 10461083 | Han | Oct 2019 | B2 |
| 10461084 | Widjaja | Oct 2019 | B2 |
| 10468102 | Widjaja | Nov 2019 | B2 |
| 20020018366 | von Schwerin et al. | Feb 2002 | A1 |
| 20020048193 | Tanikawa et al. | Apr 2002 | A1 |
| 20050024968 | Lee et al. | Feb 2005 | A1 |
| 20050032313 | Forbes | Feb 2005 | A1 |
| 20050124120 | Du et al. | Jun 2005 | A1 |
| 20060018164 | Wu | Jan 2006 | A1 |
| 20060044915 | Park et al. | Mar 2006 | A1 |
| 20060125010 | Bhattacharyya | Jun 2006 | A1 |
| 20060157679 | Scheuerlein | Jul 2006 | A1 |
| 20060199336 | Kang et al. | Sep 2006 | A1 |
| 20060227601 | Bhattacharyya | Oct 2006 | A1 |
| 20060237770 | Huang et al. | Oct 2006 | A1 |
| 20060278915 | Lee et al. | Dec 2006 | A1 |
| 20070004149 | Tews | Jan 2007 | A1 |
| 20070090443 | Choi et al. | Apr 2007 | A1 |
| 20070164351 | Hamamoto | Jul 2007 | A1 |
| 20070164352 | Padilla | Jul 2007 | A1 |
| 20070210338 | Orlowski | Sep 2007 | A1 |
| 20070215954 | Mouli | Sep 2007 | A1 |
| 20070263466 | Morishita et al. | Nov 2007 | A1 |
| 20070284648 | Park et al. | Dec 2007 | A1 |
| 20080048239 | Huo et al. | Feb 2008 | A1 |
| 20080080248 | Lue et al. | Apr 2008 | A1 |
| 20080111154 | Voldman | May 2008 | A1 |
| 20080123418 | Widjaja | May 2008 | A1 |
| 20080157092 | Arai et al. | Jul 2008 | A1 |
| 20080185646 | Anderson et al. | Aug 2008 | A1 |
| 20080224202 | Young et al. | Sep 2008 | A1 |
| 20080265305 | He et al. | Oct 2008 | A1 |
| 20080303079 | Cho et al. | Dec 2008 | A1 |
| 20090034320 | Ueda | Feb 2009 | A1 |
| 20090065853 | Hanafi | Mar 2009 | A1 |
| 20090081835 | Kim et al. | Mar 2009 | A1 |
| 20090085089 | Chang et al. | Apr 2009 | A1 |
| 20090101975 | Holz et al. | Apr 2009 | A1 |
| 20090108322 | Widjaja | Apr 2009 | A1 |
| 20090108351 | Yang et al. | Apr 2009 | A1 |
| 20090109750 | Widjaja | Apr 2009 | A1 |
| 20090173985 | Lee et al. | Jul 2009 | A1 |
| 20090190402 | Hsu et al. | Jul 2009 | A1 |
| 20090251966 | Widjaja | Oct 2009 | A1 |
| 20090316492 | Widjaja | Dec 2009 | A1 |
| 20100008139 | Bae | Jan 2010 | A1 |
| 20100034041 | Widjaja | Feb 2010 | A1 |
| 20100046287 | Widjaja | Feb 2010 | A1 |
| 20100157664 | Chung | Jun 2010 | A1 |
| 20100246277 | Widjaja et al. | Sep 2010 | A1 |
| 20100246284 | Widjaja et al. | Sep 2010 | A1 |
| 20100290271 | Lung | Nov 2010 | A1 |
| 20110032756 | Widjaja | Feb 2011 | A1 |
| 20110042736 | Widjaja | Feb 2011 | A1 |
| 20110044110 | Widjaja | Feb 2011 | A1 |
| 20110170329 | Kang | Jul 2011 | A1 |
| 20110228591 | Widjaja | Sep 2011 | A1 |
| 20110228617 | Wang et al. | Sep 2011 | A1 |
| 20110305085 | Widjaja | Dec 2011 | A1 |
| 20120012915 | Widjaja et al. | Jan 2012 | A1 |
| 20120014180 | Widjaja | Jan 2012 | A1 |
| 20120014188 | Widjaja et al. | Jan 2012 | A1 |
| 20120069652 | Widjaja | Mar 2012 | A1 |
| 20120081976 | Widjaja et al. | Apr 2012 | A1 |
| 20120106234 | Widjaja | May 2012 | A1 |
| 20120113712 | Widjaja | May 2012 | A1 |
| 20120120752 | Widjaja | May 2012 | A1 |
| 20120217549 | Widjaja | Aug 2012 | A1 |
| 20120230123 | Widjaja et al. | Sep 2012 | A1 |
| 20120241708 | Widjaja | Sep 2012 | A1 |
| 20120281475 | Oh et al. | Nov 2012 | A1 |
| 20130015517 | Widjaja et al. | Jan 2013 | A1 |
| 20130058169 | Lee et al. | Mar 2013 | A1 |
| 20130094280 | Widjaja | Apr 2013 | A1 |
| 20130229857 | Kajigaya | Sep 2013 | A1 |
| 20130250685 | Widjaja | Sep 2013 | A1 |
| 20130264656 | Widjaja et al. | Oct 2013 | A1 |
| 20140036577 | Widjaja | Feb 2014 | A1 |
| 20140159156 | Widjaja | Jun 2014 | A1 |
| 20140160868 | Widjaja et al. | Jun 2014 | A1 |
| 20140198551 | Louie et al. | Jul 2014 | A1 |
| 20140332899 | Widjaja | Nov 2014 | A1 |
| 20140340972 | Widjaja et al. | Nov 2014 | A1 |
| 20140355343 | Widjaja | Dec 2014 | A1 |
| 20150016207 | Louie et al. | Jan 2015 | A1 |
| 20150023105 | Widjaja et al. | Jan 2015 | A1 |
| 20150092486 | Widjaja | Apr 2015 | A1 |
| 20150109860 | Widjaja | Apr 2015 | A1 |
| 20150155284 | Widjaja | Jun 2015 | A1 |
| 20150170743 | Widjaja | Jun 2015 | A1 |
| 20150187776 | Widjaja | Jul 2015 | A1 |
| 20150213892 | Widjaja | Jul 2015 | A1 |
| 20150221650 | Widjaja et al. | Aug 2015 | A1 |
| 20150221653 | Han et al. | Aug 2015 | A1 |
| 20150310917 | Widjaja | Oct 2015 | A1 |
| 20150371707 | Widjaja | Dec 2015 | A1 |
| 20160005741 | Widjaja | Jan 2016 | A1 |
| 20160005750 | Widjaja | Jan 2016 | A1 |
| 20160078921 | Widjaja et al. | Mar 2016 | A1 |
| 20160086655 | Widjaja | Mar 2016 | A1 |
| 20160086954 | Widjaja et al. | Mar 2016 | A1 |
| 20160111158 | Widjaja | Apr 2016 | A1 |
| 20160300613 | Widjaja | Oct 2016 | A1 |
| 20160300841 | Widjaja | Oct 2016 | A1 |
| 20160336326 | Han et al. | Nov 2016 | A1 |
| 20160365444 | Widjaja | Dec 2016 | A1 |
| 20170025534 | Widjaja | Jan 2017 | A1 |
| 20170032842 | Widjaja | Feb 2017 | A1 |
| 20170040326 | Widjaja | Feb 2017 | A1 |
| 20170053919 | Widjaja et al. | Feb 2017 | A1 |
| 20170092359 | Louie et al. | Mar 2017 | A1 |
| 20170092648 | Widjaja | Mar 2017 | A1 |
| 20170125421 | Widjaja et al. | May 2017 | A1 |
| 20170133091 | Widjaja | May 2017 | A1 |
| 20170133382 | Widjaja | May 2017 | A1 |
| 20170154888 | Widjaja | Jun 2017 | A1 |
| 20170169887 | Widjaja | Jun 2017 | A1 |
| 20170213593 | Widjaja | Jul 2017 | A1 |
| 20170221900 | Widjaja et al. | Aug 2017 | A1 |
| 20170229178 | Widjaja | Aug 2017 | A1 |
| 20170229466 | Widjaja et al. | Aug 2017 | A1 |
| 20170271339 | Widjaja | Sep 2017 | A1 |
| 20170294230 | Widjaja | Oct 2017 | A1 |
| 20170365340 | Widjaja | Dec 2017 | A1 |
| 20170365607 | Widjaja | Dec 2017 | A1 |
| 20180012893 | Widjaja et al. | Jan 2018 | A1 |
| 20180025780 | Widjaja | Jan 2018 | A1 |
| 20180047731 | Widjaja | Feb 2018 | A1 |
| 20180069008 | Han et al. | Mar 2018 | A1 |
| 20180075907 | Widjaja | Mar 2018 | A1 |
| 20180122943 | Han et al. | May 2018 | A1 |
| 20180158825 | Widjaja et al. | Jun 2018 | A1 |
| 20180166446 | Widjaja | Jun 2018 | A1 |
| 20180174654 | Widjaja | Jun 2018 | A1 |
| 20180182458 | Widjaja | Jun 2018 | A1 |
| 20180182466 | Widjaja | Jun 2018 | A1 |
| 20180219013 | Widjaja | Aug 2018 | A1 |
| 20180233199 | Widjaja | Aug 2018 | A1 |
| 20180301191 | Widjaja | Oct 2018 | A1 |
| 20180301192 | Louie et al. | Oct 2018 | A1 |
| 20180308848 | Widjaja et al. | Oct 2018 | A1 |
| 20180330790 | Widjaja | Nov 2018 | A1 |
| 20180331109 | Widjaja | Nov 2018 | A1 |
| 20180358360 | Han et al. | Dec 2018 | A1 |
| 20180374854 | Widjaja | Dec 2018 | A1 |
| 20190006367 | Widjaja | Jan 2019 | A1 |
| 20190027220 | Widjaja | Jan 2019 | A1 |
| 20190067289 | Widjaja et al. | Feb 2019 | A1 |
| 20190096889 | Widjaja et al. | Mar 2019 | A1 |
| 20190131305 | Widjaja et al. | May 2019 | A1 |
| 20190139962 | Widjaja | May 2019 | A1 |
| 20190148381 | Widjaja et al. | May 2019 | A1 |
| 20190156889 | Widjaja | May 2019 | A1 |
| 20190156890 | Widjaja | May 2019 | A1 |
| 20190164974 | Widjaja | May 2019 | A1 |
| 20190180820 | Widjaja | Jun 2019 | A1 |
| 20190189212 | Widjaja | Jun 2019 | A1 |
| 20190259763 | Widjaja et al. | Aug 2019 | A1 |
| 20190267089 | Widjaja | Aug 2019 | A1 |
| 20190267382 | Widjaja | Aug 2019 | A1 |
| 20190295646 | Widjaja | Sep 2019 | A1 |
| 20190311769 | Louie et al. | Oct 2019 | A1 |
| 20190355419 | Widjaja | Nov 2019 | A1 |
| Entry |
|---|
| Pulcani et al., “Simulation of intrinsic bipolar transistor mechanisms for future capacitor-less eDRAM on bulk substrate”, Electronics, Circuits and Systems (ICECS), 2010 17th IEEE International Conference on . . . , IEEE, 2010, pp. 966-969. |
| Rodriguez et al., “A-RAM memofy cell: concept and operation”, Electron Device Letters, IEEE, vol. 31, No. 9 (2010), pp. 972-974. |
| Rodriguez et al., “A-RAM Novel capacitor-less DRAM memory”, Intl SOI Conference, 2009 IEEE International . . . , pp. 1-2, IEEE, 2009. |
| Zhang et al., “Total ionizing Dose Effects on FinFET-Based Capacitor-less 1T-DRAMs”, Nuclear Science, IEEE Trnasactions on . . . , vol. 57, No. 6, 2010, pp. 3298-3304. |
| Villaret et al., “Mechanisms of charge modulation in the floating body of triple-well nMOSFET capacitor-less DRAMs”, Microelectronic Engineering 72 (2004) 434-439. |
| Almeida et al., “Comparison between low and high read bias in FB-RAM on UTBOX FDSOI devices”, IEEE, 1978-1-4673-0192-3/12, 2012, pp. 61-64. |
| Andrade et al., “The impact of Back Bias on the Floating Body Effect in UTBOX SOI Devices for 1T-FBRAM Memory Applications”, 2012 8th International Caribbean Conferences on Devices, Circuits and Systems (ICCDCS), IEEE, 2012,, 978-1-4577-1117-6/12/$26.00. |
| Aoulaiche et al., “Hot Hole Induced Damage in 1T-FBRAM on Bulk FinFET”, 978-1-4244-911-7/11/$26.00. IEEE, 2011, pp. 2D.3.1-2D.3.6. |
| Aoulaiche et al., “Junction Field Effect on the Retention Time for One-Transistor Floating-Body RAM”, IEEE Transactions on Electron Devices, vol. 59, No. 8, Aug. 2012, pp. 2167-2172. |
| Avci et al., “Floating-Body Diode—A Novel DRAM Device”, IEEE Electron Device Letters, vol. 33, No. 2, Feb. 2012, pp. 161-163. |
| Cao et al., “A Novel 1T-DRAM Cell for Embedded Application”, IEEE Transactions on Electron Devices, vol. 59, No. 5, May 2012, pp. 1304-1310. |
| Cho et al., “Variation-Aware Study of BJT-based Capacitorless DRAM Cell Scaling Limit”, Silicon Nanoelectronics Workshop (SNW), 2012 IEEE; 978-1-4673-0996-7. |
| Cho et al., “Variation Study and Implications for BJT-BasedThin-Body Capacitorless DRAM”, IEEE Electron Device Letters, vol. 33, No. 3, Mar. 2012, pp. 312-314. |
| Chun et al., “A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches”, IEEE Journal of Solid-State Circuits, vol. 47, No. 2, Feb. 2012, pp. 547-559. |
| Collaert et al., “Substrate bias dependency of sense margin and retention in bulk FinFET 1T-DRAM cells”, Solid-State Electronics 65-66 (2011) 205-210. |
| Galeti et al., “BJT effect analysis in p- and n-SOI MuGFETs with high-k gate dielectrics and TiN metal gate electrode for a 1T-DRAM application”, 978-1-61284-760-3/11/$26.00 © 2011 IEEE. |
| Gamiz et al., “3D Trigate 1T-DRAM memory cell for 2x nm nodes”, 978-1-4673-1081-9/12/$31.00 © 2012 IEEE. |
| Gamiz et al., “A 20nm Low-Power Triple-Gate Multibody 1T-DRAM cell”, 978-1-4577-2084-0/12/$26.00 © 2012 IEEE. |
| Hwang et al., “Offset Buried Metal Gate Vertical Floating Body Memory Technology with Excellent Retention Time for DRAM Application”, 2011 Symposium on VLSI Technology Digest of Technical Papers, pp. 172-173. |
| Kim et al., “Optical Charge-Pumping: A Universal Trap Characterization Technique for Nanoscale Floating Body Devices”, 2011 Symposium on VLSI Technology Digest of Technical Papers, pp. 190-191. |
| Lee et al., “A Novel Capacitorless 1T DRAM Cell for Data Retention Time Improvement”, IEEE Transactions on Nanotechnology, vol. 10, No. 3, May 2011; pp. 462-466. |
| Liu et al., “A three-dimensional DRAM using floating body cell in FDSOI devices”, 978-1-4673-1188-5/12/$31.00 © 2012 IEEE. |
| Lu et al., “A Floating-Body/Gate DRAM Cell Upgraded for Long Retention Time”, IEEE Electron Device Letters, vol. 32, No. 6, Jun. 2011, pp. 731-733. |
| Mahatme et al., “Total Ionizing Dose Effects on Ultra Thin Buried Oxide Floating Body Memories”, 978-1-4577-1680-5/12/$26.00 © 2012 IEEE; pp. MY.3.1-MY.3.5. |
| Moon et al., “Multi-Functional Universal Device using a Band-Engineered Vertical Structure”, 978-1-4577-0505-2/11/$26.00 © 2011 IEEE, pp. 24.6.1-24.6.4. |
| Nicoletti et al., “The Dependence of Retention Time on Gate Length in UTBOX FBRAM With Different Source/Drain Junction Engineering”, IEEE Electron Device Letters, vol. 33, No. 7, Jul. 2012, pp. 940-942. |
| Pulicani et al., “Simulation of Intrinsic Bipolar Transistor Mechanisms for future capacitor-less eDRAM on bulk substrate.” 978-1-4244-8157-6/10/$26.00 2010 IEEE pp. 966-969. |
| Rodriguez et al., “A-RAM: Novel capacitor-less DRAM memory”, 978-1-4244-5232-3/09/$25.00 © 2009 IEEE. |
| Rodriguez et al., “A-RAM Memory Cell: Concept and Operation”, IEEE Electron Device Letters, vol. 31, No. 9, Sep. 2010, pp. 972-974. |
| Rodriguez et al., “Novel Capacitorless 1T-DRAM Cell for 22-nm Node Compatible With Bulk and SOI Substrates”, IEEE Transactions on Electron Devices, vol. 58, No. 8, Aug. 2011, pp. 2371-2377. |
| Romanjek et al., “Compact (Wg/Lg)=80/85 nm FDSOI 1T-DRAM programmed by Meta Stable Dip”, 978-1-4673-0192-3/12/$31.00 © 2012 IEEE, pp. 199-202. |
| Rothemund et al., “The importance of being modular”, 584 | Nature | vol. 485 | May 31, 2012, pp. 584-585. |
| Shim et al., “A BJT-Based Heterostructure 1T-DRAM for Low-Voltage Operation”, IEEE Electron Device Letters, vol. 33, No. 1, Jan. 2012, pp. 14-16. |
| Shin et al., “A Novel Double HBT-Based Capacitorless 1T DRAM Cell With Si/SiGe Heterojunctions”, IEEE Electron Device Letters, vol. 32, No. 7, Jul. 2011, pp. 850-852. |
| Shin et al., “Vertical-Gate Si/SiGe Double-HBT-Based Capacitorless 1T DRAM Cell for Extended Retention Time at Low Latch Voltage”, IEEE Electron Device Letters, vol. 33, No. 2, Feb. 2012, pp. 134-136. |
| Ventrice et al., “Analytical model of deeply-scaled thyristors for memory applications”, Microelectronics and Electron Devices (WMED), 2012 IEEE Workshop on, 978-1-4577-1735-2, pp. 1-4. |
| Wu et al., “Experimental Demonstration of the High-Performance Floating-Body/Gate DRAM Cell for Embedded Memories”, IEEE Electron Device Letters, vol. 33, No. 6, Jun. 2012, pp. 743-745. |
| Zhang et al., “Total Ionizing Dose Effects on FinFET-Based Capacitor-Less 1T-DRAMs”, IEEE Transactions on Nuclear Science, vol. 57, No. 6, Dec. 2010, pp. 3298-3304. |
| Pelizzer et al., “A 90nm Phase Change Memory Technology for Stand-Alone Non-Volatile Memory Applications”, 2006 Symposium on VLSI Technology Digest of Technical Papers, 1-4244-0005-8/06/$20.00 (c) 2006 IEEE. |
| Chatterjee, et al. “Taper isolated dynamic gain RAM cell.” Electron Devices Meeting, 1978 International. vol. 24. IEEE, 1978, pp. 698-699. |
| Chatterjee, et al. Circuit Optimization of the Paper Isolated Dynamic Gain RAM Cell for VLSI Memories, pp. 22-23, 1979. |
| Chatterjee, et al. “A survey of high-density dynamic RAM cell concepts.” Electron Devices, IEEE Transactions on 26.6 (1979): 827-839. |
| Erb, D. “Stratified charge memory.” Solid-State Circuits Conference. Digest of Technical Papers. 1978 IEEE International. vol. 21. IEEE, 1978, pp. 24-25. |
| Lanyon et al., “Bandgap Narrowing in Moderately to Heavily Doped Silicon”, pp. 1014-1018, No. 7, vol. ED-26, 1979 IEEE. |
| Leiss, et al, “dRAM Design Using the Taper-Isolated Dynamic RAM Cell.” Solid-State Circuits, IEEE Journal of 17.2 (1982): 337-344. |
| Lin et al., “A new 1T DRAM Cell with enhanced Floating Body Effect”, pp. 1-5, Proceedings of the 2006 IEEE International Workshop on Memory Technology. |
| Ohsawa et al., “Autonomous refresh of floating body cell (FBC)”, Electron Devices Meeting, 2008. IEDM 2008. IEEE International. IEEE 2008, pp. 801-804. |
| Oh et al., “A 4-Bit Double SONOS memory (DSM) with 4 Storage Nodes Per Cell for Ultimate Multi-Bit Operation”, pp. 1-2, 2006 Symposium on VLSI Technology Digest of Technical Papers. |
| Ranica, et al. “A one transistor cell on bulk substrate (1T-Bulk) for low-cost and high density eDRAM.” VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on. IEEE, 2004, pp. 128-129. |
| Ranica, et al. “Scaled IT-Bulk devices built with CMOS 90nm technology for low-cost eDRAM applications.” VLSI Technology, 2005. Digest of Technical Papers. 2005 Symposium on. IEEE, 2005, pp. 38-39. |
| Reisch, “On bistable behavior and open-base breakdown of bipolar transistors in the avalanche regime-modeling and applications.” Electron Devices, IEEE Transactions on 39.6 (1992): 1398-1409. |
| Sakui et al., “A new static memory cell based on reverse bias current (RBC) effect of bipolar transistor”, Electron Devices Meeting, 1988. IEDM'88. Technical Digest, International IEEE, 1988, pp. 44-47. |
| Sakui et al., “A new static memory cell based on the reverse bias current effect of bipolar transistors”, Electron Devices, IEEE Transactions on 36.6 (1989): 1215-1217. |
| Sze et al., “Physics of Semiconductor Devices”, Wiley-Interscience, 2007, p. 104. |
| Terada et al., “A new VLSI memory cell using capacitance coupling (CC) cell”, Electron Devices, IEEE Transactions on 31.9 (1984); pp. 1319-1324. |
| Villaret et al., “Further insight into the physics and modeling of floating-body capacitorless DRAMs”, Electron Devices, IEEE Transactions on 52.11 (2005); pp. 2447-2454. |
| Ohsawa et al., “Autonomous refresh of floating-body cell due to Current Anomaly of Impact Ionization”, vol. 56, No. 10, pp. 2301-2311, 2009. |
| Ban et al., “A Scaled Floating Body Cell (FBC) memory with High-k+Metal Gate on Thin-Silicon and Thin-BOX fro 16-nm Technology Node and Beyond”, Symposium on VLSI Technology, 2008, pp. 92-93. |
| Campardo et al., VLSI Design of Non-Volatile Memories, Springer-Berlin Heidelberg New York, 2005, pp. 94-95. |
| Han et al., “Programming/Erasing Characteristics of 45 nm NOR-Type Flash Memory Based on SOI Fin FET Structure”, J. Korean Physical Society, vol. 47, Nov. 2005, pp. 5564-5567. |
| Headland, Hot electron injection, Feb. 19, 2004. |
| Pellizer et al., “A 90 nm Phase Change Memory Technology for Stand-Alone Non-Volatile Memory Applications”, Symposium on VLSI Technology Digest of Technical Papers, IEEE, 2006, pp. 1-2. |
| Ranica et al., “Scaled 1T-Bulk devices built with CMOS 90nm technology for low-cost eDRAM applications”, 2005 Symposium on VLSI Technology Digest of Technical Papers, pp. 38-39. |
| Pierret, Semiconductor Device Fundamentals, ISBN: 0-201-54393-1, 1996, Addison-Wesley Publishing Company, Inc., PNPN Devices 463-476. |
| Tack et al., “The Multistable Charge-Controlled Memory Effect in SOI Transistors at Low Temperatures”, IEEE Transactions on Electron Devices, vol. 37, May 1990, pp. 1373-1382. |
| Okhonin et al., “A SOI Capacitor-less 1T DRAM Concept”, 2001 IEEE International SOI Conference, pp. 153-154. |
| Ohsawa et al., “An 18.5ns 128Mb SOI DRAM with a Floating Body Cell”, IEEE International Solid-State Circuits Conference, 2005, pp. 458-459 and 609. |
| Okhonin et al., “Principles of Transient Charge Pumping on Partially Depleted SOI MOSFETs”, IEEE Electron Device Letters, vol. 23, No. 5, May 2002, pp. 279-281. |
| Okhonin et al., “A Capacitor-less 1T DRAM Cell”, IEEE Electron device Letters, vol. 23, No. 2, Feb. 2002, pp. 85-87. |
| Ohsawa et al., “Memory Design using One-Transistor Gain Cell on SOI”, Tech. Digest, IEEE Internataional Solid-State Circuits, vol. 37, No. 11, 2002, pp. 1510-1522. |
| Yoshida et al., “A Design of a Capacitorless 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory”, International Electron Devices Meeting, 2003, pp. 1-4. |
| Bawedin et al., “Floating-Body SOI Memory: Concepts, Physics and Challenges”, ECS Transactions 19.4 (2009) pp. 243-256. |
| Ban et al., “Integration of Back-Gate doping for 15-nm node floating body cell (FBC) memory”, VLSI Technology (VLSIT), 2010 Symposium on IEEE, 2010, pp. 159-160. |
| Chiu et al., “Characteristics of a new trench-oxide thin film transistor and its 1T-DRAM applications”, Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on IEEE, 2010, pp. 1106-1108. |
| Chiu et al., “A simple process of thin-film transistor using the trench-oxide layer for improving 1T-DRAM performance”, Next Generation Electronics (ISNE), 2010 International Symposium on IEEE, 2010, pp. 254-257. |
| Chun et al., “A 1.1 V, 667 MHz random cycle, asymmetric 2T gain cell embedded DRAM with a 99.9 percentile retention time of 110 microsec”, VLSI Circuits (VLSIC), 2010 IEEE Symposium on, IEEE, 2010, pp. 191-192. |
| Collaert et al., “A low voltage biasing scheme for aggressively scaled bulk FinFET 1T-DRAM featuring 10s retention at 85 C”, VLSI Technology (VLSIT), 2010 Symposium on. IEEE, 2010, pp. 161-162. |
| Giusi et al., “Bipolar mode operation and scalability of double-gate capacitorless 1T-DRAM cells”, Electron Devices, IEEE Transactions on, vol. 57, No. 8 (2010), pp. 1743-1750. |
| Gupta et al., “32nm high-density, high-speed T-RAM embedded memory technology”, Electron Devices Meeting (IEDM), 2010 IEEE International, IEEE, 2010, pp. 12.1.1-12.1.4. |
| Han et al., “Bistable resistor (biristor)-gateless silicon nanowire memory”, VLSI Technology (VLSIT), 2010 Symposium on. IEEE, 2010, pp. 171-172. |
| Han et al., “Biristor-bistable resistor based on a silicon nanowire”, Electron Device Letters, IEEE 31.8 (2010), pp. 797-799. |
| Hubert et al., “Experimental comparison of programming mechanisms in 1T-DRAM cells with variable channel length”, Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European., pp. 150-153, Sep. 14-16, 2010. |
| Kim et al., “Vertical double gate Z-RAM technology with remarkable low voltage operation for DRAM application”, VLSI Technology (VLSIT), 2010 Symposium on . . . , 2010, pp. 163-164. |
| Kim et al., “Silicon on replacement insulator (SRI) floating body cell (FBC) memory”, VLSI Technology (VLSIT), 2010 Symposium on . . . , IEEE, 2010, pp. 165-166. |
| Kim et al., “Investigation of 1T DRAM cell with non-overlap structure and recessed channel”, Silicon Nanoelectronics Workshop (SNW), 2010, IEEE, 2010, pp. 1-2. |
| Lu et al., “A simplified superior floating-body/gate DRAM cell”, IEEE Elec. Dev. Letters, vol. 30, No. 3, Mar. 2009, pp. 282-284. |
| Moon et al., “fin-width dependance of BJT-based 1T-DRAM implemented on FinFET”, Electron Device Letters, vol. 31, No. 9 (2010), pp. 909-911. |
| Moon et al., “An optically assisted program method for capacitorless 1T-DRAM”, Electron Devices, IEEE Transactions on . . . , vol. 57, No. 7, 2010, pp. 1714-1718. |
| Moon et al., “Ultimately scaled 20nm unified-RAM”, Electron Devices Meeting (IEDM), 2010 IEEE International, IEEE, 2010, pp. 12.2.1/12.2.4. |
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