Patent Application
20250069668
This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application Nos. 10-2023-0111519, filed on Aug. 24, 2023 and 10-2023-0178740, filed on Dec. 11, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties.
The disclosure relates to semiconductor memory devices, and more particularly, to memory devices for program disturbance suppression and programming methods thereof.
To store data or instructions used by a host and/or perform a computational operation, a system using semiconductor chips may use a dynamic random access memory (DRAM) as an operation memory or main memory of the system and uses storage devices as storage media. The storage devices may include a non-volatile memory. As the capacity of the storage devices increases, the number of memory cells and word lines stacked on a substrate of the non-volatile memory increases and the number of data bits stored in the memory cells also increases. To improve the storage capacity and integration degree of a memory, non-volatile memory devices in which memory cells are stacked in a three-dimensional (3D) structure, for example, 3D NAND flash memory devices, may be used.
In a 3D NAND flash memory device, a plurality of program loops can be performed until a program is completed according to incremental step pulse programming (ISPP). As the program loop increases, a program voltage may be applied as a series of pulses to a memory cell and the magnitude of the program pulses increases by a predetermined step size. Verification operations (or verification read operations) may be performed in durations between the program pulses. For example, verification operations may be performed on a data state of a memory cell in order to determine whether the memory cell has been programmed to a target level.
To increase a capacity per unit area, one or more bits may be programmed to a memory cell. The memory cell may be classified into a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC) based on the number of bits which may be stored in the memory cell. The memory cell may have a plurality of program states depending on the number of bits stored in the memory cell. The plurality of program states can be defined as a range of a threshold voltage (which may be denoted Vth). As multi-level cells (e.g., 4-state MLC, 8-state MLC, and 16-state MLC) are employed, the program time may gradually increase.
In addition, an ideal data state of programmed multi-level cells should be able to maintain a certain voltage gap from an adjacent data state and secure a sufficient read margin. However, during a program operation of the multi-level cells, a high voltage repeatedly applied to a selected memory cell or an adjacent memory cell may have an influence such as coupling, resulting in a program disturbance phenomenon. Due to this, a threshold voltage of each data state of the multi-level cells may be deformed into a non-ideal or otherwise undesirable form. Accordingly, there is a need for a method of suppressing the program disturbance phenomenon and improving a program characteristic.
Provided are memory devices that perform programming methods for program disturbance suppression.
Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments.
In accordance with an aspect of the disclosure, a memory device includes: a memory cell array including a plurality of cell strings, wherein each cell string includes a plurality of memory cells which are coupled in series between a string select transistor and a ground select transistor; a voltage generator configured to generate a precharge voltage, a program voltage, and a negative voltage, wherein a voltage level of the precharge voltage is higher than a voltage level of a ground voltage, and a voltage level of the negative voltage is lower than the voltage level of the ground voltage; and a control logic circuit configured to control a program operation for programming a threshold voltage of a selected memory cell of a selected cell string from among the plurality of cell strings to have a target state, wherein the program operation is performed using a plurality of program loops, based on a voltage increment of the program voltage, and wherein each program loop from among the plurality of program loops includes a precharge duration and a program execution duration, wherein the control logic circuit is further configured to provide the negative voltage to a plurality of unselected string select transistors and a plurality of unselected ground select transistors included in a plurality of unselected cell strings from among the plurality of cell strings, during the program execution duration.
In accordance with an aspect of the disclosure, a programming method for programming a memory device including a plurality of cell strings, each of which include a plurality of memory cells are coupled in series between a string select transistor and a ground select transistor, includes: generating a precharge voltage, a program voltage, a pass voltage, and a negative voltage, wherein a voltage level of the precharge voltage is higher than voltage level of a ground voltage, and a voltage level of the negative voltage is lower than a voltage level of the ground voltage, and wherein a voltage level of the pass voltage is set to a voltage level configured to active the plurality of memory cells regardless of program states of the plurality of memory cells; performing a program operation for programming a threshold voltage of a selected memory cell of a selected cell string from among the plurality of cell strings to have a target state, wherein the program operation is performed using a plurality of program loops, based on a voltage increment of the program voltage, and wherein each program loop of the plurality of program loops includes a precharge duration and a program execution duration; providing the precharge voltage to a plurality of unselected string select transistors and a plurality of unselected ground select transistor included in a plurality of unselected cell strings from among the plurality of cell strings, during the precharge duration; and providing the negative voltage to the plurality of unselected string select transistors and the plurality of unselected ground select transistors, during the program execution duration.
In accordance with an aspect of the disclosure, a programming method of a memory device including a plurality of cell strings, each of which includes a plurality of memory cells are coupled in series between a string select transistor and a ground select transistor, includes: generating a precharge voltage, a program voltage, and a negative voltage, wherein a voltage level of the precharge voltage is higher than a voltage level of a ground voltage, and a voltage level of the negative voltage is lower than the voltage level of the ground voltage; performing a program operation for programming a threshold voltage of a selected memory cell of a selected cell string from among the plurality of cell strings to have a target state, wherein the program operation is performed using program loops, based on a voltage increment of the program voltage, and wherein each program of the plurality of program loops includes a precharge duration and a program execution duration; providing the ground voltage to a plurality of unselected string select transistors and a plurality of unselected ground select transistors included in unselected cell strings from among the plurality of cell strings, during the precharge duration; and providing the negative voltage to the plurality of unselected string select transistors and the plurality of unselected ground select transistors, during the program execution duration.
The above and other aspects, features, and advantages of certain embodiments of the present disclosure will be more apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
Hereinafter, embodiments will be described with reference to the accompanying drawings.
As is traditional in the field, the embodiments are described, and illustrated in the drawings, in terms of functional blocks, units and/or modules. Those skilled in the art will appreciate that these blocks, units and/or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, and the like, which may be formed using semiconductor-based fabrication techniques or other manufacturing technologies. In the case of the blocks, units and/or modules being implemented by microprocessors or similar, they may be programmed using software (e.g., microcode) to perform various functions discussed herein and may optionally be driven by firmware and/or software. Alternatively, each block, unit and/or module may be implemented by dedicated hardware, or as a combination of dedicated hardware to perform some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) to perform other functions. Also, each block, unit and/or module of the embodiments may be physically separated into two or more interacting and discrete blocks, units and/or modules without departing from the present scope. Further, the blocks, units and/or modules of the embodiments may be physically combined into more complex blocks, units and/or modules without departing from the present scope.
Referring to
The memory cell array 12 may be coupled to word lines WL, string select lines SSL, ground select lines GSL, and bit lines BL. The memory cell array 12 may be coupled to the row decoder 16 through the word lines WL, the string select lines SSL, and the ground select lines GSL and may be coupled to the page buffer 17 through the bit lines BL. The memory cell array 12 may include a plurality of memory blocks BLK1 to BLKn, where n is a natural number of 2 or more. Each memory block of the plurality of memory blocks BLK1 to BLKn may include a plurality of memory cells. For example, the plurality of memory cells may include flash memory cells. Hereinafter, embodiments are described in detail by way of an example in which each memory cell of the plurality of memory cells BLK1 to BLKn include NAND flash memory cells, but embodiments are not limited thereto. The memory cell array 12 may include a three-dimensional memory cell array including a plurality of cell strings.
The three-dimensional memory cell array may be formed in a monolithic manner in a physical level of at least one memory cell array that has an active region disposed on a silicon substrate and a circuit formed on or in the substrate as a circuit related to an operation of memory cells. The term “monolithic” may mean that layers of each level included in the array may be stacked directly on layers of each lower level of the array. In an embodiment, the three-dimensional memory cell array may include cell strings arranged in a vertical direction such that at least one memory cell is located above another memory cell. The at least one memory cell may include a charge trap layer. U.S. Pat. Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and U.S.
Patent Application Publication No. 2011/0233648, the disclosures of which are incorporated by reference herein in their entirety, disclose suitable configurations of a three-dimensional memory array including a plurality of levels and sharing word lines and/or bit lines between the levels.
Each memory block BLK1 to BLKn may include a plurality of memory cells and a plurality of select transistors (e.g., string select transistors SST and ground select transistors GST). The memory cells may be respectively coupled to the word lines WL, and the select transistors may be coupled to the string select lines SSL or the ground select lines GSL. The memory cells included each memory block BLK1 to BLKn may include single-level cells storing 1-bit data, or may include multi-level cells storing M-bit data, where M is an integer of 2 or more.
The row decoder 16 may select one of the plurality of memory blocks BLK1 to BLKn of the memory cell array 12, may select one of the word lines WL of the selected memory block, and may select one of the plurality of string select lines SSL.
The control logic circuit 14 may output various internal control signals for performing program, read, and erase operations on the memory cell array 12, based on a command CMD, an address ADDR, and a control signal CTRL received from the memory controller. The control logic circuit 14 may provide a row address R_ADDR to the row decoder 16, may provide a column address to the input/output circuit 18, and may provide a voltage control signal CTRL_VOL to the voltage generator 15.
The control logic circuit 14 may control a program operation such that threshold voltages of memory cells of a first page and a second page disposed adjacently to each other at the same height from a substrate within the memory cell array 12 have a plurality of target states. In some embodiments, the first page may be referred to as a previous page, and the second page may be referred to as a next page, and the previous page and the next page may be disposed adjacently to each other at the same height from a substrate within the memory cell array 12.
In some embodiments, the control logic circuit 14 may boost a channel potential using a self-boosting effect to prevent program disturbance from occurring in a channel of a program-inhibited cell string during a program operation. The self-boosting effect may refer to precharging a program-inhibited channel in the bit line BL and causing the program-inhibited channel to be a floating node, and coupling a series capacitance from the word line WL to the channel, in order to automatically boost the channel potential.
In some embodiments, the control logic circuit 14 may perform a program operation using a bidirectional precharge and negative bias (BPNB) scheme which includes precharging the program-inhibited channel not only in the bit line BL but also a common source line CSL, and causing the program-inhibited channel to have an enhanced self-boosting effect. The BPNB scheme may suppress program disturbance by sufficiently depleting electrons remaining in the program-inhibited channel and allowing the program-inhibited channel to have a high channel potential, before a program voltage of a program execution duration is applied to the word line WL for a program execution duration.
In some embodiments, the control logic circuit 14 may provide a negative (−) voltage to a string select transistor and a ground select transistor coupled to a program-inhibited channel, during a program execution duration. This may be done to prevent the introduction of electrons from the bit line and the common source line and consistently keep the channel potential high.
The page buffer 17 may operate as a write driver or a sense amplifier depending on an operation mode. During a read operation, the page buffer 17 may sense a bit line BL of a selected memory cell under the control by the control logic circuit 14. Sensed data may be stored in latches provided within the page buffer 17. The page buffer 17 may dump the data stored in the latches to the input/output circuit 18 through a data line DL under the control by the control logic circuit 14.
The input/output circuit 18 may temporarily store a command CMD, an address ADDR, and data DATA that are provided through an input/output line I/O from the memory controller. The input/output circuit 18 may temporarily store read data of the memory device 10 and output the stored data to an outside (e.g., an outside of the memory device 10) through the input/output line I/O at a specified time.
The voltage generator 15 may generate various types of voltages VWL for performing program, read, and erase operations on the memory cell array 12, based on a voltage control signal CTRL_VOL. For example, as shown in
The memory block BLK1 shown in
Referring to
Each cell string (e.g., NS11) may include a string select transistor SST, a plurality of memory cells MC, and a ground select transistor GST that are coupled in series. The string select transistor SST may be coupled to a corresponding string select line SSL1. The plurality of memory cells MC may be coupled to the corresponding word lines WL1 to WL8, respectively. The ground select transistor GST may be coupled to the ground select line GSL. The string select transistor SST may be coupled to the corresponding bit lines BL1 to BL3, and the ground select transistor GST may be coupled to the common source line CSL.
In some embodiments, each cell string may be provided with one or more dummy memory cells between the string select transistor SST and the memory cells MC. Each cell string may be provided with one or more dummy memory cells between the ground select transistor GST and the memory cells MC. Each cell string may be provided with one or more dummy memory cells between the memory cells MC. The dummy memory cells may have the same structure as the memory cells MC and may be unprogrammed (e.g., program-inhibited) or may be programmed differently from the memory cells MC. For example, when the memory cells MC are programmed to have two or a larger number of threshold voltage distributions, the dummy memory cells may be programmed to have one threshold voltage distribution range or a smaller number of threshold voltage distributions than the memory cells MC.
First, first page data is simultaneously stored in memory cells of a selected word line. As shown in
Next, two-page data, for example second page data and third page data, is simultaneously stored in the memory cells of the selected word line. As shown in
Here, verification voltages VP1′ to VP7′ used to determine the threshold voltage distributions P1′ to P7′ are lower than verification voltages VP1 to VP7 used to determine final threshold voltage distributions P1 to P7 (as shown for example in
Referring to
In some embodiments, the number of program loops may be determined by the voltage increment ΔV used to generate the plurality of step pulse voltages. A voltage shift in each program loop when a small voltage increment ΔV is applied may appear small, and a voltage shift in each program loop when a large voltage increment ΔV is applied may appear large. When the same voltage is shifted, the number of program loops used when the large voltage increment ΔV is applied may be less than the number of program loops used when the small voltage increment ΔV is applied. The small number of program loops may mean that the program speed is fast because the number of repeated programs is small. Conversely, the large number of program loops may mean that the program speed is slow because the number of repeated programs is large.
Referring to
According to the example shown in
In the program execution duration between time t2 and time t3, a program voltage VPGM1 may be applied to the selected word line WLsel, and a program pass voltage VPASS may be applied to the unselected word lines WLunsel. The program pass voltage VPASS may be provided as a voltage level capable of always activating or turning on a memory cell regardless of a program state of the memory cell.
In this program duration, 18 V may be applied to a gate of the selected memory cell TG programmed in the NS11 cell string, and a channel voltage may be 0 V. Because a strong electric field may be formed between the gate of the selected memory cell TG and a channel, the selected memory cell TG may be programmed. Because a channel voltage of a memory cell X adjacent to the selected memory cell TG may be a power supply voltage VDD, and a weak electric field may be formed between a gate of the memory cell X and a channel, the memory cell X may be not programmed. Because channels of memory cells Y and XY adjacent to the selected memory cell TG may be in a floating state, a channel voltage may rise to a boosting level by the pass voltage VPASS, and the memory cells Y and XY may be not programmed.
In some embodiments, in the verification duration after the program duration, a read pass voltage capable of always activating or turning on a memory cell regardless of a program state of the memory cell may be applied to the unselected word line WLunsel, and a verification voltage VVFY may be applied to the selected word line WLsel. In addition, an activation voltage may be applied to a selected ground select line GSL, and a deactivation voltage may be applied to an unselected ground select line GSL. In embodiments, the deactivation voltage may be referred to as a turn-off voltage. In this verification duration, it may be determined whether the selected memory cell TG has been programmed to a target program state.
The programming process described with reference to
Referring to
In some embodiments, according to the BP scheme, channels of a plurality of cell strings may be precharged through a selected string select transistor SST coupled to the unselected string select line SSLunsel, and may be precharged through a ground select transistor GST coupled to the ground select line GSL
In the program execution duration between time t2 and time t3, the program voltage VPGM1 may be applied to the selected word line WLsel, and a program pass voltage VPASS may be applied to the unselected word lines WLunsel. The ground voltage VSS may be applied to the selected bit line BLsel, the unselected string select line SSLunsel, and the ground select line GSL.
Referring to
In the program execution duration between time t2 and time t3, a program voltage VPGM1 may be applied to the selected word line WLsel, and a program pass voltage VPASS may be applied to the unselected word lines WLunsel. A ground voltage VSS may be applied to the selected bit line BLsel. A negative voltage VNEG may be applied to the unselected string select line SSLunsel and the ground select line GSL. The negative voltage VNEG may be provided as a voltage level lower than the ground voltage VSS.
In the precharge duration between time t1 and time t2, the BPNB scheme of
In the program execution duration between time t2 and time t3, a program voltage VPGM1 may be applied to the selected word line WLsel, and a program pass voltage VPASS may be applied to the unselected word lines WLunsel. A negative voltage VNEG may be applied to the unselected string select line SSLunsel and the ground select line GSL.
Referring to
ΔVth=Vth,pgm-Vth,ers (Equation 1)
In Equation 1 above, Vth,pgm may denote a threshold voltage of a program state, and Vth,ers may denote a threshold voltage of an erase state. The program efficiency may be superior as the ΔVth value increases because a threshold voltage of a target program state may be reached faster at the same program voltage. In contrast, as the ΔVth decreases, the degree of program disturbance may be superior in a memory cell Y because the memory cell Y may be designed not to be programmed from the beginning.
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
The memory device 500 may include the at least one upper chip including the cell region. For example, as illustrated in
Each of the peripheral circuit region PERI and the first and second cell regions CELL1 and CELL2 of the memory device 500 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.
The peripheral circuit region PERI may include a first substrate 210 and a plurality of circuit elements 220a, 220b and 220c formed on the first substrate 210. An interlayer insulating layer 215 including one or more insulating layers may be provided on the plurality of circuit elements 220a, 220b and 220c, and a plurality of metal lines electrically connected to the plurality of circuit elements 220a, 220b and 220c may be provided in the interlayer insulating layer 215. For example, the plurality of metal lines may include first metal lines 230a, 230b and 230c connected to the plurality of circuit elements 220a, 220b and 220c, and second metal lines 240a, 240b and 240c formed on the first metal lines 230a, 230b and 230c. The plurality of metal lines may be formed of at least one of various conductive materials. For example, the first metal lines 230a, 230b and 230c may be formed of tungsten having a relatively high electrical resistivity, and the second metal lines 240a, 240b and 240c may be formed of copper having a relatively low electrical resistivity.
The first metal lines 230a, 230b and 230c and the second metal lines 240a, 240b and 240c are illustrated and described in the present embodiments. However, embodiments are not limited thereto. For example, in some embodiments, at least one or more additional metal lines may further be formed on the second metal lines 240a, 240b and 240c. In this case, the second metal lines 240a, 240b and 240c may be formed of aluminum, and at least some of the additional metal lines formed on the second metal lines 240a, 240b and 240c may be formed of copper having an electrical resistivity lower than that of aluminum of the second metal lines 240a, 240b and 240c.
The interlayer insulating layer 215 may be disposed on the first substrate 210 and may include an insulating material such as silicon oxide and/or silicon nitride.
Each of the first and second cell regions CELL1 and CELL2 may include at least one memory block. The first cell region CELL1 may include a second substrate 310 and a common source line 320. A plurality of word lines 330 (including for example word line 331 to word line 338) may be stacked on the second substrate 310 in a direction (i.e., the Z-axis direction) perpendicular to a top surface of the second substrate 310. String selection lines and a ground selection line may be disposed on and under the plurality of word lines 330, and the plurality of word lines 330 may be disposed between the string selection lines and the ground selection line. Similarly, the second cell region CELL2 may include a third substrate 410 and a common source line 420, and a plurality of word lines 430 (including for example word line 431 to word line 438) may be stacked on the third substrate 410 in a direction (e.g., the Z-axis direction) perpendicular to a top surface of the third substrate 410. Each of the second substrate 310 and the third substrate 410 may be formed of at least one of various materials and may be, for example, a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a substrate having a single-crystalline epitaxial layer grown on a single-crystalline silicon substrate. A plurality of channel structures CH may be formed in each of the first and second cell regions CELL1 and CELL2.
In some embodiments, as illustrated in a region ‘A1’, the channel structure CH may be provided in the bit line bonding region BLBA and may extend in the direction perpendicular to the top surface of the second substrate 310 to penetrate the plurality of word lines 330, the string selection lines, and the ground selection line. The channel structure CH may include a data storage layer, a channel layer, and a filling insulation layer. The channel layer may be electrically connected to a first metal line 350c and a second metal line 360c in the bit line bonding region BLBA. For example, the second metal line 360c may be a bit line and may be connected to the channel structure CH through the first metal line 350c. The bit line 360c may extend in a first direction (e.g., a Y-axis direction) parallel to the top surface of the second substrate 310.
In some embodiments, as illustrated in a region ‘A2’, the channel structure CH may include a lower channel LCH and an upper channel UCH, which are connected to each other. For example, the channel structure CH may be formed by a process of forming the lower channel LCH and a process of forming the upper channel UCH. The lower channel LCH may extend in the direction perpendicular to the top surface of the second substrate 310 to penetrate the common source line 320 and lower word lines 331 and 332. The lower channel LCH may include a data storage layer, a channel layer, and a filling insulation layer and may be connected to the upper channel UCH. The upper channel UCH may penetrate upper word lines 333 to 338. The upper channel UCH may include a data storage layer, a channel layer, and a filling insulation layer, and the channel layer of the upper channel UCH may be electrically connected to the first metal line 350c and the second metal line 360c. As a length of a channel increases, due to characteristics of manufacturing processes, it may be difficult to form a channel having a substantially uniform width. The memory device 500 according to embodiments may include a channel having improved width uniformity due to the lower channel LCH and the upper channel UCH which are formed by the processes performed sequentially.
In the case in which the channel structure CH includes the lower channel LCH and the upper channel UCH as illustrated in the region ‘A2’, a word line located near to a boundary between the lower channel LCH and the upper channel UCH may be a dummy word line. For example, the word lines 332 and 333 adjacent to the boundary between the lower channel LCH and the upper channel UCH may be the dummy word lines. In this case, data may not be stored in memory cells connected to the dummy word line. In some embodiments, the number of pages corresponding to the memory cells connected to the dummy word line may be less than the number of pages corresponding to the memory cells connected to a general word line. A level of a voltage applied to the dummy word line may be different from a level of a voltage applied to the general word line, and thus it may be possible to reduce an influence of a non-uniform channel width between the lower and upper channels LCH and UCH on an operation of the memory device.
In embodiments, the number of the lower word lines 331 and 332 penetrated by the lower channel LCH may be less than the number of the upper word lines 333 to 338 penetrated by the upper channel UCH in the region ‘A2’. However, embodiments are not limited thereto. For example, in some embodiments, the number of lower word lines penetrated by the lower channel LCH may be equal to or greater than the number of upper word lines penetrated by the upper channel UCH. In addition, structural features and connection relationships of the channel structure CH disposed in the second cell region CELL2 may be substantially the same as those of the channel structure CH disposed in the first cell region CELL1.
In the bit line bonding region BLBA, a first through-electrode THV1 may be provided in the first cell region CELL1, and a second through-electrode THV2 may be provided in the second cell region CELL2. As illustrated in
In some embodiments, the first through-electrode THV1 and the second through-electrode THV2 may be electrically connected to each other using a first through-metal pattern 372d and a second through-metal pattern 472d. The first through-metal pattern 372d may be formed at a bottom end of the first upper chip including the first cell region CELL1, and the second through-metal pattern 472d may be formed at a top end of the second upper chip including the second cell region CELL2. The first through-electrode THV1 may be electrically connected to the first metal line 350c and the second metal line 360c. A lower via 371d may be formed between the first through-electrode THV1 and the first through-metal pattern 372d, and an upper via 471d may be formed between the second through-electrode THV2 and the second through-metal pattern 472d. The first through-metal pattern 372d and the second through-metal pattern 472d may be connected to each other using the bonding process.
In addition, in the bit line bonding region BLBA, an upper metal pattern 252 may be formed in an uppermost metal layer of the peripheral circuit region PERI, and an upper metal pattern 392 having the same shape as the upper metal pattern 252 may be formed in an uppermost metal layer of the first cell region CELL1. The upper metal pattern 392 of the first cell region CELL1 and the upper metal pattern 252 of the peripheral circuit region PERI may be electrically connected to each other using the bonding process. In the bit line bonding region BLBA, the bit line 360c may be electrically connected to a page buffer included in the peripheral circuit region PERI. For example, some of the circuit elements 220c of the peripheral circuit region PERI may be included in the page buffer, and the bit line 360c may be electrically connected to the circuit elements 220c which may be included in the page buffer through an upper bonding metal pattern 370c of the first cell region CELL1 and an upper bonding metal pattern 270c of the peripheral circuit region PERI.
Referring still to
The plurality of cell contact plugs 340 may be electrically connected to a row decoder included in the peripheral circuit region PERI. For example, some of the circuit elements 220b of the peripheral circuit region PERI may be included in the row decoder, and the plurality of cell contact plugs 340 may be electrically connected to the circuit elements 220b included in the row decoder through the upper bonding metal patterns 370b of the first cell region CELL1 and the upper bonding metal patterns 270b of the peripheral circuit region PERI. In some embodiments, an operating voltage of the circuit elements 220b included in the row decoder may be different from an operating voltage of the circuit elements 220c included in the page buffer. For example, the operating voltage of the circuit elements 220c included in the page buffer may be greater than the operating voltage of the circuit elements 220b included in the row decoder.
Similarly, in the word line bonding region WLBA, the word lines 430 of the second cell region CELL2 may extend in the second direction (e.g., the X-axis direction) parallel to the top surface of the third substrate 410 and may be connected to a plurality of cell contact plugs 440 (including for example cell contact plug 441 to cell contact plug 447). The plurality of cell contact plugs 440 may be connected to the peripheral circuit region PERI through an upper metal pattern of the second cell region CELL2 and lower and upper metal patterns and a cell contact plug 348 of the first cell region CELL1.
In the word line bonding region WLBA, the upper bonding metal patterns 370b may be formed in the first cell region CELL1, and the upper bonding metal patterns 270b may be formed in the peripheral circuit region PERI. The upper bonding metal patterns 370b of the first cell region CELL1 and the upper bonding metal patterns 270b of the peripheral circuit region PERI may be electrically connected to each other using the bonding process. The upper bonding metal patterns 370b and the upper bonding metal patterns 270b may be formed of aluminum, copper, or tungsten.
In the external pad bonding region PA, a lower metal pattern 371e may be formed in a lower portion of the first cell region CELL1, and an upper metal pattern 472a may be formed in an upper portion of the second cell region CELL2. The lower metal pattern 371e of the first cell region CELL1 and the upper metal pattern 472a of the second cell region CELL2 may be connected to each other using the bonding process in the external pad bonding region PA. Similarly, an upper metal pattern 372a may be formed in an upper portion of the first cell region CELL1, and an upper metal pattern 272a may be formed in an upper portion of the peripheral circuit region PERI. The upper metal pattern 372a of the first cell region CELL1 and the upper metal pattern 272a of the peripheral circuit region PERI may be connected to each other using the bonding process.
Common source line contact plugs 380 and 480 may be disposed in the external pad bonding region PA. The common source line contact plugs 380 and 480 may be formed of a conductive material such as a metal, a metal compound, and/or doped polysilicon. The common source line contact plug 380 of the first cell region CELL1 may be electrically connected to the common source line 320, and the common source line contact plug 480 of the second cell region CELL2 may be electrically connected to the common source line 420. A first metal line 350a and a second metal line 360a may be sequentially stacked on the common source line contact plug 380 of the first cell region CELL1, and a first metal line 450a and a second metal line 460a may be sequentially stacked on the common source line contact plug 480 of the second cell region CELL2.
Input/output pads 205, 405 and 406 may be disposed in the external pad bonding region PA. Referring to
An upper insulating layer 401 covering a top surface of the third substrate 410 may be formed on the third substrate 410. A second input/output pad 405 and/or a third input/output pad 406 may be disposed on the upper insulating layer 401. The second input/output pad 405 may be connected to at least one of the plurality of circuit elements 220a disposed in the peripheral circuit region PERI through second input/output contact plugs 403 and 303, and the third input/output pad 406 may be connected to at least one of the plurality of circuit elements 220a disposed in the peripheral circuit region PERI through third input/output contact plugs 404 and 304.
In some embodiments, the third substrate 410 may not be disposed in a region in which the input/output contact plug is disposed. For example, as illustrated in a region ‘B’, the third input/output contact plug 404 may be separated from the third substrate 410 in a direction parallel to the top surface of the third substrate 410 and may penetrate an interlayer insulating layer 415 of the second cell region CELL2 in order to be connected to the third input/output pad 406. In this case, the third input/output contact plug 404 may be formed by at least one of various processes.
In some embodiments, as illustrated in a region ‘B1’, the third input/output contact plug 404 may extend in a third direction (e.g., the Z-axis direction), and a diameter of the third input/output contact plug 404 may become progressively larger toward the upper insulating layer 401. In other words, a diameter of the channel structure CH described in the region ‘A1’ may become progressively smaller toward the upper insulating layer 401, but the diameter of the third input/output contact plug 404 may become progressively larger toward the upper insulating layer 401. For example, the third input/output contact plug 404 may be formed after the second cell region CELL2 and the first cell region CELL1 are bonded to each other using the bonding process.
In some embodiments, as illustrated in a region ‘B2’, the third input/output contact plug 404 may extend in the third direction (e.g., the Z-axis direction), and a diameter of the third input/output contact plug 404 may become progressively smaller toward the upper insulating layer 401. In other words, like the channel structure CH, the diameter of the third input/output contact plug 404 may become progressively smaller toward the upper insulating layer 401. For example, the third input/output contact plug 404 may be formed together with the plurality of cell contact plugs 440 before the second cell region CELL2 and the first cell region CELL1 are bonded to each other.
In some embodiments, the input/output contact plug may overlap with the third substrate 410. For example, as illustrated in a region ‘C’, the second input/output contact plug 403 may penetrate the interlayer insulating layer 415 of the second cell region CELL2 in the third direction (e.g., the Z-axis direction) and may be electrically connected to the second input/output pad 405 through the third substrate 410. In this case, a connection structure of the second input/output contact plug 403 and the second input/output pad 405 may be created using various processes.
In some embodiments, as illustrated in a region ‘C1’, an opening 408 may be formed to penetrate the third substrate 410, and the second input/output contact plug 403 may be connected directly to the second input/output pad 405 through the opening 408 formed in the third substrate 410. In this case, as illustrated in the region ‘C1’, a diameter of the second input/output contact plug 403 may become progressively larger toward the second input/output pad 405. However, embodiments are not limited thereto, and in some embodiments, the diameter of the second input/output contact plug 403 may become progressively smaller toward the second input/output pad 405.
In some embodiments, as illustrated in a region ‘C2’, the opening 408 penetrating the third substrate 410 may be formed, and a contact 407 may be formed in the opening 408. An end of the contact 407 may be connected to the second input/output pad 405, and another end of the contact 407 may be connected to the second input/output contact plug 403. Thus, the second input/output contact plug 403 may be electrically connected to the second input/output pad 405 through the contact 407 in the opening 408. In this case, as illustrated in the region ‘C2’, a diameter of the contact 407 may become progressively larger toward the second input/output pad 405, and a diameter of the second input/output contact plug 403 may become progressively smaller toward the second input/output pad 405. For example, the second input/output contact plug 403 may be formed together with the plurality of cell contact plugs 440 before the second cell region CELL2 and the first cell region CELL1 are bonded to each other, and the contact 407 may be formed after the second cell region CELL2 and the first cell region CELL1 are bonded to each other.
In some embodiments illustrated in a region ‘C3’, a stopper 409 may further be formed on a bottom end of the opening 408 of the third substrate 410, as compared with the embodiments of the region ‘C2’. The stopper 409 may be a metal line formed in the same layer as the common source line 420. In some embodiments, the stopper 409 may be a metal line formed in the same layer as at least one of the word lines 430. The second input/output contact plug 403 may be electrically connected to the second input/output pad 405 through the contact 407 and the stopper 409.
Like the second and third input/output contact plugs 403 and 404 of the second cell region CELL2, a diameter of each of the second and third input/output contact plugs 303 and 304 of the first cell region CELL1 may become progressively smaller toward the lower metal pattern 371e or may become progressively larger toward the lower metal pattern 371e.
In some embodiments, a slit 411 may be formed in the third substrate 410. For example, the slit 411 may be formed at a certain position of the external pad bonding region PA. For example, as illustrated in a region ‘D’, the slit 411 may be located between the second input/output pad 405 and the plurality of cell contact plugs 440 in a plan view. In some embodiments, the second input/output pad 405 may be located between the slit 411 and the cell contact plugs 440 in a plan view.
In some embodiments, as illustrated in a region ‘D1’, the slit 411 may be formed to penetrate the third substrate 410. For example, the slit 411 may be used to prevent the third substrate 410 from being finely cracked when the opening 408 is formed. However, embodiments are not limited thereto, and in some embodiments, the slit 411 may be formed to have a depth ranging from about 60% to about 70% of a thickness of the third substrate 410.
In some embodiments, as illustrated in a region ‘D2’, a conductive material 412 may be formed in the slit 411. For example, the conductive material 412 may be used to discharge a leakage current occurring in driving of the circuit elements in the external pad bonding region PA to the outside. In this case, the conductive material 412 may be connected to an external ground line.
In some embodiments, as illustrated in a region ‘D3’, an insulating material 413 may be formed in the slit 411. For example, the insulating material 413 may be used to electrically isolate the second input/output pad 405 and the second input/output contact plug 403 disposed in the external pad bonding region PA from the word line bonding region WLBA. Because the insulating material 413 may be formed in the slit 411, it may be possible to prevent a voltage provided through the second input/output pad 405 from affecting a metal layer disposed on the third substrate 410 in the word line bonding region WLBA.
In some embodiments, the first to third input/output pads 205, 405 and 406 may be selectively formed. For example, the memory device 500 include only the first input/output pad 205 disposed on the first substrate 210, to include only the second input/output pad 405 disposed on the third substrate 410, or to include only the third input/output pad 406 disposed on the upper insulating layer 401.
In some embodiments, at least one of the second substrate 310 of the first cell region CELL1 or the third substrate 410 of the second cell region CELL2 may be used as a sacrificial substrate and may be completely or partially removed before or after a bonding process. An additional layer may be stacked after the removal of the substrate. For example, the second substrate 310 of the first cell region CELL1 may be removed before or after the bonding process of the peripheral circuit region PERI and the first cell region CELL1, and then, an insulating layer covering a top surface of the common source line 320 or a conductive layer for connection may be formed. Similarly, the third substrate 410 of the second cell region CELL2 may be removed before or after the bonding process of the first cell region CELL1 and the second cell region CELL2, and then, the upper insulating layer 401 covering a top surface of the common source line 420 or a conductive layer for connection may be formed.
Referring to
Referring to
The camera 2100 may capture still images or moving images under user control, and store or transmit captured image/video data to the display 2200. The audio processor 2300 may process audio data included in content of the flash memories 2600a and 2600b or a network. The modem 2400 may modulate and transmit signals for wired/wireless data transmission and reception, and demodulate and restore signals to the original signals at a receiving side. The input/output devices 2700a and 2700b may include a device providing a digital input and/or output function, such as a universal serial bus (USB), a storage, a digital camera, a secure digital (SD) card, a digital versatile disc (DVD), a network adapter, a touch screen, etc.
The AP 2800 may control the overall operation of the system 2000. The AP 2800 may include a controller block 2810, an accelerator block or accelerator chip 2820, and an interface block 2830. The AP 2800 may control the display 2200 so that part of content stored in the flash memories 2600a and 2600b is displayed on the display 2200. When a user input is received through the input/outputdevices 2700a and 2700b, the AP 2800 may perform a control operation corresponding to the user input. The AP 2800 may include the accelerator block, which is a dedicated circuit for artificial intelligence (AI) data operation, or may have the accelerator chip 2820 apart from the AP 2800. The DRAM 2500b may be additionally mounted on the accelerator block or accelerator chip 2820. The accelerator is a function block of specializing in performing a specific function of the AP 2800. The accelerator may include a GPU that is a function block of specializing in graphics data processing, a neural processing unit (NPU) that is a block for specializing in performing AI determination and inference, and a data processing unit (DPU) that is a block of specializing in data transmission.
The system 2000 may include the plurality of DRAMs 2500a and 2500b. The AP 2800 may control the DRAMs 2500a and 2500b through command and mode register (MRS) settings that meet the Joint Electron Device Engineering Council (JEDEC) standard, or may communicate by setting a DRAM interface protocol so as to use a company-specific function such as low voltage/high speed/reliability, and a cyclic redundancy check (CRC)/error correction code (ECC) function. For example, the AP 2800 may communicate with the DRAM 2500a through an interface that meets JEDEC standards relating to Low-Power Double Data Rate (LPDDR) such as LPDDR4 and LPDDR5, and the accelerator block or accelerator chip 2820 may communicate by setting a new DRAM interface protocol so as to control the accelerator DRAM 2500b having a higher bandwidth than the DRAM 2500a.
Although only the DRAMs 2500a and 2500b are illustrated in
In the DRAMs 2500a and 2500b, basic operations such as addition/subtraction/multiplication/division operations, vector operations, address operations, or fast Fourier transform (FFT) operations may be performed. Also, a function of a mathematical function for execution used for inference may be performed within the DRAMs 2500a and 2500b. Here, the inference may be performed in a deep learning algorithm that uses an artificial neural network. The deep learning algorithm may include a training step of learning a model through various data and an inference step of recognizing data with the learned model. As an example, an image taken by a user through the camera 2100 may be signal processed and stored in the DRAM 2500b, and the accelerator block or accelerator chip 2820 may perform AI data operations of recognizing data using the data stored in the DRAM 2500b and the mathematical function used for inference.
The system 2000 may include a plurality of storages or the plurality of flash memories 2600a and 2600b having larger capacities than the DRAMs 2500a and 2500b. The accelerator block or accelerator chip 2820 may perform a training step and an AI data operation, using the flash memories 2600a and 2600b. In an embodiment, the flash memories 2600a and 2600b may include a memory controller 2610 and a flash memory device 2620, and may perform more efficiently the training step and the inference AI data operation performed by the AP 2800 and/or the accelerator chip 2820, using a computing device installed in the memory controller 2610. The flash memories 2600a and 2600b may store photos taken through the camera 2100, or store data received over a data network. For example, the flash memories 2600a and 2600b may store augmented reality/virtual reality, high definition (HD), or ultra high definition (UHD) content.
In the system 2000, the flash memories 2600a and 2600b may include the memory devices described with reference to
Although embodiments have been described above using specific terminology, this terminology is not used to limit the meaning or scope of the disclosure. Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments are included in the scope of the disclosure.
While embodiments are particularly shown in the drawings and described above, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0111519 | Aug 2023 | KR | national |
| 10-2023-0178740 | Dec 2023 | KR | national |
