Patent Application
20060186451
This application is a continuation of PCT patent application number PCT/EP2004/010085, filed Sep. 9, 2004, which claims priority to German patent application number 10344814.4, filed Sep. 26, 2003, the disclosures of each of which are incorporated herein by reference in their entirety.
The present invention relates in general terms to memory devices for storing electric charge having memory cells and transistors arranged spatially next to them, and relates in particular to memory devices having memory cells with a high capacitance.
In the memory cells which form a memory device to which the invention relates, there is a substrate and at least one memory cell which is arranged on the substrate and includes a first electrode element, which is electrically connected to the substrate, an insulation layer, which has been applied to the first electrode element, and a second electrode element, which has been applied to the insulation layer and is electrically insulated from the first electrode element.
Conventional memory devices comprise a trench capacitor, which is coupled to a horizontally or vertically oriented transistor based on silicon or crystalline silicon, with the transistor being arranged spatially next to the capacitor. To provide the capacitors with a storage capacity, a certain minimum capacitance is required in order to generate a measurable signal which is greater than the thermal noise. This minimum capacitance is typically 30 fF (femtofarad, 10−12 farad).
Ongoing miniaturization requires the provision of ever smaller structures for the storage capacitor. This scaling of the capacitors entails considerable problems, which include the difficulty of a continuous, uniform coating of the capacitor with a dielectric, the production of small electrodes with sufficient mechanical stability while maintaining the capacitance, etc.
One significant drawback of conventional memory devices consists in the fact that a capacitance is insufficient, since it is not possible to provide a sufficiently large electrode surface area and/or a sufficiently thin dielectric.
Proceeding from this prior art, the invention is based on the object of providing a memory device and a method for fabricating a memory device, memory cells that are present in the memory device having a sufficient storage capacity.
According to the invention, this object is achieved by a memory device for storing electric charge having the features of claim 1.
Furthermore, the object is achieved by a method as described in patent claim 9.
Further configurations of the invention will emerge from the subclaims.
One important concept of the invention consists in providing one of the electrode elements which form the capacitor of a memory cell with a high aspect ratio, i.e. a great length compared to the dimensions of a base area, so that an increase in the capacitance of the memory cells associated with an increase in the surface area of the electrode is provided. According to the invention, a nanotube (NT) having a high aspect ratio and a sufficient mechanical stability is provided as a first electrode element, which is electrically connected to the substrate.
One significant benefit of the method according to the invention comprises providing a nanotube as a first electrode element consists in the fact that it is possible to use standardized lithography processes while structures with sub-lithographic features can be produced.
It is thus advantageously possible to increase a capacitance of the memory cell by virtue of the fact that it is possible to provide a nanotube of small diameter which is below a feature size of the standardized lithography.
The memory device for storing electric charge is advantageously produced by means of standardized processes of chemical vapor deposition (CVD) and/or atomic layer deposition (ALD).
The memory device according to the invention for storing electric charge substantially includes:
a) a substrate;
b) at least one memory cell which is arranged on the substrate and includes a first electrode element, which is electrically connected to the substrate, an insulation layer, which has been applied to the first electrode element, and a second electrode element, which has been applied to the insulation layer and is electrically insulated from the first electrode element, the first electrode element, which is electrically connected to the substrate, being provided as a nanotube with a high aspect ratio.
Furthermore, the method according to the invention for fabricating a memory device for storing electric charge substantially includes the following steps:
a) providing a substrate; and
b) providing at least one memory cell arranged on the substrate by a first electrode element, which is electrically connected to the substrate, being grown on the substrate, an insulation layer being applied to the first electrode element, and a second electrode element, which is electrically insulated from the first electrode element, being applied to the insulation layer, in which method the first electrode element, which is electrically connected to the substrate, is grown on the substrate as a nanotube with a high aspect ratio.
According to a preferred refinement of the present invention, the first electrode element, which is electrically connected to the substrate, is formed as a carbon nanotube (CNT).
According to a further preferred refinement of the present invention, the insulation layer is provided as a dielectric with a dielectric constant (k) in the range from 10 to 25.
According to yet another preferred refinement of the present invention, the second electrode element, which has been applied to the insulation layer and is electrically insulated from the first electrode element, is formed as a metallization layer. By way of example, the metallization layer is provided from a polysilicon material.
According to yet another preferred refinement of the present invention, between the substrate and the first electrode element is arranged an interlayer system, which includes a barrier layer, which has been applied to the substrate, and a catalyst layer, which has been applied to the barrier layer and on which the first electrode element can be grown. It is preferable for the catalyst layer to contain at least one element from an iron group (Fe, Ni, Co), in such a manner that the first electrode element grows in the form of a carbon nanotube (CNT). In a further aspect of the present invention, the catalyst layer contains a silicide-forming material, such as for example Au, Pt, Ti, in such a manner that a silicon nanowire or a form of nanowire that is different grows and serves as the first electrode element.
According to a further aspect of the present invention, the insulation layer, which is applied to the first electrode element, is produced by means of chemical vapor deposition. In another preferred refinement of the present invention, the insulation layer, which is applied to the first electrode element, is produced by means of atomic layer deposition (ALD).
According to yet another preferred refinement of the present invention, the first electrode element, which is electrically connected to the substrate, is grown on the substrate by means of chemical vapor deposition (CVD).
By way of example, the substrate is provided from a silicon material. It is advantageous if the second electrode element, which is electrically insulated from the first electrode element and is applied to the insulation layer, is provided from a polysilicon or other metallic material.
Exemplary embodiments of the invention are illustrated in the drawings and explained in more detail in the description below.
In the drawings:
In the figures, identical reference numerals denote identical or functionally equivalent components or steps.
In process step a) shown in
It should be noted that the transistor illustrated is only an example and can be designed in various ways. According to the invention, in process step a) a cutout 114, in which the memory cell is formed in the further process steps c) to d), is etched into the oxide layer 109. The trench structure 114 is etched into the oxide layer 109, for example by an anisotropic etch.
In process step b), which follows process step a), first of all a barrier layer 105 is deposited in the cutout 114. A barrier layer 105 of this type serves as contact material to the substrate 101 below, which is preferably formed from silicon. It should be noted that the barrier layer, which acts as a diffusion barrier, can be deposited before or after deposition of the oxide layer 109. After deposition of the barrier layer 105, a catalyst layer 106, which serves as a catalyst for the growth of nanotubes according to the invention in order to increase a capacitance of the memory cell element, is applied. Like the barrier layer 105, the catalyst layer 106 is selected in such a manner as to provide sufficient electrical contact to the silicon substrate 101.
Process step c) shown in
Furthermore, it is possible for the catalyst layer 106 to contain a silicide-forming material, such as for example Au, Pt or Ti, in such a manner that the first electrode element 102 grows as a silicon nanowire on the catalyst layer 106. According to the invention, the first electrode element, which is formed as a nanotube (NT), projects out of the surface of the oxide layer 109.
It is advantageously possible, by means of the growth process of the nanotubes, to produce very thin electrode elements of considerable length. The length of carbon nanotubes is typically 0.5 mm, while their diameter is 10 nm. It should be noted that the feature size of the diameter of the nanotubes is below the resolution of the standardized lithography processes which are used to produce the memory cells and/or the associated transistors with their gate elements, drain elements and source elements.
This means that by means of the patterning with carbon nanotubes and/or silicon nanowires, it is possible to introduce sub-lithographic features using standardized lithography processes. On account of the high mechanical stability of the first electrode element, which is designed as a nanotube, it is possible for this element to project up to 0.5 mm out of the surface of the oxide layer 109.
Process step d) shown in
Furthermore, it is advantageous to use atomic layer deposition (ALD) in order to obtain particularly thin dielectric layers. Since the capacitance of the memory cell obtained and the thickness of the dielectric layer are inversely proportional to one another, the capacitance is in this way increased.
In particular, the method according to the invention also provides an increase in the capacitance by increasing the electrode surface area, since the first electrode element 102 now projects out of the surface of the oxide layer 109. A second electrode element 104 is applied as counterelectrode to the structure obtained, i.e. substantially to the deposited insulation layer 103. The second electrode element 104 is preferably formed as a metallization layer. By way of example, polysilicon is used as material for the second electrode element 104.
It should be noted that an interlayer system 108 which is arranged between the substrate 101 and the first electrode element 102 and which comprises a barrier layer 105 applied to the substrate and a catalyst layer 106 deposited on the barrier layer 105 can be replaced by other layer systems.
One important feature of the interlayer system 108 is that it provides sufficient electrical contact between the first electrode element and the silicon substrate as a base electrode. The circled region denoted by reference numeral 107 in
Therefore, one major benefit of the method according to the invention is that it is possible to produce memory devices with memory cells in which the central electrode can be provided so as to project out of a surface of the oxide layer 109 with a length of several tenths of a micrometer and a uniform diameter. In particular, it is advantageous that the carbon nanotubes used and/or the silicon nanowires have a high electrical conductivity. A further advantage is that the nanotubes formed as the first electrode element 102 are matched to the hole diameter which has been etched into the oxide layer 109 in process step a). Unlike in conventional methods, the method according to the invention allows three-dimensional patterning using standardized 2D coating processes. Whereas there are limits on the extent to which a capacitance of a memory cell can be increased by increasing the dielectric constant of the insulation layer 103 functioning as a dielectric, i.e. the dielectric constant is limited to typically between 10 and 25, it is possible to increase the capacitance by growing the first electrode element 102 out of the plane of the oxide layer 109 as a result of the increase in surface area, whereas the lateral dimensions of the memory device are not increased.
Although the present invention has been described above on the basis of preferred exemplary embodiments, it is not restricted to these embodiments, but rather can be modified in numerous ways.
Also, the invention is not restricted to the possible applications mentioned.
In the figures, identical reference numerals denote identical or functionally equivalent components or steps.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10344814.4 | Sep 2003 | DE | national |
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/EP04/10085 | Sep 2004 | US |
| Child | 11363991 | Feb 2006 | US |
