Patent Application
20110161553
Various types of memories are designed to be erased and programmed in large sections, and are generally referred to as flash memory. Such memory devices can sustain a limited number of erase cycles during their operational lifespan. The number of erase cycles that a flash memory can sustain and continue to reliably operate may be expressed as the endurance of the memory device. Generally, a given memory cell of a flash memory device can currently be erased between 10,000 and 100,000 times before it fails to reliably operate. The endurance of a memory device may depend on the semiconductor processes used to manufacture the device, and the architecture of the memory device.
Flash memory is common in various conventional electronic devices. When the endurance of the flash memory is exceeded, the performance of the flash memory and/or the electronic device containing the flash memory may be adversely impacted, or it may even stop operating. Accordingly, there is a continued need for improving the endurance of memory devices such as flash memory.
Embodiments of the present technology are directed toward memory device wear-leveling techniques. In one embodiment, a wear-level method includes translating a logical block address and a length in the logical block address that specifies a number of logical pages, to a plurality of physical addresses for accessing one or more memory devices. Each physical address includes a device address, a logical unit address, a block address, and a page address.
In another embodiment, a wear-leveling memory controller discovers a persistent state of one or more memory devices. The memory controller also builds and caches persistent state parameters for each logical unit of a given memory device if a persistent state is not discovered for the given memory device.
Embodiments of the present technology are illustrated by way of example and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
Reference will now be made in detail to the embodiments of the present technology, examples of which are illustrated in the accompanying drawings. While the present technology will be described in conjunction with these embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present technology, numerous specific details are set forth in order to provide a thorough understanding of the present technology. However, it is understood that the present technology may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present technology.
Referring to
The circuit and memory cell architecture of the block programmable memory is such that new data is written to erased physical blocks 120 of the block programmable memory 230. Generally, if data is to be written to a physical block 120 that already contains data, then the physical block 120 has to be erased before the new data is programmed. If the blocks 120 of a block programmable memory 230 are written directly from software, non-uniform address patterns can result in unequal numbers of erasures across the plurality of physical blocks 120 of the memory 230. For example, if one address pattern is continuously written to, than the number of erasures would eventually exceed the endurance limit of the given physical block 120. Exceeding the endurance limit of the block 120 would reduce the operating lifetime of the block programmable memory device 230.
The wear-leveling techniques, in accordance with embodiments of the present technology, map logical addresses that are generated by software to physical addresses in the block programmable memory device. The mapping is done such that over time all physical blocks in the block programmable memory device are subjected to almost the same number of erasure cycles regardless of software access patterns. The wear-leveling techniques significantly increase the operating lifetime of block programmable memory devices. In one implementation, the wear-level techniques are implemented for flash memory devices compliant to the Open NAND Flash Interface (ONFI) 2.0 specification.
Referring now to
The electronic device 210 includes one or more processing units 220 communicatively coupled to system memory 230, a memory controller 240 and a plurality of block programmable memory devices 260 by one or more communication buses 260. The electronic device 210 may also include other circuits, such as input/output devices 270 and the like. In one implementation, the plurality of block programmable memory devices 250 may be flash memory devices. In one implementation, the memory controller 240 may enable access to the system memory 230, the block programmable memory devices 250 and other memory device of the electronic device 210. One or more of the block programmable memory devices 250 may be internal or external to the electronic device 210. The memory controller 240 may be integral to one or more other circuits of the electronic device 210 or may be discrete devices. For example, the memory controller may be integral to one or more memory devices, one or more processors, one or more other circuits (e.g., northbridge chip, graphics processing unit) and/or may be a separate dedicated controller. The memory controller may be implemented by one or more means, such as hardware, firmware, and/or computing device readable instructions (e.g., software) and a processing unit. In another implementation, the electronic device 210 may include a plurality of memory controllers, wherein one of the memory controllers is a dedicated block programmable memory controller 240.
The block programmable memory devices 250 may include one or more devices having different operating parameters. For example, the memory devices 250 may include one or more devices having different storage capacity (e.g., pages), having different numbers of blocks, different spare blocks, different timing requirements, and/or the like.
The block programmable memory controller 240 includes a cache 280 for caching persistent state parameters of the one or more block programmable memory device 250. The block programmable memory controller 240 may cache persistent state parameters such as bad block data in a bad block data structure, mapping data in a mapping data structure, spare block data in a spare block data structure, and/or the like for the one or more block programmable memory devices 250. The persistent state parameter cache 280 may be separate or may be integral to the block programmable memory controller 240. The block programmable memory controller 240 utilizes the cached persistent state parameters 280 for processing one or more memory access commands including translating a logical block address and length that specifies an integral number of logical pages in a logical address, to a plurality of physical addresses for accessing one or more memory devices 250, each physical address including a device address, a logical unit address, a block address, and a page address. In addition, the block address includes one or more interleaved address bits. The block programmable memory controller 240 updates the cached persistent state parameters 280 and then periodically journals the persistent state parameters in the block programmable memory devices 250 to improve the wear-leveling of the block programmable memory devices 250.
Referring now to
The logical address, used by software to access data, includes a logical block address (LBA) and an integral number of logical pages specified by a length parameter. The physical address includes a device identifier (e.g., chip enable), a logical unit address, a block address and a page address. The lower order bits of the block address include one or more interleaved address bits.
The physical memory space typically includes a plurality of block programmable memory devices as illustrated in
The translation method has the flexibility to create different mappings across multiple block programmable memory devices for increased performance and reliability as compared to conventional wear-leveling techniques. In addition to address translation, the method supports the initialization of block programmable device and discovery of persistent states, the detection and management of bad physical blocks, spare block allocation, management and garbage collection, and the flexibility to avoid non-sequential programming of physical pages in a block.
Referring now to
The method begins with reading a parameter page of a plurality of block programmable memory devices, at 410. The parameter page includes parameters of the respective memory device, such as the number of LUNs, the number of blocks per LUN, the page size, the number of spare bytes per page, ECC bytes supported (e.g., strap option), and/or the like. For each attached memory device 414-425, a given physical block for each LUN in a device is read, at 430. In one implementation, block 0 of each LUN is read. At 435, the block type signature of the given block of each LUN is checked to determine if it has already been initialized.
If the given block of each LUN is already initialized, the initialization parameters are detected and cached. In one implementation, the most recent bad block table data structure is detected and cached for each LUN of each attached device, at 440. At 445, the most recent mapping table data structure is also detected and cached for each LUN of each attached device. At 450, the most recent spare block table data structure is also detected and cached for each LUN of each attached device. The parameters are cached so that the given block which stores the initialization parameters does not have to be written to each time the parameters are updated, and therefore improves the wear-leveling of the memory device.
If the given block of each LUN has not been initialized, the LUN is initialized and the initialization data is cached. In one implementation, the bad blocks are detected and a bad block table data structure is built and cached, at 455. At 460, a mapping table data structure mapping logical block addresses to physical block addresses is also built and cached. At 465, a spare block table data structure is also built and cached.
At 470, one or more memory access commands may be processed. Various background tasks may also be performed, at 475. The memory access commands are processed utilizing the address translation method described above with reference to FIG. 3. The background tasks may include garbage collection, updating the mapping or spare tables, erasing blocks, updating erase counts, journaling the mapping, spare and/or bad block table, and/or the like. Journaling the mapping table, spare table and bad block table data structures provides for persistent storage of the data. The data structures are journaled utilizing the address translation method described above with reference to
The wear-leveling techniques, in accordance with embodiments of the present technology, advantageously uses system memory map table structures to support large capacity (e.g., hundreds of gigabytes) and high performance block programmable memory, such as ONFI flash memory devices. The map data structures also advantageously have flexible semantics to support multiple instances of memory controllers. This helps in minimizing the size of firmware implementing the ware-level techniques. In accordance with embodiment of the present technology, the indexing of virtual address tuple (LBA, Length) has a programmable hash function that advantageously creates various options for interleaving mapped physical addresses across the same or different target memory devices.
The foregoing descriptions of specific embodiments of the present technology have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the present technology and its practical application, to thereby enable others skilled in the art to best utilize the present technology and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.
