MEMORY DEVICE

Abstract

A memory device includes a plurality of memory cells, where each memory cell is configured to be in an erased state or one of a plurality of program states according to data stored therein. The memory device also includes a peripheral circuit configured to, in a program operation on the plurality of memory cells, perform a first program voltage application operation on first memory cells, the first memory cells being to be programmed to first respective program states. The peripheral circuit is also configured to perform, after the first program voltage application operation, a pre-program voltage application operation on second memory cells, the second memory cells being to be programmed to second respective program states.

Description

Claims

1. A memory device comprising: a plurality of memory cells each configured to be in an erased state or one of a plurality of program states according to data stored therein; anda peripheral circuit configured to, in a program operation on the plurality of memory cells, perform a first program voltage application operation on first memory cells among the plurality of memory cells, the first memory cells being to be programmed to first respective program states; andperform, after the first program voltage application operation, a pre-program voltage application operation on second memory cells among the plurality of memory cells, the second memory cells being to be programmed to second respective program states.

2. The memory device according to claim 1, wherein the peripheral circuit is configured to perform a first verify voltage application operation after the pre-program voltage application operation is performed.

3. The memory device according to claim 1, wherein the peripheral circuit is configured to include in the second respective program states a most significant program state from among the first respective program states.

4. The memory device according to claim 1, wherein the peripheral circuit is configured to: determine the first memory cells on the basis of program data received from a device external to the peripheral circuit, andperform a first program setup operation on the first memory cells before performing the first program voltage application operation.

5. The memory device according to claim 1, wherein the peripheral circuit is configured to perform a data conversion operation in parallel with the first program voltage application operation.

6. The memory device according to claim 5, wherein the data conversion operation includes converting the program data received from a device external to the peripheral circuit into converted data.

7. The memory device according to claim 6, wherein the peripheral circuit is configured to: determine the second memory cells on the basis of the converted data, andperform a pre-program setup operation on the second memory cells before performing the pre-program voltage application operation.

8. The memory device according to claim 1, wherein the peripheral circuit is configured to perform a pre-program setup operation in parallel with the first program voltage application operation.

9. The memory device according to claim 8, wherein the peripheral circuit is configured to determine the second memory cells on the basis of program data received from a device external to the peripheral circuit.

10. The memory device according to claim 9, wherein the peripheral circuit is configured to perform a data conversion operation in parallel with the pre-program voltage application operation,wherein the data conversion operation includes converting the program data received from a device external to the peripheral circuit into converted data.

11. A memory device comprising: a plurality of memory cells each configured to be in an erased state or one of a plurality of program states according to data stored therein; anda peripheral circuit configured to, in a program operation on the plurality of memory cells: perform a first program voltage application operation on first memory cells among the plurality of memory cells;perform a pre-program voltage application operation on second memory cells among the first memory cells; andperform a data conversion operation in parallel with the pre-program voltage application operation.

12. The memory device according to claim 11, wherein the peripheral circuit is configured to perform a first verify voltage application operation after performing the pre-program voltage application operation.

13. The memory device according to claim 11, wherein the peripheral circuit is configured to: determine as the first memory cells at least a portion of the plurality of the memory cells to be in first respective program states, anddetermine as the second memory cells at least a portion of the first memory cells that are to be in respective selected program states.

14. The memory device according to claim 13, wherein the selected program states include a most significant program state among the plurality of program states.

15. The memory device according to claim 11, wherein the peripheral circuit is configured to: determine the first memory cells on the basis of program data received from a device external to the peripheral circuit, andperform a first program setup operation on the first memory cells before performing the first program voltage application operation.

16. The memory device according to claim 11, wherein the peripheral circuit is configured to: determine the second memory cells on the basis of program data received from a device external to the peripheral circuit, andperform a pre-program setup operation in parallel with the first program voltage application operation.

17. The memory device according to claim 11, wherein the data conversion operation includes converting program data received from a device external to the peripheral circuit into converted data.

18. A memory device comprising: a plurality of memory cells each configured to be in an erased state or one of a plurality of program states according to data stored therein; anda peripheral circuit configured to, in a program operation on the plurality of memory cells: determine first memory cells among the plurality of memory cells to apply a first program voltage to program the first memory cells to first respective program states, anddetermine second memory cells from among the first memory cells to be in respective selected program states among the program states while the first program voltage is applied.

19. The memory device according to claim 18, wherein, after determining the second memory cells, the peripheral circuit is configured to apply a pre-program voltage higher than the first program voltage to the second memory cells.

20. The memory device according to claim 19, wherein the peripheral circuit is configured to convert program data received from a device external to the peripheral circuit into converted data while applying the pre-program voltage.

21. The memory device according to claim 20, wherein the peripheral circuit is configured to apply a first verify voltage to the plurality of memory cells after applying the pre-program voltage.