Patent Application
20190148382
The present invention relates to memory devices and method of manufacturing the same, and more specifically, to memory devices with improved adhesion between the tungsten layer and the pre-metal layer for reducing the resistance and method of manufacturing the same.
A semiconductor device such as a DRAM (Dynamic Random Access Memory) has a memory cell area and a peripheral circuit area formed on a principal surface of a semiconductor substrate. The memory cell area includes a plurality of memory cells each having a cell transistor and a storage node. The peripheral circuit area may include various peripheral circuits for performing operations such as read operation and write operation to the memory cells in the memory cell area.
For the past few years, the size reduction has been remarkably progressing in the field of DRAMs. Capacitors used in such DRAMs are formed into a three-dimensional structure in order to ensure a large capacity. The cylinder-type or pillar-type capacitors may provide larger plate area compared to those of the hole-type capacitors. This type of capacitor is formed by providing supporting structures extending vertically from the substrate with a lower electrode, a capacity insulating film, an upper electrode layer and a top plate covering thereon.
While the top plate of the capacitor is formed preferably of silicon germanium (SiGe), a conductive metal layer, such as a tungsten (W) layer, would be formed on the SiGe top plate to reduce the resistance of the cell matrix before the deposition of the subsequent pre-metal dielectric layer. However, poor adhesion between the tungsten layer and the silicon-based pre-metal layer may induce cracking issues at sidewalls of the capacitor structures, especially after packaging. The increased strain in the packaging stage may separate and peel the pre-metal dielectric layer from the tungsten layer.
The following paragraphs present a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
In order to solve the issue of poor adhesion between the tungsten layer and the pre-metal dielectric layer, the approach of the present invention is to form a tungsten nitride layer and/or a tungsten oxide layer on the tungsten layer. The tungsten compound layers have better adhesive property with the silicon-based dielectric layer.
In one aspect of the embodiments, there is provided a method of manufacturing memory devices which includes the steps of providing a substrate with multiple capacitors, wherein the capacitor includes a lower electrode layer, an insulating layer, an upper electrode layer and a top plate, forming a tungsten layer on the top plate, performing a nitriding plasma treatment to the tungsten layer to form a tungsten nitride layer, and forming a dielectric layer on the tungsten nitride layer.
In another aspect of the embodiments, there is provided a method of manufacturing memory devices which includes the steps of providing a substrate with multiple capacitors, wherein the capacitor includes a lower electrode layer, an insulating layer, an upper electrode layer and a top plate, forming a tungsten layer on the top plate, performing an oxidizing plasma treatment to the tungsten layer to form a tungsten oxide layer, and forming a dielectric layer on the tungsten oxide layer.
In still another aspect of the embodiments, there is provided a memory device which includes a substrate, a lower electrode layer on the substrate, an insulating layer on the lower electrode layer, an upper electrode layer on the insulating layer, a top plate on the upper electrode layer, a tungsten layer on the top plate, a tungsten nitride layer on the tungsten layer, and a dielectric layer directly on the tungsten nitride layer.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Features will become apparent to those of ordinary skill in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which:
It should be noted that all the figures are diagrammatic. Relative dimensions and proportions of parts of the drawings have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments.
Advantages and features of embodiments may be understood more readily by reference to the following detailed description of preferred embodiments and the accompanying drawings. Embodiments may, however, be embodied in many different forms and should not be construed as being limited to those set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey exemplary implementations of embodiments to those skilled in the art, so embodiments will only be defined by the appended claims. Like reference numerals refer to like elements throughout the specification.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Hereinafter, a manufacturing process of memory devices according to present invention will be described with reference to
First, please refer to
Word lines WL are formed in advance in the substrate 100 to serve as gates for controlling the switch of memory devices. Dopants such as p-type dopants or n-type dopants are doped into the actives region at both sides of the word lines WL to form source/drain S/D. Storage node contacts 104 are formed on source/drain S/D to further connect contact pads 106 and capacitors formed thereon. The stack of each source/drain S/D, storage node contact 104 and contact pad 106 are spaced apart by spacers 108 and each corresponds to one capacitor unit above.
A capacitor structure 110 is formed on the cell region 101 with multiple capacitor units 112 connecting respectively with the contact pads 106 below. In the embodiment, each capacitor unit 112 includes a lower electrode 114, an insulating layer 116 and an upper lower electrode layer 118. The material of the lower electrode layer 114 and upper lower electrode layer 118 may be titanium nitride (TiN). The insulating layer 116 may be a stack of alternating ZrO2—Al2O3—ZrO2 (ZAZ) films. Supporting structures 120 are formed surrounding the capacitor units 112 to provide structural strength and separate them from each other.
A conductive top plate 122 is formed on the surface of the upper electrode layer 118 of the capacitor structure 110. The material of top plate 122 may be silicon, silicon germanium (SiGe) or silicon phosphorus (SiP) with the doping of boron (B) or phosphorus (P). A tungsten (W) layer 124 is formed on the top plate 122 to reduce the resistance of cell matrix. The tungsten layer 124 may be formed by plasma-enhanced chemical vapor deposition (PECVD) and sputtering with a thickness about 700 angstrom (Å). In addition, a thin native tungsten oxide layer (not shown) may grow on the surface of the tungsten layer 124 because the wafer surface is exposed to the air environment with the coexistence of oxygen and water or moisture at room temperature.
Please refer to
In another embodiment of the present invention, please refer to
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In the present invention, since the tungsten nitride layer 126 or the tungsten oxide layer 128 is intermediate between the tungsten layer 124 and pre-metal dielectric layer 130, the problem of poor adhesion between metal-based tungsten layer 124 and silicon-based pre-metal dielectric layer 130 is properly solved. The tungsten nitride layer 126 or the tungsten oxide layer 128 is used instead of the tungsten layer 124 to construct better bonding with the pre-metal dielectric layer 130 to achieve better adhesion.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
