Claims
- 1. A method for overwriting data in a memory device comprising a first and second set of memory cells, the method comprising:
(a) storing data in a first set of memory cells in a memory device; (b) storing an error code in a second set of memory cells in the memory device, the error code representing the data stored in the first set of memory cells; (c) writing a destructive pattern into at least some of the first set of memory cells, wherein the error code no longer represents the data stored in the first set of memory cells after the destructive pattern is written; and (d) disregarding the error code.
- 2. The method of claim 1, wherein (d) comprises disabling a comparison of the data stored in the first set of memory cells with the error code.
- 3. The method of claim 1 further comprising comparing the data stored in the first set of memory cells with the error code and detecting that the error code does not represents the data stored in the first set of memory cells, and wherein (d) comprises ignoring the detection.
- 4. The method of claim 3, wherein the data stored in the first set of memory cells is compared with the error code when the data is read.
- 5. The method of claim 3, wherein the data stored in the first set of memory cells is compared with the error code when the destructive pattern is written into at least some of the first set of memory cells.
- 6. The method of claim 1 further comprising storing an indication that the destructive pattern was written into at least some of the first set of memory cells, and wherein the error code is disregarded in (d) in response to a determination that the indication was stored.
- 7. The method of claim 6, wherein the indication comprises a flag bit designated in a file listing.
- 8. The method of claim 6, wherein the indication comprises an entry stored in a table.
- 9. The method of claim 1 further comprising recognizing that a destructive pattern is stored in the first set of memory cells, and wherein the error code is disregarded in (d) in response to the recognition.
- 10. The method of claim 1, wherein the error code comprises an error checking and correcting (ECC) code.
- 11. The method of claim 1, wherein the memory device is logically organized into a plurality of lines, and wherein a line comprises the first and second sets of memory cells.
- 12. The method of claim 1, wherein the first set of memory cells comprises a minimum number of memory cells that can be written into during a write operation.
- 13. The method of claim 1, wherein the memory device comprises a write-once memory device.
- 14. The method of claim 1, wherein the memory device comprises a three-dimensional write-once memory device.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional of application Ser. No. 09/748,589, filed Dec. 22, 2000, which is a continuation-in-part of U.S. patent application Ser. No. 09/662,953, filed Sep. 15, 2000 (now abandoned), each of which is incorporated by reference herein.
Divisions (1)
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Number |
Date |
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| Parent |
09748589 |
Dec 2000 |
US |
| Child |
10253089 |
Sep 2002 |
US |
Continuation in Parts (1)
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Number |
Date |
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09662953 |
Sep 2000 |
US |
| Child |
09748589 |
Dec 2000 |
US |