Claims
- 1. A cache defining arrangement comprising an arrangement having at least one of a memory hole modification scheme, and a mixed technique scheme where differing non-memory-hole portions of cacheable memory space is defined with at least two mutually different defining techniques.
- 2. A cache defining arrangement as claimed in claim 1, comprising the memory hole modification scheme, where an initially projected memory hole size is modified to a different size for defining cacheable memory space.
- 3. A cache defining arrangement as claimed in claim 2, wherein the memory hole modification scheme increases the initially projected memory hole size in predetermined binary increments to modify to a different size for defining cacheable memory space.
- 4. A cache defining arrangement as claimed in claim 1, comprising the mixed technique scheme to use a bottom-up scheme to define a first non-memory- hole portion of cacheable memory space, and to use a top-down scheme to define a second non-memory-hole portion, wherein in the bottom-up scheme, mainly substantially additive blocks of cacheable memory space are defined so as to cumulatively define the first non-memory-hole portion, and wherein in the top-down scheme, an oversized block of cacheable memory space is defined, and then mainly substantially subtractive blocks of cacheable memory space are subtracted so as to subtractively define the second non-memory-hole portion.
- 5. A cache defining arrangement comprising an arrangement having both of a memory hole modification scheme, and a mixed technique scheme where differing non-memory-hole portions of cacheable memory space is defined with at least two mutually different defining techniques.
- 6. A cache defining arrangement as claimed in claim 5, wherein in the memory hole modification scheme, an initially projected memory hole size is modified to a different size for defining cacheable memory space.
- 7. A cache defining arrangement as claimed in claim 6, wherein tile memory hole modification scheme increases the initially projected memory hole size in predetermined binary increments to modify to a different size for defining cacheable memory space.
- 8. A cache defining arrangement as claimed in claim 5, wherein the mixed technique scheme is to us e a bottom-up scheme t o define a first non-memory-hole portion of cacheable memory space , and to use a top-down scheme to define a second non-memory-hole portion, wherein in the bottom-up scheme, mainly substantially additive blocks of cacheable memory space are defined so as to cumulatively define the first non-memory-hole portion, and wherein in the top-down scheme, an oversized block of cacheable memory space is defined, and then mainly substantially subtractive blocks of cacheable memory space are subtracted so as to subtractively define the second non-memory-hole portion.
- 9. A cache defining arrangement as claimed in claim 5, wherein the cache defining arrangement is adapted to run each of the memory hole modification scheme and the mixed technique scheme, sequentially one after another.
- 10. A cache defining arrangement as claimed in claim 5, wherein the mixed technique scheme is adapted to run cacheable memory space defining procedures for the differing non-memory-hole portions of cacheable memory space, at least partially in parallel with one another.
- 11. A cache defining arrangement as claimed in claim 5, wherein the cache defining arrangement comprises a predetermined selection algorithm to select which result from the memory hole modification scheme and the mixed technique scheme, should be used for defining the cacheable memory space.
- 12. A cache defining arrangement as claimed in claim 5, wherein the mixed technique scheme is adapted to run at least two mutually different cache defining schemes for each non-memory-hole portion of cacheable memory space, and to select which result from the at least two mutually different cache defining schemes should be used for defining the cacheable memory space.
- 13. A cache defining arrangement as claimed in claim 5, wherein the mixed technique scheme is adapted to separately run for a plurality of different size combinations of the non-memory-hole portions of cacheable memory space, and to select which result size combination of the non-memory hole portions should be used for defining the cacheable memory space.
- 14. A cache defining arrangement as claimed in claim 5, wherein the cache defining arrangement is adapted to run a default scheme for defining the cacheable memory space to determine whether the cacheable memory space can be defined within predetermined resources, and if not, the cache defining arrangement is adapted to run at least one of the memory hole modification scheme and the mixed technique scheme for defining the cacheable memory space.
- 15. A cache defining arrangement as claimed in claim 5, comprising a selection arrangement adapted to allow selection to run only a predetermined default scheme for defining the cacheable memory space.
- 16. A system comprising a cache defining arrangement comprising an arrangement having at least one of a memory hole modification scheme, and a mixed technique scheme where differing non-memory-hole portions of cacheable memory space is defined with at least two mutually different defining techniques.
- 17. A system as claimed in claim 16, comprising the memory hole modification scheme, where an initially projected memory hole size is modified to a different size for defining cacheable memory space.
- 18. A system as claimed in claim 17, wherein the memory hole modification scheme increases the initially projected memory hole size in predetermined binary increments to modify to a different size for defining cacheable memory space.
- 19. A system as claimed in claim 16, comprising the mixed technique scheme to use a bottom-up scheme to define a first non-memory-hole portion of cacheable memory space, and to use a top-down scheme to define a second non- memory-hole portion, wherein in the bottom-up scheme, mainly substantially additive blocks of cacheable memory space are defined so as to cumulatively define the first non-memory-hole portion, and wherein in the top-down scheme, an oversized block of cacheable memory space is defined, and then mainly substantially subtractive blocks of cacheable memory space are subtracted so as to subtractively define the second non-memory-hole portion.
- 20. A system comprising a cache defining arrangement comprising an arrangement having both of a memory hole modification scheme, and a mixed technique scheme where differing non-memory-hole portions of cacheable memory space is defined with at least two mutually different defining techniques.
- 21. A system as claimed in claim 20, wherein in the memory hole modification scheme, an initially projected memory hole size is modified to a different size for defining cacheable memory space.
- 22. A system as claimed in claim 21, wherein the memory hole modification scheme increases the initially projected memory hole size in predetermined binary increments to modify to a different size for defining cacheable memory space.
- 23. A system as claimed in claim 21, wherein the mixed technique scheme is to use a bottom-up scheme to define a first non-memory-hole portion of cacheable memory space, and to use a top-down scheme to define a second non-memory-hole portion, wherein in the bottom-up scheme, mainly substantially additive blocks of cacheable memory space are defined so as to cumulatively define the first non- memory-hole portion, and wherein in the top-down scheme, an oversized block of cacheable memory space is defined, and then mainly substantially subtractive blocks of cacheable memory space are subtracted so as to subtractively define the second non-memory-hole portion.
- 24. A system as claimed in claim 21, wherein the cache defining arrangement is adapted to run each of the memory hole modification scheme and the mixed technique scheme, sequentially one after another.
- 25. A system as claimed in claim 21, wherein the mixed technique scheme is adapted to run cacheable memory space defining procedures for the differing non- memory-hole portions of cacheable memory space, at least partially in parallel with one another.
- 26. A system as claimed in claim 21, wherein the cache defining arrangement comprises a predetermined selection algorithm to select which result from the memory hole modification scheme and the mixed technique scheme should be used for defining the cacheable memory space.
- 27. A system as claimed in claim 21, wherein the mixed technique scheme is adapted to run at least two different cache defining schemes for each non- memory-hole portion of cacheable memory space, and to select which result from the at least two mutually different cache defining schemes should be used for defining the cacheable memory space.
- 28. A system as claimed in claim 21, wherein the mixed technique scheme is adapted to separately run for a plurality of different size combinations of the non- memory-hole portions of cacheable memory space, and to select which result size combination of the non-memory hole portions should be used for defining the cacheable memory space.
- 29. A system as claimed in claim 21, wherein the cache defining arrangement is adapted to run a default scheme for defining the cacheable memory space to determine whether the cacheable memory space can be defined within predetermined resources, and if not, the cache defining arrangement is adapted to run at least one of the memory hole modification scheme and the mixed technique scheme for defining the cacheable memory space.
- 30. A system as claimed in claim 21, comprising a selection arrangement adapted to allow selection to run only a predetermined default scheme for defining the cacheable memory space.
- 31. A cache defining method comprising;
defining cacheable memory space using at least one of a memory hole modification scheme, and a mixed technique scheme where differing non-memory- hole portions of the cacheable memory space is defined with at least two mutually different defining techniques.
- 32. A cache defining method as claimed in claim 31, comprising:
applying the memory hole modification scheme, where an initially projected memory hole size is modified to a different size for defining cacheable memory space.
- 33. A cache defining method as claimed in claim 32, wherein the memory hole modification scheme increases the initially projected memory hole size in predetermined binary increments to modify to a different size for defining cacheable memory space.
- 34. A cache defining method as claimed in claim 31, comprising:
applying the mixed technique scheme to use a bottom-up scheme to define a first non-memory-hole portion of cacheable memory space, and to use a top-down scheme to define a second non-memory-hole portion, wherein in the bottom-up scheme, mainly substantially additive blocks of cacheable memory space are defined so as to cumulatively define the first non-memory-hole portion, and wherein in the top-down scheme, an oversized block of cacheable memory space is defined, and then mainly substantially subtractive blocks of cacheable memory space are subtracted so as to subtractively define the second non-memory-hole portion.
- 35. A cache defining method comprising;
defining cacheable memory space using both of a memory hole modification scheme, and a mixed technique scheme where differing non-memory-hole portions of the cacheable memory space is defined with at least two mutually different defining techniques.
- 36. A cache defining method as claimed in claim 35, wherein in the memory hole modification scheme, an initially projected memory hole size is modified to a different size for defining cacheable memory space.
- 37. A cache defining method as claimed in claim 36, wherein the memory hole modification scheme increases the initially projected memory hole size in predetermined binary increments to modify to a different size for defining cacheable memory space.
- 38. A cache defining method as claimed in claim 35, wherein the mixed technique scheme uses a bottom-up scheme to define a first non-memory-hole portion of cacheable memory space, and uses a top-down scheme to define a second non-memory-hole portion, wherein in the bottom-up scheme, mainly substantially additive blocks of cacheable memory space are defined so as to cumulatively define the first non-memory-hole portion, and wherein in the top-down scheme, an oversized block of cacheable memory space is defined, and then mainly substantially subtractive blocks of cacheable memory space are subtracted so as to subtractively define the second non-memory-hole portion.
- 39. A cache defining method as claimed in claim 35, comprising:
running each of the memory hole modification scheme and the mixed technique scheme, sequentially one after another.
- 40. A cache defining method as claimed in claim 35, comprising:
running cacheable memory space defining procedures for the differing non- memory-hole portions of cacheable memory space, at least partially in parallel with one another.
- 41. A cache defining method as claimed in claim 35, comprising:
running a predetermined selection algorithm to select which result from the memory hole modification scheme and the mixed technique scheme should be used for defining the cacheable memory space.
- 42. A cache defining method as claimed in claim 35, wherein the mixed technique scheme running at least two mutually different cache defining schemes for each non-memory-hole portion of cacheable memory space, and selecting which result from the at least two mutually different cache defining schemes should be used for defining the cacheable memory space.
- 43. A cache defining method as claimed in claim 35, wherein the mixed technique scheme being separately run for a plurality of different size combinations of the non-memory-hole portions of cacheable memory space, and to select which result size combination of the non-memory hole portions should be used for defining the cacheable memory space.
- 44. A cache defining method as claimed in claim 35, comprising:
first running a default scheme for defining the cacheable memory space to determine whether the cacheable memory space can be defined within predetermined resources, and if not, then running at least one of the memory hole modification scheme and the mixed technique scheme for defining the cacheable memory space.
- 45. A cache defining method as claimed in claim 35, comprising:
running a selection arrangement adapted to allow selection to run only a predetermined default scheme for defining the cacheable memory space.
- 46. A cache defining program embodied on a computer-readable medium, comprising an arrangement capable of running at least one of a memory hole modification scheme, and a mixed technique scheme where differing non-memory- hole portions of cacheable memory space is defined with at least two mutually different defining techniques.
- 47. A cache defining program embodied on a computer-readable medium, comprising an arrangement capable of running both of a memory hole modification scheme, and a mixed technique scheme where differing non-memory-hole portions of cacheable memory space is defined with at least two mutually different defining techniques.
CROSS-REFERENCE TO OTHER APPLICATIONS
[0001] This application is cross-referenced to U.S. patent application Ser. No. 09/608,182, filed Jun. 30, 2000, still pending.