The present application claims priority to European Patent Application No. 13290084.6, filed on Apr. 12, 2013; which is hereby incorporated herein by reference.
Interleaved memory is a technique for compensating the relatively slow speed of dynamic random access memory (relatively slow compared to a processor or group of processors). The processor can access alternative sections of memory simultaneously without needing to wait for them to be free. Multiple memory devices supply data at the same time. While one section of memory (a memory channel) is busy processing upon a word at a particular location, another section accesses the word at the next location. Interleaved memory subsystems have a number of memory channels that typically is a power of 2 (e.g., 2 memory channels, 4 memory channels, etc.).
Some implementations are directed to a memory interleaver that includes a channel selection unit to receive a system memory address for a memory request. The interleaver also includes a local memory address computation unit and a de-multiplexer. The channel selection unit examines a predetermined plurality (n) of bits in a memory address of a memory transaction and assigns the memory transaction to one of a plurality of memory channels in a multi-channel memory unit based on a state of the predetermined plurality of bits. Preferably, 2n is greater than the number of memory channels in the multi-channel memory unit.
In other examples, a system includes a requestor and a multi-channel memory unit. The memory unit receives memory transactions having system memory addresses from the requestor, examines a predetermined plurality (n) of bits in the system memory address, and assigns each memory transaction to one of a plurality of memory channels based on a state of the predetermined plurality of bits. Preferably, 2n is greater than the number of memory channels in the multi-channel memory unit.
A method may include examining a predetermined plurality (n) of bits in a memory address of a memory transaction, assigning the memory transaction to one of a plurality of memory channels in a multi-channel memory unit based on a state of the predetermined plurality of bits. 2n is greater than the number of memory channels in the multi-channel memory unit.
For a detailed description of various examples of the disclosure, reference will now be made to the accompanying drawings in which:
Various examples are shown and described herein. Although one or more of these examples may be preferred, the examples disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any example is meant only to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment.
The channel selection unit 132 examines various bits in the memory address to determine to which of the multiple memory channels to direct the memory transaction. The process to select a particular memory channel based on the particular bits within the memory address is described below. The demultiplexer 136 receives the memory transaction and control bits from the local DRAM address computation unit 134 to provides the transaction to the targeted memory channel.
The system memory 150 may be addressable using a 16-bit address, such as that shown in
In another example the channel selection unit may examine the five bits 7, 8, 9, 10, and 11 from the system memory address. The example in which five bits 7-11 are examined is discussed in greater detail below.
There are 32 possible values with five bits (00000, 00001, 00010, . . . 11111). For each frame 155, the frame can be divided into 32 elements based on the state of the five predetermined bits of the memory address.
For a 5-channel memory unit 110, the channel selection unit 132 assigns 6 elements 160 to each of four of the memory channels and 8 elements 160 to the fifth memory channel. In some implementations, four of the memory channels are wide I/O channels and the fifth channel is an external channel (a non-wide I/O channel which could be one of (but not only) DDR, DDR2, DDR3, LPDDR2 or LPDDR3). The four wide I/O channels may be numbered channels 0, 1, 2, and 3 and the external channel may be numbered channel 4. Thus, each of channels 0-3 is assigned 6 of the elements of each frame 155 and channel 4 is assigned 8 elements. Table I below provides an example of how the various elements 160 of a frame 155 are assigned based on the state of bits 7, 8, 9, 10, and 11. The numbers in each cell of the table refer to a memory channel number (memory channels 0-4 for a 5 channel memory unit).
Considering the assignment to channel 0 for address bits 11, 10, 9, 8, and 7 (upper left corner of Table I), this means that any memory address that has all 0's for those particular memory address bits is assigned by the channel selection unit 132 to channel 0. Thus, the second column of Table I illustrates that memory addresses in which bits 9, 8, and 7 are all 0 are assigned to channel 0. Further, the second from the right column shows that memory addresses with bits 11, 10, 9, 8, and 7 having the values [00110] and also are assigned to channel 0. It should also be readily apparent that the elements assigned to a particular memory channel for a given frame 155 are not all contiguous.
For a 6-channel memory unit 110, the channel selection unit 132 assigns 5 elements 160 to each of four of the memory channels and 6 elements each to the fifth and sixth memory channels. In some implementations, four of the memory channels are wide I/O channels and the fifth and sixth channels are external channel (a non-wide I/O channel). The four wide I/O channels may be numbered channels 0, 1, 2, and 3 and the external channels may be numbered channels 4 and 5. Thus, each of channels 0-3 is assigned 5 of the elements of each frame 155, channel 4 is assigned 6 elements and channel 5 is also assigned 6 elements. Table II below provides an example of how the various elements 160 of a frame 155 are assigned based on the state of bits 7, 8, 9, 10, and 11.
The local DRAM address computation unit 134 in
Table III below shows the mapping between memory addresses and the local DRAM addresses for an example with 5 memory channels selected using bits 11, 10, 9, 8 and 7 of the system memory address and two DRAM base addresses selected using bit 9 of the system memory address. The numbers in the cells are hexadecimal address values. In Table III BA0 and CHxBA1 refer to the first and second base address for the memory channel of the column they appear in.
For example, system memory address 0 (which means bits [11, 10, 9, 8, 7] are all 0 is assigned to channel 0 and maps to local address BA0+0 of channel 0 as shown in the upper left portion of Table III. Going down the first system memory column in Table III, address 400 has bits [11, 10, 9, 8, 7] that have a value of [01000] and system memory address 400 is assigned to local address BA0+80 of channel 0.
As illustrated above, interleaving is performed on a number of memory channels (e.g., 5 or 6) that is not a power of 2. Further, the number of elements in each frame of memory that is allocated to the various memory channels is greater than the number of memory channels. If n is 5 (5 bits in the memory address examined to assign transactions to memory channels), 2n is greater than the number of memory channels in the multi-channel memory unit. In the example above, 32 elements are allocated to 5 or 6 memory channels based on the state of a particular set of bits in the memory address.
The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.
Number | Date | Country | Kind |
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13290084.6 | Apr 2013 | EP | regional |