Patent Application
20250225067
This application claims priority under 35 USC 119 (a) to Korean Patent Application No. 10-2024-0003363 filed on Jan. 9, 2024 and to Korean Patent Application No. 10-2024-0060936 filed on May 9, 2024, each in the Korean Intellectual Property Office, the entire disclosures of which are incorporated by reference herein for all purposes.
The present disclosure relates to memory modules and a methods of operating the same.
Generally, a memory module provided as low-power mobile memory may be composed of two or more ranks. In other words, in a dual-rank structure, multiple semiconductor memory devices mounted on the memory module's substrate may be classified into two ranks, and the semiconductor memory devices belonging to the same rank may be accessed simultaneously.
Ultimately, a rank refers to a unit by which a memory controller may input and output data to and from the semiconductor memory devices. As the number of ranks increases, higher-capacity memories may be configured.
An embodiment provides a memory module in which a bandwidth is expanded, and a method of operating the same.
An embodiment provides a memory module in which input capacitance is reduced, and a method of operating the same.
According to an embodiment, a memory module includes a plurality of receivers commonly receiving signals. Each of the plurality of receivers includes an amplifier having a respective filter, and each amplifier is configured to selectively apply a bias filtering voltage through the respective filter. In an enabled receiver among the plurality of receivers, a filter bias terminal connected to the respective filter is selectively connected to a bias power terminal; and in a disabled receiver among the plurality of receivers, the filter bias terminal connected to the respective filter is selectively disconnected from the bias power terminal.
According to an embodiment, a memory module includes a first rank having first memory devices; a second rank having second memory devices; a power management chip supplying power to the first rank and the second rank; and a serial presence detection chip storing module information. Each of the first and second memory devices has at least one receiver, and the at least one receiver includes an amplifier amplifying differential input signals. When the first rank is enabled, a first filter bias terminal connected to a first high-pass filter of a first amplifier included in the first rank is selectively connected to a bias power terminal. When the second rank is disabled, a second filter bias terminal connected to a second high-pass filter of a second amplifier included in the second rank is selectively not connected to the bias power terminal.
According to an embodiment, a method of operating a memory module having a plurality of ranks includes adjusting a resistor or a capacitor of a high-pass filter receiving differential input signals from a receiver corresponding to each of the plurality of ranks according to a channel environment; and adjusting a bias applied to the high-pass filter. The adjusting of the bias includes applying a bias voltage to a filter bias terminal of a high-pass filter included in an enabled rank among the plurality of ranks.
The above and other embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
Hereinafter, illustrative embodiments of the present disclosure will be described by way of example with reference to the accompanying drawings.
A memory module according to an embodiment of the present disclosure may include an Alternating Current (AC) Coupled Booster (ACCB) with variable bandwidth and low input capacitance. The memory module may include an analog amplifier, a high-pass filter (HPF), a switched resistor array and voltage-controlled capacitors, and a bias on/off controller. The memory module may expand the bandwidth by substantially passing the AC component of the signal through the high-pass filter and then amplifying it. The memory module may adjust the bandwidth through the bias control of the resistor array and capacitors. The memory module may alleviate input capacitance overlap caused by the AC-coupled capacitors through bias on/off control.
In an embodiment, a memory module of the present disclosure may be applied to amplifiers of other topologies in addition to folded cascode amplifiers.
In an embodiment, the application point of the high-pass filter need not be limited to the first bias. In an embodiment, the bandwidth may be adjusted by the voltage-controlled capacitors in addition to the resistor array.
As the big data and artificial intelligence (Al) markets expand, the demand for high-density memory is increasing, leading to the application of topologies such as multi-rank and byte mode to maximize Dynamic Random-Access Memory (DRAM) capacity. As a result, signal integrity (SI) characteristics observed in the channel may deteriorate. In particular, systems like Low Power Compression Attached Memory Module (LPCAMM) have limitations in increasing the operating frequency due to channel characteristics caused by heavy loading. Therefore, an equalizer, and/or a circuit technique to compensate for input SI, may be applied to DRAM receivers.
For example, equalizing may be achieved by adding a High-pass Filter (HPF) to the differential input to filter only the AC component and applying it to a biased transistor used as a current source. The bandwidth may be expanded by the complementary operation of the main input transistor and the transistor of the current source connected to the HPF. However, to adapt to various channel environments and input frequencies with a single DRAM chip, the frequency response characteristics of the HPF may need to be adjusted. The present disclosure may adjust the frequency response by controlling the resistors and capacitors. Hence, the present disclosure offers flexible means of adjustment.
Additionally, the capacitors configuring the HPF may act as input loading in a multi-rank environment, degrading SI quality. The present disclosure adds a bias control to make the HPF capacitance of deactivated other rank DRAMs invisible as input loading.
By substantially passing the AC component of the input signal through the HPF connected to both differential amplifier inputs and then amplifying it, the bandwidth of the amplifier may be expanded. To adapt to various channel environments, the resistors and capacitors configuring the HPF may be adjustable. In the memory module, a bias control section may be added to minimize the increase in input capacitance caused by deactivated DRAMs. For example, it may have a bias level for the buffer when activated, and high impedance (Hi-Z) when deactivated.
The memory system 10 may be implemented to be included in a personal computer (PC) or in a mobile device. For example, the mobile device may be implemented as a laptop computer, a mobile phone, a smartphone, a tablet PC, a Personal Digital Assistant (PDA), an Enterprise Digital Assistant (EDA), a digital still camera, a digital video camera, a Portable Multimedia Player (PMP), a Personal Navigation Device or Portable Navigation Device ((PND), a handheld game console, a Mobile Internet Device (MID), a wearable computer, an Internet of Things (IoT) device, an Internet of Everything (IoE)) device, or a drone, without limitation thereto.
The memory module 11 may include a plurality of ranks RANK1 to RANKi, where i is an integer of 2 or more. Each of the plurality of ranks RANK1 to RANKi may include a plurality of memory devices MEM1 to MEMj, where j is an integer of 2 or more. Each of the memory ranks RANK1 to RANKi refers to a number of memory devices and/or memory chips that receive and respond to commands and/or addresses from the controller 12.
Each of the memory devices MEM1 to MEMj may include a memory cell array including a plurality of memory cells. In an embodiment, the memory cell may be a volatile memory cell. For example, the memory device may be a Dynamic Random-Access Memory (DRAM), a Static Random-Access Memory (SRAM), a mobile DRAM, a Double Data Rate Synchronous Dynamic Random-Access Memory (DDR SDRAM), a Low Power DDR (LPDDR) SDRAM, a Graphic DDR (GDDR) SDRAM, a Rambus Dynamic Random-Access Memory (RDRAM), or the like.
In an embodiment, the memory cell may be a non-volatile memory cell. For example, the memory device may be a non-volatile memory, such as an Electrically Erasable Programmable Read-Only Memory (EEPROM), a flash memory, a Phase Change Random-Access Memory (PRAM), a Resistance Random-Access Memory (RRAM), a Nano Floating Gate Memory (NFGM), a Polymer Random-Access Memory (PoRAM), a Magnetic Random-Access Memory (MRAM), a Ferroelectric Random-Access Memory (FRAM), or the like. Below, the memory device is described as being DRAM, but it shall be understood that the memory device is not limited thereto.
A rank generally refers to a plurality of memory devices and/or chips that all receive and respond to common commands from an associated memory controller and/or control unit. As illustrated in
Additionally, each of the ranks RANK1 to RANKi has an adjustable bandwidth and may be embodied as an amplifier implemented as an AC Coupled Booster (ACCB) with low input capacitance. In an embodiment, the amplifier may vary the bandwidth of the amplifier by substantially passing the AC component of the input signal through a high-pass filter connected to both inputs of the differential amplifier. In an embodiment, the amplifier may adjust the resistors and capacitors constituting the high-pass filter to respond to various channel environments. In an embodiment, the amplifier may control bias to significantly reduce the increase in input capacitance caused by a deactivated memory device.
The controller 12 may be implemented to send commands to some or all of the memory ranks RANK1 to RANKi simultaneously. The controller 12 may be implemented to perform a write operation to write data to the memory module 11 or a read operation to read data stored in the memory module 11. The controller 12 may write data to the memory module 11 or generate commands and addresses for reading data stored in the memory module 11. The controller 12 may be at least one of a chipset for controlling the memory module 11, a system-on-chip such as a mobile application processor (AP), a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), and/or a Data Processing Unit (DPU).
The memory system 10 according to an embodiment includes a memory module 12 having an amplifier implemented as an AC Coupled Booster (ACCB), and thus, bandwidth may be adjusted, and the increase in input capacitance due to deactivated memory devices may be significantly reduced.
The memory cell array 210 may include first to eighth bank arrays 211 to 218. Moreover, it shall be understood that the number of bank arrays constituting the memory cell array 210 is not limited thereto. The first to eighth bank arrays 211 to 218, first to eighth bank row decoders 221 to 228, first to eighth bank column decoders 231 to 238, and first to eighth banks of sense amplifiers 241 to 248 may configure 1st to 8th banks, respectively. Each of the first to eighth bank arrays 211 to 218 may include a plurality of memory cells MC formed between the word lines WL and the bit lines BL.
The row decoder 220 may include first to eighth bank row decoders 221 to 228 respectively connected to first to eighth bank arrays 211 to 218. In an embodiment, each of the first to eighth bank row decoders 221 to 228 may be configured to perform a repair operation using an address swap function. In an embodiment, the bank row decoder activated by the bank control logic 252 among the first to eighth bank row decoders 221 to 228 decodes the row address RA output from the row address multiplexer 256, and may activate the word line corresponding to each row address. For example, an enabled bank row decoder may apply a word line driving voltage to a word line corresponding to a row address. Additionally, the enabled bank row decoder activates the word line corresponding to the row address, and simultaneously therewith, may activate a redundancy word line corresponding to the spare row address (SRA, or ‘redundancy row address’) output from the repair control circuit 266.
The column decoder 230 may include first to eighth bank column decoders 231 to 238 respectively connected to the first to eighth bank arrays 211 to 218. In an embodiment, among the first to eighth bank column decoders 231 to 238, the bank column decoder activated by the bank control logic 252 may activate sense amplification corresponding to the bank address BANK_ADDR and column address COL_ADDR through the input/output gating circuit 270. Additionally, the enabled bank column decoder may perform a column repair operation in response to the column repair signal CRP output from the repair control circuit 266.
The sense amplification circuit 240 may include first to eighth bank sense amplifiers 241 to 248 respectively connected to the first to eighth bank arrays 211 to 218.
The address register 250 may receive and store an address ADDR having a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from an external memory controller, such as the memory controller 12 of
The bank control logic 252 may generate bank control signals in response to the bank address BANK_ADDR. In response to some bank control signals, a bank row decoder corresponding to the bank address BANK_ADDR among the first to eighth bank row decoders 221 to 228 may be activated. In response to other bank control signals, a bank column decoder corresponding to the bank address BANK_ADDR among the first to eighth bank column decoders 231 to 238 may be activated.
The row address multiplexer 256 may receive a row address ROW_ADDR from the address register 250 and a refresh row address REF_ADDR from the refresh counter 254. The row address multiplexer 256 may selectively output a row address ROW_ADDR or a refresh row address REF_ADDR as a row address RA. The row address RA output from the row address multiplexer 256 may be applied to the first to eighth bank row decoders 221 to 228, respectively.
The column address latch 258 may receive the column address COL_ADDR from the address register 250 and temporarily store the received column address COL_ADDR. Additionally, the column address latch 258 may gradually increase the received column address COL_ADDR in a burst mode. The column address latch 258 may apply a temporarily stored or gradually increased column address COL_ADDR to the first to eighth bank column decoders 231 to 238, respectively.
The control logic circuit 260 may be implemented to control the operation of the memory device 200. For example, the control logic circuit 260 may generate control signals so that the semiconductor memory device 200 performs a write operation or a read operation. The control logic circuit 260 may include a command decoder 261 for decoding a command CMD received from the external memory controller and a mode register 262 for setting the operational mode of the memory device 200. For example, the command decoder 261 may decode a write enable signal/WE, a row address strobe signal/RAS, a column address strobe signal/CAS, a chip select signal/CS, and the like, thereby generating operational control signals corresponding to commands CMD. The generated operational control signals may include an active signal ACT, a precharge signal PCH, a write signal WR, and a read signal RD, without limitation thereto.
The control logic circuit 260 may provide the operational control signals ACT, PCH, WE and RD to the timing control circuit 264. The timing control circuit 264 may generate first control signals CTL1 controlling the voltage level of the word line WL and second control signals CTL2 controlling the voltage level of the bit line BL, in response to the operational control signals ACT, PCH, WR and RD, and may provide the generated first control signals CTL1 and second control signals CTL2 to the memory cell array 210.
The repair control circuit 266 may generate repair control signals that control repair operations of a first cell area and a second cell area of at least one of the bank arrays, based on the fuse information of each word line, the row address ROW_ADDR and column address COL_ADDR of the address ADDR (or access address). The generated repair control signals may include a spare row address SRA (or redundancy row address) for provision to the corresponding bank row decoder, a column repair signal CRP for provision to the corresponding bank column decoder, a selection signal SEL and an enable signal EN for provision to the block control circuit related to the corresponding spare array block (or redundancy array block). The repair control circuit 266 may vary the repair unit based on the address ADDR and fuse information. For example, the repair control circuit 266 may change the type and number of repair address bits using address ADDR and fuse information.
Each of multiple input/output gates of the input/output gating circuit 270 may include input data mask logic, read data latches for storing data output from the first to eighth bank arrays 211 to 228, and write drivers for writing data to the first to eighth bank arrays 211 to 218, along with circuitry gating input and/or output data.
The error correction circuit 280 may generate parity bits based on data bits of data DQ provided from the data input/output buffer 282 during a write operation, and provide a codeword CW containing data DQ and parity bits to the input/output gating circuit 270, and the input/output gating circuit 270 may write a codeword CW to the bank memory array 210. Additionally, the error correction circuit 280 may receive a codeword CW read from one bank array through the input/output gating circuit 270 during a read operation. The error correction circuit 280 performs Error Correction Code (ECC) decoding on the data DQ using the parity bits included in the read codeword CW. At least one error bit included in the data DQ may be corrected and provided to the data input/output buffer 282.
A codeword CW to be read from one of the first to eighth bank arrays 211 to 218 may be detected by a sense amplification corresponding to one bank array and stored in the read data latches of the input/output gating circuit 270. The codeword CW stored in the read data latches may be provided to the external memory controller through the data input/output buffer 282 after ECC decoding is performed by the error correction circuit 280. Data DQ written to one bank array among the first to eighth bank arrays 210 to 218 may be written to the one bank array through write drivers after performing ECC encoding in the error correction circuit 280.
In a write operation, the data input/output buffer 282 provides data DQ to the error correction circuit 280 based on the clock signal CLK provided from the external memory controller, and in a read operation, data DQ provided from the error correction circuit 280 may be provided to the external memory controller.
Moreover, in an embodiment of the present disclosure, bias control may be performed in a multi-rank system.
Each of the plurality of receivers 31 to 34 may include an amplifier AMP. The amplifier AMP may vary the bias of the amplification operation depending on whether the receiver RX is enabled. In an embodiment, when the receiver RX is enabled such as when the corresponding rank is selected, the filter bias terminal VB_HPF of the amplifier AMP may receive the voltage of the bias power terminal VB. And when the receiver RX is disabled such as when the corresponding rank is unselected, the filter bias terminal VB_HPF of the amplifier AMP may be in a high impedance state Hi-Z preventing it from receiving the voltage of the bias power terminal VB.
The current source CS may be connected to the power terminal VDD. The current source CS may generate a common current.
The first PMOS transistor PM1 is connected between the current source CS and the first node N1 and may have a gate receiving a first input signal IN+. The first node (N1) may output a second output signal OUT−.
The second PMOS transistor PM2 is connected between the current source CS and the second node N2 and may have a gate receiving a second input signal IN−. In this case, the first input signal IN+ and the second input signal IN− are differential signals. The second node N2 may output a first output signal OUT+. In this case, the first output signal OUT+ and the second output signal OUT− are differential signals.
The first NMOS transistor NM1 is connected between the first node N1 and the ground terminal GND and may have a gate receiving a first filtering voltage. In this case, the first filtering voltage is the voltage obtained by filtering the first input signal IN+ by the high-pass filter 41.
The second NMOS transistor NM2 is connected between the second node N2 and the ground terminal GND and may have a gate receiving a second filtering voltage. In this case, the second filtering voltage is the voltage obtained by filtering the second input signal IN− by the high-pass filter 41.
The high-pass filter 41 (HPF) may include a first capacitor C1, a second capacitor C2, a first resistor R1, and a second resistor R2. In this embodiment, each of the first capacitor C1 and the second capacitor C2 may be a variable capacitor. Additionally, each of the first resistor R1 and the second resistor R2 may be a variable resistor.
The first capacitor C1 may be connected between the first input terminal receiving the first input signal IN+ and the gate of the first NMOS transistor NM1. The second capacitor C2 may be connected between the second input terminal receiving the second input signal IN− and the gate of the second NMOS transistor NM2.
The first resistor R1 may be connected between the filter bias terminal VB_HPF and the gate of the first NMOS transistor NM1. The second resistor R2 may be connected between the filter bias terminal VB_HPF and the gate of the second NMOS transistor NM2. The switch SW may be connected between the filter bias terminal VB_HPF and the bias power terminal VB.
In an embodiment, when the rank is enabled such as activated in response to a rank enable signal, the switch SW is turned on so that the filter bias terminal VB_HPF and the bias power terminal VB may be electrically connected. Accordingly, the voltage of the bias power terminal VB may be applied to the filter bias terminal VB_HPF. When the rank is disabled, the switch SW is turned off so that the filter bias terminal VB_HPF and the bias power terminal VB are electrically blocked. Accordingly, the filter bias terminal VB_HPF is in the high impedance state Hi-Z. In an embodiment, the switch SW may be implemented as a transistor.
In general, when multiple DRAM receivers are configured in a multi-rank environment, the first and second inputs SI may be degraded by the capacitors that make up the HPF. Inputs SI are greatly affected by input capacitance. However, the capacitor of the HPF being connected multiple times by multi-rank configurations may greatly increase the input capacitance.
As illustrated in
As illustrated in
The first PMOS transistor PT1 is connected between the current source CS and the first node ND1 and may have a gate receiving the first input signal IN+. The second PMOS transistor PT2 is connected between the current source CS and the second node ND2 and may have a gate receiving the second input signal IN−. The third PMOS transistor PT3 is connected between the power terminal VDD and the second output terminal and may have a gate receiving the first filtering voltage. In this case, the second output terminal may output a second output signal OUT−. Additionally, the first filtering voltage is a voltage obtained by filtering the first input signal IN+ by the high-pass filter 51. The fourth PMOS transistor PT4 is connected between the power terminal VDD and the first output terminal and may have a gate receiving the second filtering voltage. In this case, the first output terminal may output the first output signal OUT+. Additionally, the second filtering voltage is the voltage obtained by filtering the second input signal IN− by the high-pass filter 51.
The first NMOS transistor NT1 may be connected between the first node ND1 and the ground terminal GND, and may have a gate connected to the first bias terminal VB1 receiving a first bias voltage. The second NMOS transistor NT2 may be connected between the second node ND2 and the ground terminal GND, and may have a gate connected to the first bias terminal VB1 receiving the first bias voltage. The third NMOS transistor NT3 is connected between the second output terminal and the first node ND1 and may have a gate connected to the second bias terminal VB2 receiving a second bias voltage. The fourth NMOS transistor NT4 is connected between the first output terminal and the second node ND2 and may have a gate connected to the second bias terminal VB2 receiving the second bias voltage.
The high-pass filter (HPF) 51 may include a first capacitor C1, a second capacitor C2, a first resistor R1, and a second resistor R2. In an embodiment, at least one of the first capacitor C1, the second capacitor C2, the first resistor R1, and the second resistor R2 may be variably controlled.
The switch SW may be connected between the filter bias terminal VB_HPF and the bias power terminal VB. In an embodiment, when the rank is enabled, the switch SW is turned on so that the filter bias terminal VB_HPF and the bias power terminal VB may be electrically connected. Accordingly, the voltage of the bias power terminal VB may be applied to the filter bias terminal VB_HPF. In an embodiment, when the rank is disabled, the switch SW is turned off so that the filter bias terminal VB_HPF and the bias power terminal VB are electrically blocked. Accordingly, the filter bias terminal VB_HPF is in a high resistance state Hi-Z.
Moreover, in
Moreover, in the present disclosure, a Low Power Compression Attached Memory Module (LPCAMM) may be used.
The SPD chip 701 may include device information of the memory module 700. As an example, the SPD chip 701 may include initial information or device information such as module type, module configuration, storage capacity, module type, execution environment, and the like of the memory module 700.
When the memory system 700 is booted, the memory controller may read device information from the SPD chip 701 of the memory module 700 and recognize the memory module 700 based on the read device information. The memory controller may control the memory module 700 based on device information from the SPD chip 701. The PMIC chip 730 may generate a power voltage based on the input voltage and provide the generated power voltage to the memory chips. The memory chips may operate based on the power supply voltage.
Moreover, the memory module 700 may further include a Registering Clock Driver (RCD) chip. The RCD chip may control the ranks 710 and 720 and the PMIC chip 730 under the control of the memory controller. For example, the RCD chip may receive commands, addresses, clock signals, and control signals from the memory controller through the memory bus, and may perform a buffer function to distribute the received signals to the first memory channel and/or the second memory channel. The memory chips of each memory channel will exchange data with the memory controller in response to commands, addresses, clock signals, and control signals provided from the RCD chip 780.
The memory controller 3100 may perform an access operation to write data to the memory module 3200 or read data stored in the memory module 3200. The memory controller 3100 may write data to the memory module 3200 or generate a command CMD and an address ADDR for reading data stored in the memory module 3200. The memory controller 3100 may be a chipset for controlling the memory module 3200, a system-on-chip (SoC) such as a mobile application processor (AP), a CPU, a GPU, a DPU, and/or a neural processing unit (NPU), without limitation thereto.
The memory module 3200 may include a plurality of stacked memory devices corresponding to multiple ranks (multi-ranks) Rank0, Rank1, Rank2, and Rank3. In this case, each of the multi-ranks Rank0, Rank1, Rank2, and Rank3 may be implemented as an amplifier with ACCB as described supra in
Moreover, the present disclosure is applicable to a High Bandwidth Memory (HBM)-Processing-in-Memory (PIM) configuration.
The device described above may be implemented with hardware components, software components, and/or a combination of hardware components and software components. For example, the devices and elements described may be implemented using one or more general-purpose computers or special-purpose computers, such as a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. Additionally, a processing device may access, store, manipulate, process, and generate data in response to the execution of software. For ease of understanding, one processing device may be described as being used in some cases, but those of ordinary skill in the pertinent art will appreciate that a processing device may include a plurality of processing elements or multiple types of processing elements. For example, a processing device may include a plurality of processors or one processor and one controller. Additionally, other processing configurations, such as parallel processors, may be applied in an alternate embodiment.
Software may include computer programs, code, instructions, or a combination of one or more thereof, or an external configuration device may configure the processing devices to operate as desired or command the processing devices independently or collectively. Software and/or data may be embodied in any type of machine, component, physical device, virtual equipment, computer storage medium or device, to be interpreted by the processing device and/or provide instructions or data to the processing device. Software may be distributed over networked computer systems and may be stored or executed in a distributed manner. Software and data may be stored on one or more non-transitory computer-readable recording media.
A memory module according to an embodiment may include a high-pass filter (HPF) for high frequency (HF) boosting connected to both end inputs, a resistor and/or capacitor (RC) control unit for RC control of variable resistors or capacitors within the HPF, and a control unit for adjusting the bias applied to the HPF, in a differential amplifier structure. The present disclosure may be particularly applicable to a differential amplifier structure such as a common source and/or folded cascode structure, rather than a clocked sense amplifier, without limitation thereto. In an embodiment, the memory module may add tunable RC applications to adjust the peaking of the HPF. In an embodiment, the memory module may add bias control to reduce the increase in input capacitance due to high-pass filtering in a multi-rank environment. The memory module according to an embodiment is applicable to DRAM receivers in mobile, discrete, server, and LPCAMM environments. without limitation thereto.
A memory module and operating method thereof according to an embodiment of the present disclosure may extend the bandwidth (BW) of the amplifier by substantially passing the AC component of the input signal through a high-pass filter (HPF) connected to the differential input of the differential amplifier, and then amplifying the passed signal. The memory module and the operating method may adjust the resistors and capacitors that configure the HPF to respond to various channel environments. The memory module and the operating method may add a bias control section such as for setting the buffer to the bias level when activated and/or to a high impedance state Hi-Z when deactivated, in a multi-rank system to minimize the increase in input capacitance caused by the deactivated DRAM(s). As set forth above, in a memory module and a method of operating the same according to an embodiment, a bandwidth may vary using an AC coupled booster.
In a memory module and a method of operating the same according to an embodiment, a bandwidth may be expanded after substantially passing an AC component of a signal through a high-pass filter.
In a memory module and a method of operating the same according to an embodiment, a bandwidth may be adjusted through bias control of a resistor array and a capacitor.
In a memory module and a method of operating the same according to an embodiment, input capacitance overlap caused by an AC coupled capacitor may be alleviated by using bias on/off control in a multi-rank system.
While illustrative embodiments have been shown and described, it will be apparent to those of ordinary skill in the pertinent art that modifications and variations may be made without departing from the scope and spirit of the present disclosure as defined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2024-0003363 | Jan 2024 | KR | national |
| 10-2024-0060936 | May 2024 | KR | national |
