Input/output (I/O) data interface arrangements

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G11C11/4093

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GPHYSICS G11Information storage G11CSTATIC STORES G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements Storage elements therefor

Current Industry

G11C11/4093Input/output (I/O) data interface arrangements

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Delay control circuit, semiconductor memory device, and delay contr...
- Patent number 12,348,232
- Issue date Jul 1, 2025
- Windbond Electronics Corp.
- Shinya Okuno
- G11 - INFORMATION STORAGE
Information Patent Grant
Optimizing power in a memory device
- Patent number 12,346,188
- Issue date Jul 1, 2025
- RAMBUS INC.
- Dinesh Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device for performing read protection operation of limiting...
- Patent number 12,340,836
- Issue date Jun 24, 2025
- SK hynix Inc.
- Byung Goo Cho
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory devices having adjustable I/O signal line load...
- Patent number 12,334,140
- Issue date Jun 17, 2025
- Samsung Electronics Co., Ltd.
- Seung-Jun Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Write timing compensation
- Patent number 12,334,141
- Issue date Jun 17, 2025
- Micron Technology, Inc.
- Kang-Yong Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Maximum memory clock estimation procedures
- Patent number 12,334,137
- Issue date Jun 17, 2025
- Micron Technology, Inc.
- Erik V. Pohlmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid volatile and non-volatile memory device
- Patent number 12,327,590
- Issue date Jun 10, 2025
- RAMBUS INC.
- Scott C. Best
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory package and a memory module including the memory package
- Patent number 12,322,436
- Issue date Jun 3, 2025
- SK Hynix Inc.
- Won Ha Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier with read circuit for compute-in-memory
- Patent number 12,322,435
- Issue date Jun 3, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chieh Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory chip and memory system including the same
- Patent number 12,322,437
- Issue date Jun 3, 2025
- Samsung Electronics Co., Ltd.
- Kwangsook Noh
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device and method for manufacturing the same
- Patent number 12,315,556
- Issue date May 27, 2025
- NANYA TECHNOLOGY CORPORATION
- Kuo-Chiang Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Signal control circuit, signal control method for blocking activati...
- Patent number 12,315,546
- Issue date May 27, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Enpeng Gao
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory and method of operation with dummy and loaded route
- Patent number 12,315,557
- Issue date May 27, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Kangling Ji
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device and method for manufacturing the same
- Patent number 12,308,071
- Issue date May 20, 2025
- NANYA TECHNOLOGY CORPORATION
- Kuo-Chiang Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory devices
- Patent number 12,308,089
- Issue date May 20, 2025
- Samsung Electronics Co., Ltd.
- Jongcheol Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory systems and methods for improved power management
- Patent number 12,300,307
- Issue date May 13, 2025
- RAMBUS INC.
- Frederick A. Ware
- G11 - INFORMATION STORAGE
Information Patent Grant
Parallel access in a memory array
- Patent number 12,300,305
- Issue date May 13, 2025
- Micron Technology, Inc.
- Efrem Bolandrina
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device and method of operating the same
- Patent number 12,288,578
- Issue date Apr 29, 2025
- Samsung Electronics Co., Ltd.
- Sunghye Cho
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device and method for compensating slew rate u...
- Patent number 12,288,582
- Issue date Apr 29, 2025
- Winbond Electronics Corp.
- Chia-Lung Hsieh
- G11 - INFORMATION STORAGE
Information Patent Grant
Efficient and low power reference voltage mixing
- Patent number 12,288,581
- Issue date Apr 29, 2025
- Advanced Micro Devices, Inc.
- Aaron D Willey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device interface and method
- Patent number 12,277,056
- Issue date Apr 15, 2025
- Micron Technology, Inc.
- Brent Keeth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for processing read-modify-write requests
- Patent number 12,271,624
- Issue date Apr 8, 2025
- Recogni Inc.
- Gary S. Goldman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of generating a multi-level signal using selective equalizat...
- Patent number 12,272,396
- Issue date Apr 8, 2025
- Samsung Electronics Co., Ltd.
- Junyoung Park
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Input data pre-alignment circuit capable of performing a first-in f...
- Patent number 12,266,396
- Issue date Apr 1, 2025
- Fujian Jinhua Integrated Circuit Co., Ltd.
- Minho Park
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus including parallel pipelines and methods of manufacturing...
- Patent number 12,265,485
- Issue date Apr 1, 2025
- Micron Technology, Inc.
- Kallol Mazumder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Communicating data with stacked memory dies
- Patent number 12,265,489
- Issue date Apr 1, 2025
- Robert Nasry Hasbun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signal input buffer for effectively calibrating offset
- Patent number 12,260,901
- Issue date Mar 25, 2025
- FIDELIX CO., LTD.
- Jae Jin Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device interface and method
- Patent number 12,253,943
- Issue date Mar 18, 2025
- Brent Keeth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sub-word line driver placement for memory device
- Patent number 12,254,919
- Issue date Mar 18, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yi-Tzu Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device, memory system having the same and method of operatin...
- Patent number 12,236,995
- Issue date Feb 25, 2025
- Samsung Electronics Co., Ltd.
- Jungmin You
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY DEVICE AND METHOD FOR OPERATING THE SAME
- Publication number 20250210097
- Publication date Jun 26, 2025
- NANYA TECHNOLOGY CORPORATION
- Chien Yu CHEN
- G11 - INFORMATION STORAGE
Information Patent Application
COMPUTING SYSTEM ARCHITECTURE HAVING EFFICIENT BUS CONNECTIONS
- Publication number 20250201769
- Publication date Jun 19, 2025
- SK HYNIX INC.
- Seong Ju LEE
- G11 - INFORMATION STORAGE
Information Patent Application
Sub-Word Line Driver Placement For Memory Device
- Publication number 20250201297
- Publication date Jun 19, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yi-Tzu Chen
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE HAVING DQS COUNTER CIRCUIT
- Publication number 20250191638
- Publication date Jun 12, 2025
- Micron Technology, Inc.
- SHINGO MITSUBORI
- G11 - INFORMATION STORAGE
Information Patent Application
Overlapping a Page Operation with a Processing-in-Memory Computation
- Publication number 20250191642
- Publication date Jun 12, 2025
- Google LLC
- Hongil Yoon
- G11 - INFORMATION STORAGE
Information Patent Application
SMOOTH RTT TRANSITION
- Publication number 20250191647
- Publication date Jun 12, 2025
- Micron Technology, Inc.
- Ryo Fujimaki
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE HAVING GEAR DOWN MODE
- Publication number 20250191639
- Publication date Jun 12, 2025
- Micron Technology, Inc.
- Yoshiya Komatsu
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORYS, OPERATION METHODS THEREOF AND MEMORY SYSTEMS
- Publication number 20250182815
- Publication date Jun 5, 2025
- Yangtze Memory Technologies Co., Ltd.
- Ling DING
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES INCLUDING OUTPUT DRIVERS AND METHODS FOR PROVIDING OUTP...
- Publication number 20250182819
- Publication date Jun 5, 2025
- Micron Technology, Inc.
- Tetsuya Arai
- G11 - INFORMATION STORAGE
Information Patent Application
LOAD REDUCED MEMORY MODULE
- Publication number 20250176102
- Publication date May 29, 2025
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMMUNICATING DATA WITH STACKED MEMORY DIES
- Publication number 20250165413
- Publication date May 22, 2025
- Lodestar Licensing Group LLC
- Robert Nasry Hasbun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE PERFORMING LOOPBACK OPERATION
- Publication number 20250157526
- Publication date May 15, 2025
- Micron Technology, Inc.
- Yuichiro Sato
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICES HAVING EFFICIENT SERIALIZERS THEREIN F...
- Publication number 20250157513
- Publication date May 15, 2025
- Samsung Electronics Co., Ltd.
- Sanguk Lee
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS WITH MULTI-MODE-REGISTER READ AND WRITE COMMANDS
- Publication number 20250157528
- Publication date May 15, 2025
- Micron Technology, Inc.
- Keun-Soo Song
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS WITH MULTI-MODE-REGISTER READ AND WRITE COMMANDS
- Publication number 20250157527
- Publication date May 15, 2025
- Micron Technology, Inc.
- Keun-Soo Song
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
- Publication number 20250149082
- Publication date May 8, 2025
- NANYA TECHNOLOGY CORPORATION
- KUO-CHIANG WANG
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR REDUCED POWER COMMAND SHIFTER
- Publication number 20250140304
- Publication date May 1, 2025
- Micron Technology, Inc.
- Yukimi Morimoto
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR CONTROLLING SENSE AMPLIFIER OPERATION
- Publication number 20250140306
- Publication date May 1, 2025
- Micron Technology, Inc.
- Christopher G. Wieduwilt
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND MEMORY SYSTEM
- Publication number 20250140309
- Publication date May 1, 2025
- Samsung Electronics Co., Ltd.
- Hyeongjin Yoo
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY MODULE WITH REDUCED READ/WRITE TURNAROUND OVERHEAD
- Publication number 20250139026
- Publication date May 1, 2025
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM AND RECEIVER
- Publication number 20250124967
- Publication date Apr 17, 2025
- NANYA TECHNOLOGY CORPORATION
- Wu-Der YANG
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS INCLUDING CLOCK INPUT BUFFER
- Publication number 20250118356
- Publication date Apr 10, 2025
- Micron Technology, Inc.
- Yasuhiro Takai
- G11 - INFORMATION STORAGE
Information Patent Application
SIGNAL RECEIVER, DATA RECEIVER AND DATA LATCH THEREOF
- Publication number 20250118355
- Publication date Apr 10, 2025
- NANYA TECHNOLOGY CORPORATION
- Po-Chun Hsieh
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR SINGLE AND MULTI MEMORY CELL ARCHITECTURES
- Publication number 20250118351
- Publication date Apr 10, 2025
- Micron Technology, Inc.
- Yang Lu
- G11 - INFORMATION STORAGE
Information Patent Application
SIGNAL ROUTING BETWEEN MEMORY DIE AND LOGIC DIE
- Publication number 20250104761
- Publication date Mar 27, 2025
- Micron Technology, Inc.
- Sean S. Eilert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC RANDOM-ACCESS MEMORY STRUCTURE WITH HIGH SPEED AND WIDE BUS
- Publication number 20250104763
- Publication date Mar 27, 2025
- Invention And Collaboration Laboratory, Inc.
- Chao-Chun Lu
- G11 - INFORMATION STORAGE
Information Patent Application
RESISTANCE CALIBRATION CIRCUIT, RESISTANCE CALIBRATION METHOD, AND...
- Publication number 20250095719
- Publication date Mar 20, 2025
- CXMT Corporation
- Xi WANG
- G11 - INFORMATION STORAGE
Information Patent Application
READ/WRITE CONVERSION CIRCUIT, AND WRITE DRIVER CIRCUIT
- Publication number 20250095721
- Publication date Mar 20, 2025
- CXMT Corporation
- Weibing SHANG
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND MEMORY SYSTEM FOR PERFORMING RESISTOR OFFSET CALI...
- Publication number 20250095711
- Publication date Mar 20, 2025
- Yangtze Memory Technologies Co., Ltd.
- Zhefan Li
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR OPERATIONS IN A SELF-REFRESH STATE
- Publication number 20250095708
- Publication date Mar 20, 2025
- Lodestar Licensing Group LLC
- Perry V. Lea
- G06 - COMPUTING CALCULATING COUNTING

Input/output (I/O) data interface arrangements

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Delay control circuit, semiconductor memory device, and delay contr...

Optimizing power in a memory device

Memory device for performing read protection operation of limiting...

Semiconductor memory devices having adjustable I/O signal line load...

Write timing compensation

Maximum memory clock estimation procedures

Hybrid volatile and non-volatile memory device

Memory package and a memory module including the memory package

Sense amplifier with read circuit for compute-in-memory

Memory chip and memory system including the same

Semiconductor device and method for manufacturing the same

Signal control circuit, signal control method for blocking activati...

Memory and method of operation with dummy and loaded route

Semiconductor device and method for manufacturing the same

Semiconductor memory devices

Memory systems and methods for improved power management

Parallel access in a memory array

Semiconductor memory device and method of operating the same

Semiconductor memory device and method for compensating slew rate u...

Efficient and low power reference voltage mixing

Memory device interface and method

Methods and systems for processing read-modify-write requests

Method of generating a multi-level signal using selective equalizat...

Input data pre-alignment circuit capable of performing a first-in f...

Apparatus including parallel pipelines and methods of manufacturing...

Communicating data with stacked memory dies

Signal input buffer for effectively calibrating offset

Memory device interface and method

Sub-word line driver placement for memory device

Memory device, memory system having the same and method of operatin...

Patents Applicationslast 30 patents

MEMORY DEVICE AND METHOD FOR OPERATING THE SAME

COMPUTING SYSTEM ARCHITECTURE HAVING EFFICIENT BUS CONNECTIONS

Sub-Word Line Driver Placement For Memory Device

SEMICONDUCTOR DEVICE HAVING DQS COUNTER CIRCUIT

Overlapping a Page Operation with a Processing-in-Memory Computation

SMOOTH RTT TRANSITION

SEMICONDUCTOR DEVICE HAVING GEAR DOWN MODE

MEMORYS, OPERATION METHODS THEREOF AND MEMORY SYSTEMS

APPARATUSES INCLUDING OUTPUT DRIVERS AND METHODS FOR PROVIDING OUTP...

LOAD REDUCED MEMORY MODULE

COMMUNICATING DATA WITH STACKED MEMORY DIES

SEMICONDUCTOR DEVICE PERFORMING LOOPBACK OPERATION

SEMICONDUCTOR MEMORY DEVICES HAVING EFFICIENT SERIALIZERS THEREIN F...

APPARATUS WITH MULTI-MODE-REGISTER READ AND WRITE COMMANDS

APPARATUS WITH MULTI-MODE-REGISTER READ AND WRITE COMMANDS

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

APPARATUSES AND METHODS FOR REDUCED POWER COMMAND SHIFTER

APPARATUSES AND METHODS FOR CONTROLLING SENSE AMPLIFIER OPERATION

MEMORY DEVICE AND MEMORY SYSTEM

MEMORY MODULE WITH REDUCED READ/WRITE TURNAROUND OVERHEAD

MEMORY SYSTEM AND RECEIVER

APPARATUS INCLUDING CLOCK INPUT BUFFER

SIGNAL RECEIVER, DATA RECEIVER AND DATA LATCH THEREOF

APPARATUSES AND METHODS FOR SINGLE AND MULTI MEMORY CELL ARCHITECTURES

SIGNAL ROUTING BETWEEN MEMORY DIE AND LOGIC DIE

DYNAMIC RANDOM-ACCESS MEMORY STRUCTURE WITH HIGH SPEED AND WIDE BUS

RESISTANCE CALIBRATION CIRCUIT, RESISTANCE CALIBRATION METHOD, AND...

READ/WRITE CONVERSION CIRCUIT, AND WRITE DRIVER CIRCUIT

MEMORY DEVICE AND MEMORY SYSTEM FOR PERFORMING RESISTOR OFFSET CALI...

APPARATUSES AND METHODS FOR OPERATIONS IN A SELF-REFRESH STATE