Patent Application
20080133817
A memory arrangement generally comprises one or more memory modules and a memory controller. A memory module generally relates to a portion of memory for storing data which may be used alone or in connection with further memory modules to form a memory arrangement. A memory module may be located on a dedicated circuit board or a may be arranged on a circuit board together with other components. A memory controller controls the read operations and, in the case writeable memory, also the write operations of the memory arrangement.
A communication unit is typically associated with a memory module and handling at least part of the communication between a memory controller and the memory module.
One embodiment includes a communication unit configured to operate with a memory module. The communication unit includes a first connection configured to couple to a memory controller, a second connection configured to couple to memory of the memory module, and a search engine. The search engine includes a search routine activatable by a search request received via the first connection, the search routine when activated searching a memory connected to the second connection for a search pattern received via the first connection.
The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
Embodiments relate to a communication unit for a memory module, a corresponding memory module, a memory arrangement, a memory controller and methods of operation thereof.
In the following, embodiments are described in detail. In order to make the following description more precise, some terms used within the description will be defined first:
The term “memory” generally relates to all types of memory devices used for storing data, in particular both to rewritable types of memory like random access memory (RAM), flash memory and the like and to memory which may be read out only like read only memory (ROM), or only written to once like electrically programmable read only memory (EPROM) and subtypes thereof. Examples for subtypes are Static RAM (SRAM) and Dynamic RAM (DRAM) as subtypes of RAM.
The term “memory module” generally relates to a portion of memory for storing data which may be used alone or in connection with further memory modules to form a memory arrangement. A memory module in this sense may be located on a dedicated circuit board (e.g., dual inline memory modules (DIMMs) used for example as memory in computers) or may be arranged on a circuit board together with other components.
A memory arrangement generally comprises one or more memory modules and a memory controller. A memory controller in this context refers to an entity controlling the read operations and, in case of writable memory, also the write operations of the memory arrangement.
A communication unit refers generally to a unit associated with a memory module and handling at least part of the communication between a memory controller and the memory module. An example for communication units are referred to as advanced memory buffers (AMB) used in fully-buffered DIMM.
In the embodiment illustrated, memory modules 12A, 12B, 12C and 12D are arranged on respective separate circuit boards which for example may be inserted into corresponding slots on a motherboard of a computer (e.g., a server or a workstation).
The read and write operations of the memory arrangement illustrated in
Memory controller 10 receives, as indicated by arrows 11, a read request or a write request from the system in which the memory arrangement illustrated is installed, for example from a central processing unit of a computer.
Memory controller 10 then, as indicated by arrows 16, forwards the request to the AMB(s) 14 of the corresponding memory module(s) where the memory address to be read out or to be written to is located, for example to AMB 14A in case the memory corresponding to the memory address is located on memory module 12A. As illustrated in
The corresponding AMB, for example AMB 14A, then forwards the read/write request to the corresponding DRAM(s) of the corresponding memory module, wherein AMB 15A buffers the data to be written to the memory or the data read out from the memory. The AMB 15A then sends the read out data back to memory controller 10. In case of a read operation, memory controller 10 then forwards the read out data to the requesting entity like the above-mentioned central processing unit.
In the embodiment illustrated in
At 20, a search request for searching a specific pattern in the memory constituted by DRAMs 13 of memory modules 12 is sent to memory controller 10, for example by a central processing unit. Memory controller 10 then, at 21, sends the search request to all AMBs 14 and in particular the search engines 15 thereof. Search engines 15 then in parallel each search their corresponding memory module for the pattern to be searched by comparing the data stored in the DRAMs 13 which said pattern. Finally, at 23, the search results are returned to memory controller 10, for example in form of memory addresses where the searched pattern is stored or a signal indicating that the searched pattern was not found.
In the embodiment illustrated, since all search engines 15 perform the search in parallel, a quick search is possible.
In one specific embodiment, search engines 15 are incorporated in a self-test function of AMBs 14. Such self-test functions are provided in conventional AMBs for self-testing of the memory modules and are commonly referred to as memory built-in self-test (MemBIST).
In particular, in this case functions of the built-in self-test for comparing of data and the like may be used within search engines 15.
In the memory arrangement of
In the embodiment of
In the embodiment illustrated in
In the embodiment illustrated, if a search as mentioned is to be performed by search engine 15, the address space (i.e., the set of memory addresses on the respective memory module) is split in two, one part of the address space being searched via address bus 30 and the other part being searched by address bus 31. In embodiments where more than two address busses are provided, the address space correspondingly may be split in more than two parts.
This concept will be further explained with reference to
Since in the embodiment illustrated two address busses are present, the address space for performing the search is split in two, wherein addresses up to 0-0x7ff . . . f are searched via address bus 30 as indicated by arrow 40, whereas address from 0x8 . . . on are searched via address bus 31 as indicated by arrow 41.
For searching, the content bytes addressed by the corresponding address bus are retrieved (i.e., sent to AMB 14) and compared with the search pattern or part thereof in search engine 15.
Therefore, during the search, it is checked whether the content bytes addressable by the corresponding address bus 30 or 31 match the pattern, for example a 72 bit pattern to be searched in the present case. Only if a match is found here, the remaining content bytes are also checked in order to determine if in fact a full match has been found.
In the example illustrated in
In the part of the address space searched using address bus 31 as indicated by arrow 41, the retrieved content bytes are compared with the lower 5×8=40 bits of the search pattern. Only if a match is found, which in the example illustrated is the case for the addresses indicated by horizontal lines 43 and 44, address bus 30 is used to retrieve content bytes 5-8 for these addresses to check whether also these bytes match. In the example illustrated, this is not the case as indicated by the word “mismatch”.
The search in the two parts of the address space as indicated by arrows 40 and 41 can be performed in parallel. In this way, the search speed is almost doubled compared with the case where the whole address space is searched consecutively, since only for those addresses where a partial match is found using one address bus the whole data stored at that address has to be retrieved.
As a matter of course, the partitioning of the address space illustrated in
In the embodiment illustrated, the AMBs 14 receive a search request from memory controller 10 and send the results to memory controller 10 after the results for the corresponding memory module or, in a different embodiment, the results of all the memory modules are present. In these embodiments, no communication regarding the search is performed between memory controller 10 and AMBs 14 inbetween.
While the search is performed, read or write requests may be sent to memory controller 10 by other entities like a CPU.
According to an embodiment, while the search is performed, these read and write requests are refused or delayed until the search is completed. In other words, in this embodiment after memory controller 10 has sent a search request to AMBs 14, when memory controller 10 receives a read request or a write request it refuses this request or it stores the parameters of the request in a buffer memory (not illustrated) for delaying the request until the search results have been returned to memory controller 10.
In this case where no read and write operations are allowed during search, the corresponding connections indicated by arrows 16 are powered down in a particular embodiment (i.e., their power consumption can be reduced) while the search is being performed.
In other embodiments of the invention, read and write operations are allowed also while a search is being performed. In this case, read and write requests received by memory controller 10 are forwarded as already described above to the corresponding AMB(s) 14.
In case read and write access is possible during the search, according to an embodiment, the search is interrupted when an AMB receives a read or write request. In case of a write request, the situation may occur where the write operation changes the result of the search. In embodiments, this is being monitored, and corresponding information is returned to memory controller 10. A method according to such an embodiment is discussed with reference to
The method of
After that, at 53 the write operation is performed (i.e., data is written to the write address overwriting the previously stored data).
At 54, again a search at the write address like the one performed at 51 is performed (i.e., it is again checked whether the data stored at the write address matches the search pattern). Since the old data stored there has been overwritten by new data at 53, the results obtained at 54 may differ from the results obtained at 51.
Finally, at 55 the results are output. Various types of results are possible which may for example be identified by returning different codes or flags to memory controller 10. In one embodiment, the following results are possible:
no match (i.e., neither the old data nor the new data at the write address matches the search pattern);
no match with the old data, but match with the new data (in which case for example a flag NEW may be returned);
match with the old data which is overwritten, but no match with the new data (flag OLD); and
match with both new data and old data (possible flag: CONTINUOUS).
Additionally, it is possible to return a flag CONSTANT if the new data is the same as the old data irrespective of the matching conditions.
The method illustrated in
It has been explained above that the search pattern may for example be a series of 1 and 0 to be compared with bit patterns stored in the memory, for example a search pattern of 1100 in case data is stored in groups 4 bits or a 72-bit pattern in case of the storage of 72 bit groups as explained. Any other length of the search pattern is also possible. In other embodiments the search pattern may also comprise so-called “don't cares” which designate bits where a match can be obtained both if the bit has a value of 1 and if the bit has a value of 0. Taking X as a representation of such a don't care value, a search pattern of 11X0 would yield a match both for a stored value of 1110 and 1100.
Furthermore, in the embodiments discussed above the memory comprises bits which may assume either a state of 1 or a state of 0. It is also possible, in different embodiments, to arrange the memory in a way to be able to have more than two states, for examples three states, a 1, a 0 and a “don't care” state similar to the don't care search pattern above to which both a 1 in a search pattern or a 0 in a search pattern matches. Such a memory may for example be realized by combining two bits or a conventional memory to a “three state bit” wherein a combination 00 corresponds to a value of 0 of the three state bit, a combination 11 of the two bits corresponds to a 1 of the three state bit and a 10 or a 01 corresponds to a don't care.
Embodiments, as mentioned above, may be used in computers, but also in other electronic devices like routers, personal digital assistance, mobile phones or the like. For example, in PDA or mobile phone applications, the search functionality provided by the search engines 15 may be used for finding an entry in an address data base, in a router it may be used for locating an entry in a routing table to determine the connection to take for a specific IP address, the IP address in this case being used for forming the search pattern. Other applications comprise data base applications wherein a specific entry in the data base is searched using the searching functionality of the search engines.
As a matter of course, the above-described embodiments are to be taken as examples only, and numerous modifications are possible without departing from the scope of the present invention. Some of the possible modifications will be discussed below.
In the embodiment illustrated, four memory modules 12A-12D were provided. However, the number of memory modules may vary according to the application. For example, in some computers, a plurality of slots for memory modules are provided, and an arbitrary number of modules starting from a single module may be inserted in order to provide as much memory as desired by the user.
Furthermore, in the embodiment illustrated search engines 15 were implemented in AMB. In other embodiments, search engines 15 are provided as separate entities, for example separate chips, on the memory modules and are controlled by memory controller 10 for performing the search. This in particular may be implemented in embodiments which are not based on fully-buffered DIMMs (i.e., memory modules which do not have an AMB) for example conventional DIMMs. In other embodiments, the search engine may be incorporated in a memory chip of the memory module.
Also, as already mentioned above, while the memory modules in the embodiments illustrated each have dedicated circuit boards, in other embodiments the memory modules may be put on a common circuit board, either alone or together with further components like the memory controller, a processing unit and the like.
In yet further embodiments, the search request sent by the memory controller comprises, beside the search pattern, a memory range to be searched, for example by indicating a start address and an end address. In this case, the search engines only search the part of the memory indicated by the memory range.
Furthermore, in the embodiment illustrated in
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments illustrated and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
