MEMORY POWER CONTROL

Abstract

A power control device includes a first switch and a second switch. A first terminal of the first switch is configured to receive a first voltage signal in a first voltage domain, and a first terminal of the second switch is configured to receive a second voltage signal in a second voltage domain different from the a first voltage domain. A second terminal of the second switch is coupled to a second terminal of the first switch, and a control circuit is coupled to control terminals of the first switch and the second switch. The control circuit is configured to turn on the first switch in response to a decrease of a voltage level of the first voltage signal.

Description

Claims

1. A device, comprising: a first switch, a first terminal of the first switch configured to receive a first voltage signal in a first voltage domain;a second switch, a first terminal of the second switch configured to receive a second voltage signal in a second voltage domain different from the a first voltage domain, a second terminal of the second switch coupled to a second terminal of the first switch; anda control circuit coupled to control terminals of the first switch and the second switch, and configured to turn on the first switch in response to a decrease of a voltage level of the first voltage signal.

2. The device of claim 1, wherein the first voltage domain is a VDD domain.

3. The device of claim 1, wherein the first voltage domain is a VDDM domain.

4. The device of claim 1, wherein the control circuit includes an enable input terminal configured to receive an enable signal, wherein the enable signal is based on the voltage level of the first voltage signal.

5. The device of claim 4, further comprising an enable circuit having an input terminal configured to receive the first voltage signal in the first voltage domain and an output terminal connected to the connected to output the enable signal to the enable input terminal.

6. The device of claim 5, wherein the enable circuit includes an inverter.

7. The device of claim 1, wherein the first and second switches each comprise a PMOS transistor.

8. The device of claim 1, further comprising a plurality of first switches including the first switch, wherein the plurality of first switches are connected in series, and wherein the control circuit is configured to turn on at least one of the first switches in response to the decrease of the voltage level of the first voltage signal.

9. A circuit, comprising: a first voltage domain input terminal;a second voltage domain input terminal;a first transistor having a first source/drain terminal connected to the first voltage domain input terminal and a second source/drain terminal connected to a voltage output terminal;a second transistor having a first source/drain terminal connected to the second voltage domain input terminal and a second source/drain terminal connected to the voltage output terminal;a control circuit having an enable input terminal and an output terminal connected to gate terminals of the first and second transistors; andan enable circuit including an inverter having an input terminal connected to the first voltage domain input terminal, and an output connected to the enable input terminal.

10. The circuit of claim 9, wherein the control circuit is configured to turn on the first transistor in response to the enable signal indicating a decrease of a voltage signal received at the first voltage domain input terminal.

11. The circuit of claim 9, wherein the control circuit includes a shutdown terminal configured to receive a shutdown signal, and wherein the control circuit is further configured to turn off the first and second transistors based on the shutdown signal.

12. The circuit of claim 9, wherein a voltage level of the first voltage domain is lower than a voltage level of the second voltage domain.

13. The circuit of claim 9, wherein the first and second transistors each comprise a PMOS transistor.

14. The circuit of claim 9, further comprising a third transistor having a first source/drain terminal connected to the second source/drain terminal of the first transistor, and a second source/drain terminal connected to the voltage output terminal, wherein the control circuit has an output terminal connected to a gate terminal of the third transistor.

15. The circuit of claim 14, wherein the control circuit is configured to output first and second control signals to the gate terminals of the first and second transistors, respectively, in response to a shutdown signal, and to output a third control signal to the gate terminal of the third transistor in response to the shutdown signal and an enable signal output by the enable circuit.

16. The circuit of claim 9, wherein the voltage output terminal is connected to an SRAM memory array.

17. A method, comprising: receiving a first voltage signal in a first power domain by a first switch;receiving a second voltage signal in a second power domain by a second switch;receiving a shutdown signal having a first logic level that indicates a shutdown mode;turning off the first switch and the second switch in response to the first logic level of the shutdown signal; and thereafterturning on the first switch in response to a decrease of the first voltage signal while in the shutdown mode.

18. The method of claim 17, wherein the first power domain is one of a VDD power domain or a VDDM power domain.

19. The method of claim 17, wherein the shutdown signal has a second logic level that indicates a memory mode, and wherein the method further comprises turning on one of the first power switch or the second power switch to output a desired one of the first voltage signal or the second voltage signal in response to the second logic level of the shutdown signal.

20. The method of claim 17, further comprising: generating an enable signal based on the decrease of the first voltage signal while in the shutdown mode; andturning on the first switch in response to the enable signal.