Patent Application
20140095814
The present disclosure pertains to managing registers that reside inside CPUs, in particular, to memory renaming mechanisms for tracking the mapping between logical registers and their corresponding physical registers to facilitate the out-of-order execution of instructions and/or micro-operations.
Hardware processors include one or more central processing unit (CPU) which each may further include a number of physical registers for staging data between various functional units as well as between memory and functional units in CPUs. Register renaming may be used to increase the speed of instruction execution by parallelizing the execution of independent writer-reader instruction sets (often referred to as lifetimes). Table 1 is an illustrative example of independent writer-reader sets.
In this example, a logical register RAX which is mapped to a physical register M inside the CPU may receive the result of the first operation. The value of the result may be stored in a memory location (at ADDRESS). Subsequently, the value stored in a different memory location (at ADDRESS′) may be loaded to logical register RAX on which a second operation may be performed. Although the memory write (Store) and memory read (Load) operations are directed at the same logical register RAX, the memory read operation is not dependent on the execution of all of the prior instructions such as the first operation, and thus the hardware assigns this second lifetime of RAX to a different physical register. For example, the write to the physical register associated with the second RAX lifetime may have completed before the full execution of the first operation. Thus, register renaming may be used to facilitate out of order execution of the independent writer-reader sets.
Embodiments are illustrated by way of example and not limitation in the Figures of the accompanying drawings:
Embodiments of the present invention may include a computer system as shown in
In one embodiment, the processor 102 includes a Level 1 (L1) internal cache memory 104. Depending on the architecture, the processor 102 can have a single internal cache or multiple levels of internal cache. Alternatively, in another embodiment, the cache memory can reside external to the processor 102. Other embodiments can also include a combination of both internal and external caches depending on the particular implementation and needs. Register file 106 can store different types of data in various registers including integer registers, floating point registers, status registers, and instruction pointer register.
Execution unit 108, including logic to perform integer and floating point operations, also resides in the processor 102. The processor 102 also includes a microcode (ucode) ROM that stores microcode for certain macroinstructions. For one embodiment, execution unit 108 includes logic to handle a packed instruction set 109. By including the packed instruction set 109 in the instruction set of a general-purpose processor 102, along with associated circuitry to execute the instructions, the operations used by many multimedia applications may be performed using packed data in a general-purpose processor 102. Thus, many multimedia applications can be accelerated and executed more efficiently by using the full width of a processor's data bus for performing operations on packed data. This can eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations one data element at a time.
Alternate embodiments of an execution unit 108 can also be used in micro controllers, embedded processors, graphics devices, DSPs, and other types of logic circuits. System 100 includes a memory 120. Memory 120 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, flash memory device, or other memory device. Memory 120 can store instructions and/or data represented by data signals that can be executed by the processor 102.
A system logic chip 116 is coupled to the processor bus 110 and memory 120. The system logic chip 116 in the illustrated embodiment is a memory controller hub (MCH). The processor 102 can communicate to the MCH 116 via a processor bus 110. The MCH 116 provides a high bandwidth memory path 118 to memory 120 for instruction and data storage and for storage of graphics commands, data and textures. The MCH 116 is to direct data signals between the processor 102, memory 120, and other components in the system 100 and to bridge the data signals between processor bus 110, memory 120, and system I/O 122. In some embodiments, the system logic chip 116 can provide a graphics port for coupling to a graphics controller 112. The MCH 116 is coupled to memory 120 through a memory interface 118. The graphics card 112 is coupled to the MCH 116 through an Accelerated Graphics Port (AGP) interconnect 114.
System 100 uses a proprietary hub interface bus 122 to couple the MCH 116 to the I/O controller hub (ICH) 130. The ICH 130 provides direct connections to some I/O devices via a local I/O bus. The local I/O bus is a high-speed I/O bus for connecting peripherals to the memory 120, chipset, and processor 102. Some examples are the audio controller, firmware hub (flash BIOS) 128, wireless transceiver 126, data storage 124, legacy I/O controller containing user input and keyboard interfaces, a serial expansion port such as Universal Serial Bus (USB), and a network controller 134. The data storage device 124 can comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.
For another embodiment of a system, an instruction in accordance with one embodiment can be used with a system on a chip. One embodiment of a system on a chip comprises of a processor and a memory. The memory for one such system is a flash memory. The flash memory can be located on the same die as the processor and other system components. Additionally, other logic blocks such as a memory controller or graphics controller can also be located on a system on a chip.
Embodiments of the present invention may include a processor including a processing unit such as a central processing unit (CPU) that further includes a storage module having stored thereon a table for tracking physical registers for store operations, the store operations storing source data from physical registers into memory, and a memory renaming module for renaming load logical register destinations to physical registers based on the table.
Embodiments of the present invention may include a method for register renaming in a processor. The method includes in response to a store operation of a producer command, writing, in an entry of a table, a physical register identification number and an associated store buffer number of the store operation, and performing the register renaming based on the table.
Embodiments of the present invention may include a method for memory renaming which includes in response to a load operation of a consumer command, predicting an entry in a memory renaming table as a potential renaming physical register, determining if the predicted entry is valid, if the predicted entry is valid, identifying a physical register ID in the predicted entry, and mapping a logical register destination of the load operation in a register alias table with the identified physical register ID.
Table 2 is an illustrative example of a different case, where the lifetime of RBX is in fact dependent on the lifetime of RAX through the memory location ADDRESS.
In this example, RAX is produced by the first operation (the producer), and moved into RBX via a store to and load from a memory location. An out-of-order (“OOO”) execution engine employs a memory renaming technique to eliminate the unnecessary latency to the second operation incurred by the store-load pair by keeping a copy of the stored data value in a location directly accessible by the execution units in the OOO. A Register Alias Table (RAT) is commonly used to track the mappings between logical registers (such as RAX) and their corresponding physical registers inside the CPU. Thus, for each Store or Load operation, the respective source or destination logical register may be associated with a respective corresponding physical register ID in the RAT. The OOO execution engine inside the CPU may execute several independent writer-reader sets (or lifetimes) of the same logical register at the same time. The youngest (latest) version of the logical register as seen at the CPU's allocator is referred to as the “current” version from which subsequent new allocating instructions/micro-operations depend on. An instruction/micro-operation may commit the result (“retire”) the instruction/micro-operation after all older (or prior) instructions/micro-operations have retired.
The exemplary Table 2 may include different execution scenarios. For example, it is possible that logical register RAX is overwritten between the Store operation and the Load operation. In such a case, the logical register RAX is being used for other computations other than the first operation at the time of the execution of the Load allocation. However, versions of the original RAX may still be alive in the out-of-order execution engine, being referenced through the corresponding physical register ID. In this scenario, memory renaming is still possible while that physical register is still alive (it contains the result of the first operation). But tracking via logical register name aliasing (such as whether RAX and RBX share the same value) is not viable because the allocation-time view of RAX already references something else when the second operation allocates.
In other cases, all of the references to the original logical register RAX have executed and retired at the time of allocation of the second operation, and thus the original physical register may have been reclaimed to the free list. In this case, the value of the original logical register is no longer in the out-of-order engine, and thus the Load operation is needed to load the value from memory. Alternatively, reclamation of the original physical register could be delayed to facilitate later memory renaming. However, the delay has a performance overhead of reducing the number of available physical registers for general out-of-order execution for the hope that the original physical register might be used for memory renaming.
The instruction fetch and decode module 202 may fetch instructions/micro-operations from an instruction cache and decode the instruction/micro-operation in preparation for execution. The decoded instructions/micro-operations may include Store operation and Load operation pairs (writer-reader sets) that may be sped up through memory renaming. In response to receiving a writer-reader set that can be optimized by memory renaming, the rename and allocation module 204 may initiate memory renaming. The rename and allocation module 204 may include a register alias table (RAT) (not shown) for tracking the mappings between logical registers and physical registers. Additionally, the rename and allocation module 204 may be communicatively connected to a storage component stored thereon a memory renaming table (MRT) 218 that tracks the physical register identification number for each store operation. Based on the information from MRT and RAT, the rename and allocation module 204 may rename logical registers, and may remove the store-load pair from the execution path by associating the destination of the load operation with the data source of the store operation, and further convert the load into a load check operation that verifies at retirement time whether the conversion was legal. It is determined to be legal provided that there were no intervening writes to the store/load memory address. A detailed discussion of the memory renaming mechanism is provided below in conjunction with the description of
The reservation station 206 is a logic circuit that may start to schedule independent operations out-of-order with respect to program (allocation) order. Consider the Load and Second Operation in Table 1. These instructions are not data dependent on the Store and First Operation, and can be executed in parallel. However, the Store instruction is data dependent on the First Operation, and so the reservation station 206 will execute those in order. Likewise, the Load and Second Operation must be executed in order. Referring to Table 2, the Load operation is data dependent on the Store operation because the Load is from the same address as the Store, thus the reservation station 206 would ensure all four instructions execute in order. In response to the initiation of memory renaming by the rename and allocation module, the reservation station 206 can execute the Second Operation out-of-order immediately after the first operation, thus bypassing memory, as well as execute the Store and Load operation (the latter converted to a load check instruction) in order following the First Operation. The execution module 208 is the logic circuit that executes the instructions. The reorder buffer and history table 210 may retain the execution results executed out-of-order, ensuring they are committed in order. In particular, the history buffer may store several mappings of logical registers to physical registers pertaining to several lifetimes of the same logical register that are alive in the out-of-order engine so that if a branch misprediction occurs, the correct mapping for the lifetime at the point of the misprediction may be restored so execution can resume on the correct path. The reorder buffer is a structure that sequentially indexing instructions in flight on a per-operation basis. After an instruction has executed (this information may be acquired from the reorder buffer), the instruction may be committed. All of the committed instructions may be indexed in the retirement reclaim table, which contains a list of the physical registers that are no longer needed once the committed instructions retire. For example, when an instruction that writes the RAX logical register retires, there can be no more instructions remaining in the machine that can refer to a previous version of RAX, and therefore the physical register that held that old value can be reclaimed to the physical register free list 216. However, through memory renaming, RBX might also be associated with the same physical register, such as at the end of the instruction sequence in Table 2. Since there may be multiple references to a physical register due to memory renaming, the physical reference list (PRL) is a data structure stored on a storage component that tracks the multiple references to the physical register. Once all references to a value have been overwritten as tracked by the PRL, an identification of the physical register may be placed on the physical register free list 216 and made available for instruction fetch and decode module 202.
Referring to
For example,
In another embodiment, MRT may contain a contiguous set of stores in the order of program code, rather than piecemeal set of still eligible stores.
Referring to
For example,
It is possible that the Producer Over-writer does not appear in the application until after the Load Over-writer.
While
In another embodiment, the MRT may always retain physical register of n past store operations (where n is an integer) to prevent these physical registers from reclamation to the free list, even if the store's data source register is overwritten and retired. If there are no references inside the out-of-order engine, the physical register is reclaimed to the free list when it exits the MRT, for example, when it is no longer one of the n most recent store operations.
To track the existence of multiple logical references to a single physical register file (PRF) entry and prevent their early reclamation, a physical reference list (PRL) 214 as shown in
In one embodiment, when a register is renamed for a Load operation, a memory execution unit (MEU) may need to perform a check to ensure that the predicted Store-to-Load data dependence actually exists. Therefore, during memory renaming, the Load operation is converted into a load check micro-operation which proceeds to execute in the memory unit, but does not write back any data values to the execution units. The MEU may perform the standard store/load ordering check based on the computed addresses of all loads and stores. The memory address of load should be aligned with the store, and that the size of load should be the same or smaller than the size of the store. If the load address and size do not match those of the store, the load operation should trigger a fault condition and should be re-executed without performing memory renaming.
While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.
