MEMORY SYSTEM INCLUDING A POWER DIVIDER ON A MULTI MODULE MEMORY BUS

Abstract

A memory system includes a memory controller, a transmission bus, a power divider, a first memory chip, and a second memory chip. The transmission bus is coupled from the memory controller to a first node of the power divider for transferring signals. The first node of the power divider is coupled to a second node of the power divider via a first line, and the first node is also coupled to a third node of the power divider via a second line. The first memory chip is coupled to the second node via a first branch bus and the second memory chip is coupled to the third node via a second branch bus. Accordingly, reflected wave due to an impedance mismatching can be reduced to enhance the signal integrity.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating a conventional memory system including a multi-module memory bus architecture with On-Die Termination (ODT).

FIGS. 2 and 3 are block diagrams illustrating a memory system including a Wilkinson power divider on a multi module memory bus according to an embodiment of the present invention.

FIG. 4 is a graph illustrating an improved AC response in a write operation of the memory system shown in FIG. 2.

FIG. 5 is a graph illustrating an improved AC response in a read operation of the memory system shown in FIG. 3.

FIG. 6 is an eye diagram illustrating an eye pattern of a memory chip in the memory module for conventional memory devices without a power divider.

FIG. 7 is an eye diagram for embodiments including a power divider in a write operation at 4 Gbps.

FIG. 8 is an eye diagram illustrating an eye pattern of a memory chip in the memory module 130 for conventional memory devices without a power divider.

FIG. 9 is an eye diagram for embodiments including a power divider in a write operation at 6 Gbps.

FIG. 10 is an eye diagram illustrating an eye pattern of a memory controller chip for conventional memory devices without a power divider.

FIG. 11 is an eye diagram for embodiments including a power divider in a read operation at 4 Gbps.

FIG. 12 is an eye diagram illustrating an eye pattern of a memory controller chip for conventional memory devices without a power divider.

FIG. 13 is an eye diagram for embodiments including a power divider in a read operation at 6 Gbps.

FIG. 14 is a picture of a test board for testing a multi-module memory bus architecture including a power divider according to an embodiment of the present invention.

FIG. 15 is an extended picture of a dotted area shown in FIG. 14.

FIG. 16 is a diagram illustrating a measured s-parameter of a signal applied to a test board in relation to the frequency.

FIG. 17 is a diagram illustrating a waveform for conventional memory devices without a Wilkinson power divider.

FIG. 18 is a diagram illustrating a waveform of an output signal at a third port for embodiments including a Wilkinson power divider, such as those shown in FIG. 15.

Claims

1. A memory system comprising: a memory controller;a transmission bus configured to transfer signals, wherein a first end of the transmission bus is coupled to the memory controller;a power divider having first, second, and third nodes, the first node of the power divider being coupled to a second end of the transmission bus;a first memory chip coupled to the second node via a first branch bus; anda second memory chip coupled to the third node through a second branch bus.

2. The memory system of claim 1, wherein the power divider further comprises: a first line between the first and second nodes having a first length;a second line between the first and second nodes having a second length; andan absorption resistor coupled between the second and third nodes.

3. The memory system of claim 2, wherein the first length and the second length are substantially equal to each other and each of the first length and the second length corresponds to one fourth of a wavelength of a transferred signal.

4. The memory system of claim 3, wherein each line length of the first and second branch buses is substantially equal to each of the first and second line lengths.

5. The memory system of claim 3, wherein the first and second lines include a micro strip line and a strip line, respectively.

6. The memory system of claim 2, wherein the power divider is a Wilkinson power divider.

7. The memory system of claim 1, wherein the first and second memory chips correspond to master chips.

8. The memory system of claim 1, wherein the first and second branch buses includes only a wire line without mounting a stub resistor.

9. A memory system comprising a module board;a data input/output(I/O) terminal;a transmission bus formed on the module board for transferring signals, wherein one end of the transmission bus is coupled to the I/O terminal;a power divider formed on the module board having first, second, and third nodes, the first node of the power divider being coupled to another end of the transmission bus;a first memory chip coupled to the second node via a first branch bus and mounted on the module board; anda second memory chip connected to the third node via a second branch bus and mounted on the module board.

10. A memory system comprising: a memory controller;a power divider including a first, second, and third node, where the first node is connected to the second node via a first line having a first line length, the first node is connected to the second node via a second line having a second line length, and the second node is connected to the third node via a line including an absorption resistor;a transmission bus coupled between the memory controller and the first node of the power divider, the transmission bus structured to transfer a signal having a characteristic wavelength between the memory controller and the power divider;a first memory module coupled to the second node of the power divider via a first socket, the first memory module including a first memory chip and a first branch bus having a first branch length connecting the first memory chip to the first socket; anda second memory module coupled to the third node of the power divider via a second socket and a wire line having a third line length, the second memory module including a second memory chip and a second branch bus having a second branch length connecting the second memory chip to the second socket,wherein the first line length is substantially equal to the second line length, the first branch length, and the sum of the third line length and the second branch length.

11. The memory system of claim 10, wherein the first line length is structured to be substantially equal to one fourth of the characteristic wavelength of the signal transferred over the transmission bus.

12. The memory system of claim 11, wherein the first and second branch bus do not include stub resistors.

13. A method of enhancing signal integrity on a multi module memory bus, the method comprising: transmitting a signal having a characteristic wavelength from a memory controller;receiving the transmitted signal at a first node of a power divider;directing the signal over a first line connecting the first node of the power divider to a second node of the power divider and substantially simultaneously directing the signal over a second line connecting the first node of the power divider to a third node of the power divider, where each of the first and second lines have a length substantially equal to one fourth of the characteristic wavelength;directing the signal at the second node to a first memory chip on a first memory module via a first branch bus having a length substantially equal to one fourth of the characteristic wave length; anddirecting the signal at the third node to a second memory chip on a second memory module via a third line and a second branch bus, where a sum of lengths of the third line and second branch bus is substantially equal to one fourth of the characteristic wave length.