Patent Application
20150310901
1. Field
The present disclosure relates generally to electronic circuits, and more particularly, a memory with a sleep mode.
2. Background
With the ever increasing demand for more processing capability in mobile devices, low power consumption has become a common design requirement. Various techniques are currently being employed to reduce power consumption in such devices. One example of such technique is a sleep mode in which all power supplies to a memory are disconnected. As a result, the memory operating in such sleep mode would draw no power.
Aspects of a memory are disclosed. The memory includes one or more storage elements. A bitline is coupled to the one or more storage elements. A precharge circuit configured to precharge the bitline during a precharge period and float the bitline during the sleep mode. A operating circuit is configured operate a part of the memory and is configured to remain electrically coupled to a supply voltage in the sleep mode.
Further aspects of a memory are disclosed. The memory includes a bitline and one or more storage means for storing a value. The one or more storage means are coupled to the bitline. The memory includes precharging means for precharging the bitline during a precharge period and floating the bitline during the sleep mode. Operating means for operating a part of the memory is configured to remain electrically coupled to a supply voltage in the sleep mode.
Aspects of a method for operating a memory are disclosed. The method includes precharging a bitline during a precharge period. The bitline is coupled to one or more storage elements. The method further includes entering a sleep mode and floating the bitline. An operating circuit configured to operate a part of the memory remains electrically coupled to a supply voltage in the sleep mode.
It is understood that other aspects of apparatus and methods will become readily apparent to those skilled in the art from the following detailed description, wherein various aspects of apparatus and methods are shown and described by way of illustration. As will be realized, these aspects may be implemented in other and different forms and its several details are capable of modification in various other respects. Accordingly, the drawings and detailed description are to be regarded as illustrative in nature and not as restrictive.
Various aspects of apparatus and methods will now be presented in the detailed description by way of example, and not by way of limitation, with reference to the accompanying drawings, wherein:
The detailed description set forth below in connection with the appended drawings is intended as a description of various exemplary embodiments of the present invention and is not intended to represent the only embodiments in which the present invention may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring the concepts of the present invention. Acronyms and other descriptive terminology may be used merely for convenience and clarity and are not intended to limit the scope of the invention.
Various apparatus and methods presented throughout this disclosure may be implemented in various forms of hardware. By way of example, any of these apparatus or methods, either alone or in combination, may be implemented as an integrated circuit, or as part of an integrated circuit. The integrated circuit may be an end product, such as a microprocessor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), programmable logic, or any other suitable integrated circuit. Alternatively, the integrated circuit may be integrated with other chips, discrete circuit elements, and/or other components as part of either an intermediate product, such as a motherboard, or an end product. The end product can be any suitable product that includes integrated circuits, including by way of example, a cellular phone, personal digital assistant (PDA), laptop computer, a desktop computer (PC), a computer peripheral device, a multimedia device, a video device, an audio device, a global positioning system (GPS), a wireless sensor, or any other suitable device.
The word “exemplary” is used herein to mean serving as an example, instance, or illustration. Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term “embodiment” of an apparatus or method does not require that all embodiments of the invention include the described components, structure, features, functionality, processes, advantages, benefits, or modes of operation.
The terms “connected,” “coupled,” or any variant thereof, mean any connection or coupling, either direct or indirect, between two or more elements, and can encompass the presence of one or more intermediate elements between two elements that are “connected” or “coupled” together. The coupling or connection between the elements can be physical, logical, or a combination thereof. As used herein, two elements can be considered to be “connected” or “coupled” together by the use of one or more wires, cables and/or printed electrical connections, as well as by the use of electromagnetic energy, such as electromagnetic energy having wavelengths in the radio frequency region, the microwave region and the optical (both visible and invisible) region, as several non-limiting and non-exhaustive examples.
Any reference to an element herein using a designation such as “first,” “second,” and so forth does not generally limit the quantity or order of those elements. Rather, these designations are used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements can be employed, or that the first element must precede the second element.
As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of the stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Various aspects of a memory on an integrated circuit (IC) having a novel sleep mode will now be presented. Such IC may be, for example, a system-on-chip (SOC) processor for a communication apparatus (such as mobile phone). However, as those skilled in the art will readily appreciate, such aspects may be extended to other circuit configurations. Accordingly, all references to a specific application for a memory is intended only to illustrate exemplary aspects of the memory with the understanding that such aspects may have a wide differential of applications.
The memory 100 may be any suitable storage medium, such as, by way of example, a static random access memory (SRAM). SRAM is volatile memory that requires power to retain data. However, as those skilled in the art will readily appreciate, the memory 102 is not necessarily limited to SRAM. Accordingly, any reference to SRAM is intended only to illustrate various concepts, with the understanding that such concepts may be extended to other memories.
SRAM includes an array of storage elements know as “bitcells.” Each bitcell is configured to store one bit of data.
The bitcell 300 is shown with two inverters 302, 304. The first inverter 302 comprises a P-channel transistor 306 and an N-channel transistor 308. The second inverter 304 comprises a P-channel transistor 310 and an N-channel transistor 312. The first and second inverters 302, 304 are interconnected to form a cross-coupled latch. A first N-channel write access transistor 314 couples the output 316 from the first inverter 302 to a first local write bitline W-BLB and a second N-channel write access transistor 318 couples the output 320 from the second inverter 304 to a second local write bitline W-BL. The gates of the N-channel write access transistors 314, 318 are coupled to a write wordline W-WL. The output 316 from the first inverter 302 is also coupled to the gate of an N-channel transistor 322. An N-channel read access transistor 324 couples the output from the N-channel transistor 322 to a local read bitline R-BL. The gate of the N-channel read access transistor 324 is coupled to a read wordline R-WL.
The write operation is initiated by setting the local write bitlines W-BLB, W-BL to the value to be written to bitcell 300 and then asserting the write wordline W-WL. By way of example, a logic level 1 may be written to the bitcell 300 by setting the first local write bitline BLB to a logic level 0 and the second local write bitline BL to a logic level 1. The logic level 0 at the first local write bitline W-BLB is applied to the input of the second inverter 304 through the write access transistor 314, which in turn forces the output 320 of the second inverter 304 to a logic level 1. The output 320 of the second inverter 304 is applied to the input of the first inverter 302, which in turn forces the output 316 of the first inverter 302 to a logic level 0. A logic level 0 may be written to the bitcell 300 by inverting the values of the local write bitlines W-BLB, W-BL. The local write bitline drivers (not shown) are designed to be much stronger than the transistors in the bitcell 300 so that they can override the previous state of the cross-coupled inverters 302, 304.
The read operation is initiated by precharging the local read bitline R-BL to a logic level 1 and then asserting the read wordline R-WL. With the read wordline asserted, the output from the N-channel transistor 322 is transferred to the local read bitline R-BL through the read access transistor 324. By way of example, if the value stored at the output 320 of the second inverter 304 is a logic level 0, the output 316 from the first inverter 302 forces the N-channel transistor 322 on, which in turn causes the local read bitline R-BL to discharge to a logic level 0 through the read access transistor 324 and the N-channel transistor 322. If the value stored at the output 320 of the second inverter 304 is a logic level 1, the output 316 from the first inverter 302 forces the N-channel transistor 322 off As a result, the local read bitline R-BL remains charged to a logic level 1.
When the SRAM is in a standby mode, the write wordline W-WL and read wordline R-WL are set to a logic level 0. The logic level 0 causes the write access transistors 314, 318 and the read access transistor 324 to disconnect the local write and read bitlines W-BL, W-BLB, R-BL from the two inverters 302, 304. The cross-coupling between the two inverters 302, 304 maintains the state of the output as long as power is applied to the bitcell 300.
The SRAM 400 includes a memory core 402 with supporting circuitry to decode addresses and perform read and write operations. The memory core 402 is comprised of bitcells arranged to share connections in horizontal rows and vertical columns. Specifically, each horizontal row of bitcells shares a read wordline and each vertical column of bitcells shares a local read bitline. The size of the memory core 402 (i.e., the number of bitcells) may vary depending on a variety of factors including the specific application, the speed requirements, the layout and testing requirements, and the overall design constraints imposed on the system. Typically, the memory core 402 will contain thousands or millions of bitcells.
In the exemplary embodiment of the SRAM shown in
The row decoder 404 converts the n-bit address into 2n read wordline outputs. A different read wordline is asserted by the row decoder 404 for each different n-bit row address. As a result, each of the 2m bitcells in the horizontal row with the asserted read wordline is connected to one of the 2m local read bitlines 480 through its access transistor as described above in connection with
The multiplexer and global read bitline precharge 408 includes the circuits to perform the multiplexing or selecting function described above. The multiplexer and global read bitline precharge 408 further includes circuits that precharge the global read bitline 482 for the read operation. The global read bitline 482 output from the multiplexer and global read bitline precharge 408 is provided to a data latch 410 for further processing before being output to a peripheral circuit (not shown). In one example, the data latch 410 provides the data from the global read bitline 482 to the execution unit 210 or the modem 220.
A sleep mode in which the memory is electrically decoupled from all power supplies is known as a deep sleep mode. The deep sleep mode is advantageous in that the memory consumes no power in such mode. However, activating the memory for an access from the deep sleep mode may require substantial delays (e.g., additional wait delays may need to be added intentionally after exiting the deep sleep mode).
Thus, at least one portion of the memory (e.g., one of a control circuit and the storage elements) remains electrically coupled to the supply voltage in the sleep mode. The portions of the memory remaining electrically coupled to the supply voltage in the sleep mode are configured such that, in response to an end of the sleep mode, the memory may enter the subsequent memory access with no delay. In one example, there are no wait delays added between the exiting of the sleep mode and the start of the subsequent memory access (e.g., the precharge period of the subsequent memory access). As would be understood by one of ordinary skill in the art, the supply voltage may be read broadly for supplying a plurality of voltage levels.
As illustrated, the memory core 402 includes a plurality of storage elements (520, 522, or 524, etc.) coupled to the read wordline R-WL and coupled to the local read bitline 480. The storage elements may be examples of the memory bitcells and provide the means for storing a value. A storage element may be, for example, an SRAM or other type of memory cell that stores a value (e.g., a value that may be read as a logic “1” or a logic “0”). Accordingly, the local read bitline 480 is directly coupled to at least one storage element (520, 522, or 524, etc.) at least because the coupling is not via another bitline.
A read memory access of the memory may start with a precharge operation in a precharge period, in which the bitlines (such as the local read bitline 480 or the global read bitline 482) are precharged or pulled-up to, e.g., VDD level. A read operation may follow the precharge operation and outputs the stored value onto the global read bitline 482 based on the stored value of a storage element (520, 522, or 524, etc.). In one example, the valued is outputted onto the global read bitline 482 via the local read bitline 480. First, the read wordline R-WL goes high to select a storage element (520, 522, or 524, etc.). The selected storage element (520, 522, or 524, etc.) may selectively output a value onto the local read bitline 480 based on its stored value. As illustrated in
The local read bitline 480 is precharged by the local read bitline precharge circuit 412 to VDD level (e.g., in a precharge period prior to the read operation). In the exemplary embodiment, the local read bitline precharge 412 receives a precharge trigger PRE_N and the sleep mode signal LIGHTSLEEP. When the memory of the exemplary embodiment is not in the sleep mode (i.e., LIGHTSLEEP is low), the precharge trigger PRE_N goes low to initiate the precharging of the local read bitline 480. The precharge trigger PRE_N going low turns on the P-channel MOS precharge transistor 516 (e.g., the pull up device), which is coupled to a supply voltage VDD and precharges or pulls up the local read bitline 480 to VDD level. Accordingly, in the exemplary embodiment, the precharge transistor 516 provides the means to precharge or pull up the local read bitline 480 during the precharge period.
When the memory of the exemplary embodiment enters the sleep mode, the sleep mode signal LIGHTSLEEP goes high, and in response, the logic elements of the local read bitline precharge circuit 412 disable the precharge trigger PRE_N from being provided to the pull up device (e.g., the precharge transistor 516) during the sleep mode.
In other words, the logic elements of the local read bitline precharge circuit 412 are configured to remove the precharge trigger PRE_N from the pull up device (e.g., the precharge transistor 516) during the sleep mode. The precharge circuit (e.g., precharge transistor 516) is deactivated during the sleep mode. As illustrated in
Accordingly, the precharge transistor 516 is kept in the off state, and the memory does not enter precharge mode (e.g., the precharge transistor 516 does not precharge or pull up the local read bitline 480) regardless of the state of the precharge trigger PRE_N. Thus, the precharge circuit (e.g., the precharge transistor 516) is deactivated in the precharge period and does not precharge or pull up the local read bitline 480. In one example, the precharge trigger PRE_N may continue to operate (going into low state) in the sleep mode.
In the exemplary embodiment, deactivating the precharge circuit (e.g., precharge transistor 516) floats the local read bitline 480 in the sleep mode. That is, the local read bitline 480 is not electrically coupled to any supply voltage or ground in the sleep mode.
The local read bitline 480 is provided to the multiplexer and global read bitline precharge circuit 408 and via which couples to the global read bitline 482. The multiplexer and global read bitline precharge circuit 408 includes a multiplexer portion 540 and a global read bitline precharge portion 530. The multiplexer portion 540 performs the multiplexing function, e.g., selecting a local read bitline 480 from a plurality of local read bitlines and coupling the selected local read bitline 480 to the global read bitline 482. As such, the multiplexer portion 540 may be implemented using various circuits known by one of ordinary skill in the art. For example, the multiplexer function may be implemented using pass gates. In the exemplary embodiment, the multiplexer portion 540 includes multiplexed pull-down circuits 540-1 to 540-2m. The multiplexer portion 540 performs the multiplexing or selecting function by way of selectively pulling down (e.g., via the pull-down transistor 544 and the selection transistor 546) one of the multiplexed pull-down circuits 540-1 to 540-2m. The selection is performed by signals from the column decoder 406. Each of the pull-down circuits 540-1 to 540-2m receives a different read bitline 480 and is controlled by an associated signal from the column decoder 406.
The global read bitline 482 is precharged or pulled up to VDD level by the global read bitline precharge circuit 530 (e.g., in the precharge operation prior to the read operation). The local read bitline 480 couples to the global read bitline 482 via the inverter 542 and the pull-down transistor 544. The pull-down transistor 544 is selected by the selection transistor 546. A plurality of such pull-down circuits is coupled in parallel to the global read bitline 482. In a read operation of the exemplary embodiment, the value stored in the selected storage element (520, 522, or 524, etc.) is coupled to the local read bitline 480 (e.g., the selected storage element selectively pulling down the local read bitline 480 based on the stored value). The local read bitline 480 is then selectively coupled to the global read bitline 482. For example, only one of the selection transistors is selectively turned on, allowing only the associated local read bitline 480 to pull down or couple to the global read bitline 482 via the pull-down transistor 544. In the exemplary embodiment, the selection transistor 546 is controlled by signals from the column decoder 406 to perform the multiplexing or selection function.
In the exemplary embodiment, the global read bitline precharge circuit 530 receives the precharge trigger PRE_N and the sleep mode signal LIGHTSLEEP. When the memory of the exemplary embodiment is not in the sleep mode (i.e., LIGHTSLEEP is low), the precharge trigger PRE_N goes low to initiate the precharging of the global read bitline 482. The precharge trigger PRE_N going low turns on the P-channel MOS precharge transistor (e.g., the pull up device) 536, which is coupled to a supply voltage VDD and precharges or pulls up the global read bitline 482 to VDD level. Accordingly, in the exemplary embodiment, the precharge transistor 536 provides the means to precharge or pull up the global read bitline 482.
When the memory of the exemplary embodiment enters the sleep mode, the sleep mode signal LIGHTSLEEP goes high. The sleep mode signal LIGHTSLEEP going high keeps the precharge transistor 536 in the off state, and therefore, the memory does not enter precharge mode (e.g., the precharge transistor 536 does not precharge or pull up the global read bitline 482) regardless of the state of the precharge trigger PRE_N. Thus, the precharge circuit (e.g., the precharge transistor 536) is deactivated in the precharge period and does not precharge or pull up the global read bitline 482. Accordingly, in the exemplary embodiment, the precharge transistor 536 provides the means to float the global read bitline 482. In one example, the precharge trigger PRE_N may continue to operate (going into low state) in the sleep mode.
In the exemplary embodiment, deactivating the precharge circuit (e.g., precharge transistor 536) floats the global read bitline 482 in the sleep mode. That is, the global read bitline 482 is not electrically coupled to any supply voltage or ground in the sleep mode.
As illustrated in
At T1, the precharge trigger PRE_N and the PRE_ENABLE go to a high state, and the memory exits the precharge operation. Subsequently, the memory starts the read operation by, e.g., selectively pulling down the local read bitline 480 based on the stored value of the selected storage element (520, 522, or 524, etc.). The local read bitline 480 may further selectively pull down the global read bitline 482 based the operation of the multiplexer portion 540 (which is controlled by the column decoder 406). At T2, the read memory access is completed.
At T3, the sleep mode signal LIGHTSLEEP goes to a high state, and the memory enters the sleep mode. As a result, the PRE_ENABLE is driven high and disables the precharge transistors 516 and 536. The local read bitlines 480 and global read bitline 482 are thus electrically decoupled from the supply voltage VDD, and are floating while in the sleep mode. At T4-T5, the precharge trigger PRE_N continues to operate during the sleep mode (going to the active low state at T4). As described with
At T6, the sleep mode signal LIGHTSLEEP goes to a low state, and the memory exits the sleep mode. The memory is in a ready state for the next memory access, which may start with no wait delay. For example, no wait or delay states are needed before the subsequent memory access (starting the precharge period for the subsequent memory access) starts at T6, in response to the end of the sleep mode.
The specific order or hierarchy of blocks in the method of operation described above is provided merely as an example. Based upon design preferences, the specific order or hierarchy of blocks in the method of operation may be re-arranged, amended, and/or modified. The accompanying method claims include various limitations related to a method of operation, but the recited limitations are not meant to be limited in any way by the specific order or hierarchy unless expressly stated in the claims.
The various aspects of this disclosure are provided to enable one of ordinary skill in the art to practice the present invention. Various modifications to exemplary embodiments presented throughout this disclosure will be readily apparent to those skilled in the art, and the concepts disclosed herein may be extended to other magnetic storage devices. Thus, the claims are not intended to be limited to the various aspects of this disclosure, but are to be accorded the full scope consistent with the language of the claims. All structural and functional equivalents to the various components of the exemplary embodiments described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed under the provisions of 35 U.S.C. §112(f) unless the element is expressly recited using the phrase “means for” or, in the case of a method claim, the element is recited using the phrase “step for.”
