Memory

Abstract

A memory capable of operating at a high speed is obtained. This memory includes memory cells arranged on the intersectional positions between bit lines and word lines respectively. A read operation and a first and second rewrite operations performed when reading data of the memory cells are started by changing voltages applied to the bit lines and the word lines to applied voltages responsive to each operation, and when each operation performed when reading data of the memory cells is transferred, the voltages applied to the bit lines and the word lines are directly changed from the applied voltages responsive to the operation before transition to the applied voltages responsive to the operation after transition.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram for illustrating an overall structure of a ferroelectric memory according to a first embodiment of the present invention;

FIG. 2 is a circuit diagram showing an internal structure of a sense amplifier of the ferroelectric memory according to the first embodiment shown in FIG. 1;

FIGS. 3 and 4 are voltage waveform diagrams for illustrating operations of the ferroelectric memory according to the first embodiment of the present invention;

FIG. 5 is a voltage waveform diagram for illustrating an experiment conducted for confirming effects of the first embodiment;

FIG. 6 is a graph showing measurement results (changes in quantities of polarization inversion charges) of the experiment conducted for confirming effects of the first embodiment;

FIGS. 7 and 8 are voltage waveform diagrams for illustrating operations of the ferroelectric memory according to a second embodiment of the present invention; and

FIG. 9 is a voltage waveform diagram for illustrating operations of a ferroelectric memory of related art.

Claims

1. A memory comprising: bit lines and word lines arranged to intersect with each other, andmemory cells arranged on the intersectional positions between said bit lines and said word lines respectively, whereina read operation and a rewrite operation consisting of a plurality of operations are performed when data of said memory cells is read,said read operation and said rewrite operation consisting of said plurality of operations performed when reading data of said memory cells are started by changing voltages applied to said bit lines and said word lines to applied voltages responsive to each operation, andwhen each operation performed when reading data of said memory cells is transferred, the voltages applied to said bit lines and said word lines are directly changed from the applied voltages responsive to the operation before transition to the applied voltages responsive to the operation after transition.

2. The memory according to claim 1, further comprising holding portions for holding a reading voltage outputted from said memory cells to said bit lines, wherein said reading voltage is outputted from said memory cells to said bit lines by changing the voltages applied to said bit lines and said word lines to the applied voltages responsive to said read operation, and amplified after being held by said holding portions, andthe voltages responsive to said rewrite operation are applied to said bit lines and said word lines in parallel with a period during which said reading voltage is amplified.

3. The memory according to claim 2, wherein the voltage applied to said bit lines is switched based on amplified said reading voltage after said reading voltage outputted to said bit lines is amplified, when a voltage responsive to said rewrite operation is applied to said bit line.

4. The memory according to claim 1, wherein a first voltage pulse providing an electrical field in a first direction and a second voltage pulse providing an electrical field in a direction opposite to said first direction are applied to at least nonselected said memory cell throughout said read operation and said rewrite operation consisting of said plurality of operations performed when reading data of said memory cells.

5. The memory according to claim 4, wherein frequencies of application in one cycle of said first voltage pulse and said second voltage pulse are at least once, and difference between frequencies of application in one cycle of said first voltage pulse and said second voltage pulse is at most once.

6. The memory according to claim 5, wherein the frequencies of application in one cycle of said first voltage pulse and said second voltage pulse are once and twice respectively.

7. The memory according to claim 5, wherein the frequencies of application in one cycle of said first voltage pulse and said second voltage pulse are the same.

8. The memory according to claim 1, wherein said rewrite operation includes a first rewrite operation and a second rewrite operation, and is constituted so as to directly change from the voltage responsive to said first rewrite operation to the voltage responsive to said second rewrite operation.

9. The memory according to claim 8, wherein a reading voltage outputted to said bit lines is amplified after transition from said read operation to said first rewrite operation.

10. The memory according to claim 9, wherein said bit lines are controlled at a potential at which no data is written in said memory cells, in a period during which the reading voltage outputted to said bit lines is amplified of a period of said first rewrite operation.

11. The memory according to claim 9, wherein a second data different from a first data is rewritten in said memory cell in which said first data is written, and no data is rewritten in said memory cell in which said second data is written after a period during which the reading voltage outputted to said bit lines is amplified, in said first rewrite operation.

12. The memory according to claim 8, wherein a first data is rewritten in said memory cell in which said first data is written, and no data is rewritten in said memory cell in which a second data is written, in said second rewrite operation.

13. The memory according to claim 12, wherein the voltages applied to said bit lines and said word lines are directly changed to the applied voltages responsive to said read operation, after said first data is rewritten in said memory cell in which said first data is written, or no data is rewritten in said memory cell in which said second data is written, in said second rewrite operation.

14. The memory according to claim 8, wherein a first voltage pulse providing an electrical field in a first direction and a second voltage pulse providing an electrical field in a direction opposite to said first direction are applied to at least a part of nonselected said memory cells in said second rewrite operation.

15. The memory according to claim 14, wherein both frequencies of application in one cycle of said first voltage pulse and said second voltage pulse are twice.

16. The memory according to claim 2, further comprising bit line control portions for controlling potentials of said bit lines, provided between said memory cells and said holding portions respectively.

17. The memory according to claim 16, wherein each of said bit line control portions includes a plurality of signal lines supplying a voltage for controlling said bit line at the applied voltage responsive to each operation in a period of said rewrite operation consisting of said plurality of operations.

18. The memory according to claim 16, wherein a transistor for electrically isolating each of said bit line control portions and each of said holding portions from each other is provided between each of said bit line control portions and each of said holding portions.

19. The memory according to claim 1, wherein each of said memory cells includes a ferroelectric capacitor.

20. The memory according to claim 19, wherein each of said memory cells includes a first ferroelectric capacitor in which a first data is written and a second ferroelectric capacitor in which a second data different from said first data is written.