Patent Application
20070284654
These and other features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings that depict various embodiments of the invention, in which:
It is noted that the drawings of the invention are not to scale. The drawings are intended to depict only typical aspects of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements between the drawings.
Referring to
As illustrated, transistor device 100 (
Next, as shown in
As shown in
The above-described embodiments may also be enabled to address the loss of stress in a channel 130 of transistor device 100 caused by the use of thinner silicon 114. As known in the art, tensile stress enhances electron mobility in an nFET type transistor device 100, and a compressive stress enhances hole mobility in a pFET type transistor device 100. In an alternative embodiment, metal alloy layer 120 may include a stress coupled to a channel 130 of transistor device 100. The stress level can be controlled by the manner of deposition, and can be modulated by the composition and thickness of metal alloy layer 120 and the thermal budget of the post-deposition processes. Additionally, the stress level may be controlled by the make up of conductive region(s) 102, e.g., silicide, and middle-of-the-line (MOL) materials deposited underneath and above metal alloy layer 120, respectively, and the thermal cycles used in the fabrication process of the device. Hence, metal alloy layer 120 may be employed to compensate for the loss of an ability to impart stress into channel 130 posed by thinner silicon 114.
Transistor device 100 includes a conductive region(s) 102 including at least one first conductive material, and metal alloy layer 120 disposed on substantially all of a surface of conductive region(s) 102. As stated above, metal alloy layer 120 includes a second conductive material different than the at least one first conductive material. Metal alloy layer 120 provides a low parasitic resistance contact to source 104, drain 106 and/or gate 108. One reason for the lower parasitic resistance is the thicker conductive material, and another reason is that the silicide and alloy material interface is free of oxygen, thus preventing creation of additional parasitic resistance. As such, metal alloy layer 120 removes the need for an RSD 10 (
In one illustrative implementation, an ultra-thin Si channel nFET was fabricated on lightly doped p-type <100> bonded SOI wafer. The initial SOI layer was thinned by thermal oxidation to target a final channel thickness of 10 nm underneath the gate oxide. Device isolation was achieved using a mesa isolation approach. A traditional polysilicon gate nFET process flow was used to fabricate nMOS transistors with gate lengths down to 20 nm. An ultra-thin layer (60 Å) of nickel or cobalt silicide, commensurate with the thin Si channel, was then formed in the source/drain and gate regions. To decrease the resistance associated with the ultra-thin silicide, a thicker conducting (metal alloy) layer was selectively deposited in the source/drain and gate silicide areas using the above-described embodiments of the invention. A metal alloy layer of cobalt-tungsten-phosphorous (CoWP)(25-50 nm) was selectively deposited on the thin metal silicides with an electroless process. Both cross-sectional scanning electron microscope (XSEMs) and electrical measurement of leakage current showed excellent selectivity for the above-described embodiments.
The foregoing description of various aspects of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously, many modifications and variations are possible. Such modifications and variations that may be apparent to a person skilled in the art are intended to be included within the scope of the invention as defined by the accompanying claims.
