Metal-Induced Crystallization of Amorphous Silicon in Thin Film Transistors

Abstract

The invention provides a method for forming thin film transistors including a polycrystalline semiconducting film. The method comprises depositing a first layer of amorphous semiconducting thin film on to a substrate; depositing a second layer of thin film on to the first layer of amorphous semiconducting thin film; patterning the second layer or thin film so that the first layer of amorphous semiconducting thin film is exposed at selected locations; exposing the first and second layers of thin film to a nickel containing compound in either a solution or a vapor phase; removing the second layer of thin film; and annealing the first layer of amorphous semiconducting thin film at an elevated temperature so the first layer of amorphous semiconducting thin film converts into a polycrystalline semiconducting thin film.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

Further features and advantages of the invention may be understood by reviewing the following detailed description of the preferred embodiments taken in conjunction with the accompanying drawings in which:

FIGS. 1 a and 1b are schematic drawings of the MILC process and the nickel distribution of the poly-Si crystallized using the induced hole;

FIGS. 2 a and 2b are schematic drawings of disk-like MILC Poly-Si process, where silicon nitride is used as the cover layer;

FIGS. 3 a-c are schematic drawings of the MILC process and the distribution of nickel;

FIG. 4 is a schematic drawing of the crystalline nucleation sites and the nickel supplementary sites to result in the disk-like grain MILC poly-Si;

FIG. 5 is a schematic drawing of the disk-like grain arranged to honeycomb grain;

FIG. 6 is a photomicrograph of the poly-Si with honeycomb grain etched with TMAH;

FIG. 7 is a photomicrograph of the poly-Si with honeycomb grain etched with Secco;

FIG. 8 is a schematic drawing of the crystalline nucleation sites and the nickel supplementary sites to result in the MILC poly-Si with parallel line structure grains;

FIG. 9 is a photomicrograph of the parallel line structure of poly-Si etched by TMAH; and

FIG. 10 is a photomicrograph of the parallel line structure of poly-Si etched by Secco.

Claims

1. A method of forming a polycrystalline silicon film comprising the steps: depositing a first layer of amorphous silicon thin film on a substrate;forming a second layer of thin film on the first layer of amorphous silicon thin film; patterning the second layer of thin film so that the first layer of amorphous silicon thin film is exposed at selected locations;depositing a thin layer of a nickel containing compound on the exposed selected locations on the first amorphous silicon thin film;removing the second layer of thin film to form a composite layer of thin film; andannealing the resulting composite layer of thin film at a sufficient temperature to convert the first layer of amorphous silicon thin film into polycrystalline silicon.

2. A method according to claim 1, wherein the step of patterning the second layer comprises exposing major and minor areas of the first layer, and wherein the second layer is removed if the second layer is organic.

3. A method according to claim 1, additionally comprising forming a native silicon oxide layer on the exposed locations on the first layer of amorphous silicon thin film.

4. A method according to claim 2, additionally comprising forming a native silicon oxide layer on the exposed locations on the first layer of amorphous silicon thin film.

5. A method of forming a polycrystalline silicon film comprising: depositing a first layer of amorphous silicon thin film on a substrate;forming of a second layer of thin silicon oxide film on the first layer;patterning the second layer of thin silicon oxide film to expose selected areas of the first layer;forming a thin native silicon oxide layer on the exposed areas of the first layer;depositing a thin layer of a nickel containing compound on the first layer to form a resulting composite layer; andannealing the resulting composite layer at a sufficient temperature to covert first layer into polycrystalline silicon.

6. A method of forming an array of thin film transistors, comprising; forming a continuous layer of polycrystalline silicon thin film on a substrate;patterning the continuous layer of polycrystalline silicon thin film into an array of active channels;providing source, drain, and gate connections to the active channels; andproviding interconnections to the source, drain and gate connections to form an array of thin film transistors.

7. A method according to with claim 4, wherein the substrate is glass.

8. A method according to claim 4, wherein the first layer is formed by PECVD, LPCVD or a sputtering process.

9. A method according to with claim 8, wherein the first layer has a thickness that ranges from about 10 nm to about 300 nm.

10. A method according to with claim 4, wherein the second layer is a photoresist or silicon oxide.

11. A method according to with claim 10, wherein the second layer of silicon oxide has a thickness of about 2 nm to about 10 nm.

12. A method according to claim 4, wherein the native silicon oxide layer thickness has a range from about 0 to about 4 nm.

13. A method according to claim 12, wherein patterning the second layer of thin film is performed by photolithography.

14. A method according to claim 4, wherein the pattern in the second layer is a series of circular holes with diameters ranging from about 2 to about 30 microns arranged in a square lattice.

15. A method according to claim 4, wherein the pattern of the second layer is a series of circular holes with diameters ranging from about 2 to about 30 microns arranged in a hexagonal lattice.

16. A method according to claim 4, wherein the pattern of the second layer is a series of long parallel strips having widths ranging from about 0.5 to about 10 microns, and the distance between the strips is about 10 to about 90 microns.

17. A method according to claim 4, wherein the pattern of the major areas of the second layer is a series of circular holes having diameters ranging from about 2 to about 30 microns arranged in a square lattice.

18. A method according to claim 4, wherein the pattern of the major areas of the second layer is a series of circular holes with diameters ranging from about 2 to about 30 microns arranged in a hexagonal lattice.

19. A method according to claim 4, wherein the pattern of the major areas of the second layer is a series of long parallel strips with widths ranging from 0.5 to 10 microns, and wherein the distance between the strips is about 10 to about 90 microns.

20. A method according to claim 4, wherein the pattern of the minor areas of the second layer is a series of circular holes with a diameter ranging from about 0 to about 8 microns, arranged in a square lattice, and wherein the holes have spacing of about 2 to about 10 microns between the major areas.

21. A method according to claim 4, wherein the pattern of the minor areas of the second layer is a series of circular holes having diameters ranging from about 0 to about 8 microns arranged in a hexagonal lattice, and wherein the holes have spacing of about 2 to about 10 microns between the major areas.

22. A method according to claim 4, wherein depositing a nickel containing compound includes immersing the first amorphous silicon thin film layer into a solution containing the nickel containing compound.

23. A method according to claim 4, wherein depositing the nickel containing compound is performed by sputtering or evaporation coating of nickel in a vacuum.

24. A method according to claim 4, wherein depositing the nickel containing compound is performed by spin coating a nickel containing compound in air.

25. A method according to claim 4, wherein depositing the nickel containing compound is performed by ion implantation in a vacuum.

26. A method according to claim 4, wherein annealing is carried out in a nitrogen atmosphere.

27. A method according to claim 4, wherein annealing is carried out at a temperature between about 450° C. to about 650° C.

28. A thin film transistor device comprising one or more polycrystalline thin films made in according to the method of claim 4.

29. An active matrix display device including in the backplane thereof, an array of transistors made according to claim 6.