Aspects of the present disclosure are best understood from the following detailed description when read in association with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features in the drawings are not drawn to scale. In fact, the dimensions of illustrated features may be arbitrarily increased or decreased for clarity of discussion.
It is understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Design for manufacturability, or DFM, is an integration of manufacturing data and design procedure for better yield and design efficiency. An interaction and communication between designer and manufacturer is enhanced thereby for more accurate, faster, and more efficient design. In one example, various manufacturing data are formulated, quantified, and integrated to enable collaboration between manufacturer and designer, reduce design time and design cost, and increase manufacturing yield and production performance. DFM can be realized at various design stages with collaboration of design tool vendors. The manufacturer may be a semiconductor foundry. The designer may be an integrated circuit (IC) design house. The design tool vendor may be an electronic design automation (EDA) tool vendor. In some examples, a single company may include all three.
Referring to
In the CMP simulation 114, a CMP process is simulated to a design layout by utilizing DDK 110. The design layout is converted to a material thickness and thickness hotspots can be identified for further design tweaking and tuning. CAA simulation 116 utilizes DDK for critical area identification and design improvement. DFM data may be packed in a unified format, referred to as DFM unified format (DUF). DDK 110 can be provided to an IC design vendor and be integrated into a design tool, or directly distributed to a designer such as a fab-less design house and employed by the designer in a design tool.
DFM 100 also includes DFM advisories 120. The DFM advisories 120 are extracted from the manufacturing information and provided for an IC design tool and/or a designer. The DFM advisories 120 further include DFM rules that can be incorporated into a design tool for checking any violation. DFM rules such as action required rules 122 are binding, requiring further actions to eliminate the associated violation. Recommended rules 124 are not binding and suggested for design improvement. The DFM advisories also include guidelines 146, provided for the designer to follow in implementing an IC design procedure.
DFM 100 also includes DFM utilities 130, utilizing DDK 110 and DFM advisories 120 in IC design. DFM utilities 130 may be integrated into a design tool and incorporated into a design flow. For example, dummy insertion may be implemented at the place-and-route design stage so that dummy features are automatically generated in the IC layout to reduce CMP manufacturing variances. DFM utilities 130 may provide corrective actions and solutions to the designer to guide for design improvement and tuning. For example, DFM utilities 130 may provide a solution to eliminate identified hotspots from a lithography process simulation, such as reconfiguring metal lines to eliminate the hotspots. In one embodiment, DFM utilities 130 include a layout parasitic extraction (LPE) deck 132 for extracting more accurate parasitic parameters such as parasitic resistance and capacitance with the manufacturing data such as CMP data, and further for providing suggested actions to adjust parasitic parameters and timing. DFM utilities 130 may also include a checker 134 that is integrated with DFM rules, is able to automatically check the layout for any DFM rule violation, and/or provides suggestions to eliminate the violation. DFM utilities 130 may include an enhancer 136 that is capable of automatically adjusting the layout to meet the DFM rules or eliminate identified hotspots. DFM utilities 130 may further include a dummy insertion module 138 to incorporate dummies (e.g., non-conducting metal features) into a design layout to eliminate CMP process variation.
DFM 100 provides model-based utilities from various simulations and rule-based utilities from DFM advisories. DFM 100 can be implemented at various designing stages and certain manufacturing stages. For example, dummy insertion may be implemented at place-and-route step such that the dummy features are included in a layout at early design stage. LPE deck may be implemented at extraction and a timing simulation. LPC may be implemented before the tape-out. Alternatively, LPC may be implemented after the tape-out. In this situation, the layout can be adjusted to eliminate hotspots identified by LPC before fabricating a mask of the layout in a mask shop.
The method begins at step 210 by providing an IC design layout defined into a plurality of grids. The IC design layout may include physical design information in certain layer(s) and may come from a product specification through various design stages such as logic design, floor plan, and place and route. The design module for implementing the above logic and physical design processes may include an RTL/synthesis, and place & route.
Referring also to
The design method 200 (
Referring to
The metal thickness and dielectric thickness can be easily extracted from the metal height and dielectric height. For example, the metal thickness is Z1 and dielectric thickness is the difference between Z1 and Z2 for that grid. In one embodiment, the above simulation and extraction are based on one layer mode where only one structure layer, such as metal one layer, is considered for CMP simulation parameter extraction. The impacts of the underlying structure layers to the overlying layer in term of CMP process is neglected for simplicity.
In another embodiment, the simulation and extraction are based on a multilayer mode where only multiple structure layers are considered for CMP process and simulation since a stacking effect can substantially impact the CMP and final surface topography.
Referring to
Referring to
In one example, the ESL 614 is used as the generic reference. Therefore, the absolute height Z0 of the metal bottom 620 of the metal feature 618 is defined as a vertical distance from the ESL 614 to the metal bottom 620. Specifically in one example, the absolute height Z0 is defined as a vertical distance from the ESL bottom 622 to the metal bottom 620. When each metal bottom is used as a local reference for dielectric height Z1 and metal height Z2, its absolute vertical location is also defined as Z0 to the ESL 612 in the metal one layer. Thus the absolute dielectric height and metal height for each metal layer in each grid can be included in the CMP simulation. The stacking effect is therefore included in the multilayer CMP simulation mode. The parameters Z0, Z1, and Z2 are essential to for accurate three dimensional RC extraction.
The disclosed RC extraction method not only includes CMP simulation but also three dimensional RC extraction. The disclosed RC extraction method is capable for more accurately simulate CMP processes and estimate dielectric and metal parameter for multiple interconnect structure.
Referring again to
The IC design method 200 may further include other modules. For example, the IC design method 200 can include a timing analyzer for signal timing analysis based on the extracted parasitic capacitance and resistance.
The IC design method 200 may further include a front-end design step before the physical layout design, such as a register-transfer level (RTL) design. The design method 200 may also include floor planning and place-and-route. Standard cells, input/output (I/O) cells, and IP/Macro can be placed in various locations according to the functional connectivity and the optimization of signal routing.
The design method 200 may also include design rule check (DRC) and layout vs. schematic (LVS). DRC is performed on the physical layout to verify that the manufacturer concerned process requirements have been satisfied. LVS is performed such that the devices/interconnects are extracted to generate a netlist for comparison with an original design netlist. The design method 200 may also include other steps such as dummy insertion.
The design method 200 may include a tape-out step to form a final IC design presented as various photomask patterns. After the verifications of design functional specification, signal timing, device connectivity, and design rule of layout are accomplished, the layout will be taped out and be provided to a manufacturer, such as a semiconductor foundry for fabrication.
Referring now to
A computer system typically includes at least hardware capable of executing machine readable instructions, as well as the software for executing acts (typically machine-readable instructions) that produce a desired result. In addition, a computer system may include hybrids of hardware and software, as well as computer sub-systems.
Hardware generally includes at least processor-capable platforms, such as client-machines (also known as personal computers or servers), and hand-held processing devices (such as smart phones, personal digital assistants (PDAs), or personal computing devices (PCDs), for example). Further, hardware may include any physical device that is capable of storing machine-readable instructions, such as memory or other data storage devices. Other forms of hardware include hardware sub-systems, including transfer devices such as modems, modem cards, ports, and port cards, for example.
Software includes any machine code stored in any memory medium, such as RAM or ROM, and machine code stored on other devices (such as floppy disks, flash memory, or a CD ROM, for example). Software may include source or object code, for example. In addition, software encompasses any set of instructions capable of being executed in a client machine or server.
Combinations of software and hardware could also be used for providing enhanced functionality and performance for certain embodiments of the present disclosure. One example is to directly manufacture software functions into a silicon chip. Accordingly, it should be understood that combinations of hardware and software are also included within the definition of a computer system and are thus envisioned by the present disclosure as possible equivalent structures and equivalent methods.
Computer-readable mediums include passive data storage, such as a random access memory (RAM) as well as semi-permanent data storage such as a compact disk read only memory (CD-ROM). In addition, an embodiment of the present disclosure may be embodied in the RAM of a computer to transform a standard computer into a new specific computing machine.
Data structures are defined organizations of data that may enable an embodiment of the present disclosure. For example, a data structure may provide an organization of data, or an organization of executable code. Data signals could be carried across transmission mediums and store and transport various data structures, and, thus, may be used to transport an embodiment of the present disclosure.
The system may be designed to work on any specific architecture. For example, the system may be executed on a single computer, local area networks, client-server networks, wide area networks, internets, hand-held and other portable and wireless devices and networks.
A database may be any standard or proprietary database software, such as Oracle, Microsoft Access, SyBase, or DBase II, for example. The database may have fields, records, data, and other database elements that may be associated through database specific software. Additionally, data may be mapped. Mapping is the process of associating one data entry with another data entry. For example, the data contained in the location of a character file can be mapped to a field in a second table. The physical location of the database is not limiting, and the database may be distributed. For example, the database may exist remotely from the server, and run on a separate platform. Further, the database may be accessible across the Internet. Note that more than one database may be implemented.
Thus, the present disclosure provides an integrated circuit (IC) design method. The method includes providing a design layout defined in a plurality of grids; simulating a chemical mechanical polishing (CMP) process to an IC substrate with a patterned structure defined by the design layout, generating a dielectric thickness and a metal thickness on one of the plurality of grids; extracting a capacitance based on the dielectric thickness on the one of the plurality of grids; and extracting a resistance based on the metal thickness on the one of the plurality of grids.
In the disclosed IC design method, the providing of the design layout may include partitioning the design layout into the plurality of grids. The providing of the design layout may include forming a logic design; and forming the design layout based on the logic design. The simulating of the CMP process may include simulating the CMP process in single layer mode. The simulating of the CMP process may include simulating the CMP process in multilayer mode. The simulating of the CMP process in multilayer mode may include incorporating a stacking effect. The simulating of the CMP process may include utilizing data selected from the group consisting of CMP processing recipes, CMP tool characterization, manufacturing environment, production and processing statistical information, and combinations thereof. The simulating of the CMP process may include defining a dielectric surface height and a metal surface height relative to a trench bottom on the one of the plurality of grids. The generating of the dielectric thickness and the metal thickness may include utilizing the dielectric surface height and the metal surface height. The simulating of the CMP process may include defining a height of the trench bottom relative to an absolute reference. The absolute reference may be defined as an etch stop layer disposed in a first metal structure. The generating of the dielectric thickness and the metal thickness may include utilizing the dielectric surface height, the metal surface height, and the height of the trench bottom in a multilayer mode.
The present disclosure also provides another embodiment of an integrated circuit (IC) design method. The method includes generating a design layout; defining the design layout into a plurality of grids; simulating a chemical mechanical polishing (CMP) process to an IC substrate with a patterned structure defined by the design layout; extracting a dielectric thickness and a metal thickness on one of the plurality of grids based on the simulating of the CMP process; extracting a capacitance based on the dielectric thickness on the one of the plurality of grids; and extracting a resistance based on the metal thickness on the one of the plurality of grids.
In this disclosed method, the extracting of the dielectric thickness and metal thickness may include utilizing a single layer mode or a multilayer mode. The IC design method may further include a timing analysis after the extracting of the capacitance and the extracting of the resistance.
The present disclosure also includes an IC design system. The IC design system includes a design module being capable of providing a design layout; and a resistance and capacitance (RC) extractor. The RC extractor is designed for defining the design layout into a plurality of grids; simulating a chemical mechanical polishing (CMP) process; generating a metal thickness and a dielectric thickness on each of the plurality of grids corresponding to the design layout; and extracting a resistance and a capacitance on the each of the plurality of grids.
The disclosed IC design system may further include a timing analyzer for performing timing analysis to the design layout based on the resistance and capacitance extracted by the RC extractor. The IC design system may further include at least one of CMP layout guidelines and suggested structures for fixing CMP hotspots. The IC design system may further include a design-for-manufacturing (DFM) data kit having various CMP processing data. The various CMP processing data may include those selected from the group consisting of CMP processing recipes, CMP tool characterization, manufacturing environment, production and processing statistical information, and combinations thereof.
The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the detailed description that follows. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments disclosed herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.
This application claims the benefit of U.S. Provisional Application 60/800,526 entitled “Design for Manufacturability,” filed May 15, 2006, incorporated herein by reference in its entirety. The present disclosure is related to the following commonly-assigned U.S. patent applications, the entire disclosures of which are hereby incorporated herein by reference: U.S. patent application by inventors Gwan Sin Chang, Yi-Kan Cheng, Ivy Chiu, and Ke-Ying Su for “IC DESIGN FLOW ENHANCEMENT WITH CMP SIMULATION” (attorney reference TSMC2006-0378).
Number | Date | Country | |
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60800526 | May 2006 | US |