Claims
- 1. A metal-to-metal antifuse structure located on a semiconductor device comprising.
- a. an antifuse stack located on said semiconductor device comprising:
- i. a bottom plate comprising conductive material adjacent said semiconductor device;
- ii. an antifuse dielectric comprising amorphous silicon located on said bottom plate; and
- iii. an etchstop layer located above said antifuse dielectric;
- b. an interlevel dielectric located above said semiconductor device and said antifuse stack;
- c. at least one via extending through said interlevel dielectric and said etchstop layer to said antifuse dielectric; and
- d. a top plate comprising conductive material and located adjacent said antifuse dielectric in said at least one via, wherein an electrical size of said metal-to-metal antifuse structure is determined by said top plate.
- 2. The structure of claim 1 wherein said bottom plate and said top plate comprise TiW.
- 3. The structure of claim 1 wherein said bottom plate and said top plate comprise TiN.
- 4. The structure of claim 1 wherein said etchstop layer comprises aluminum.
- 5. The structure of claim 1 wherein said etchstop layer comprises aluminum-oxide.
- 6. The structure of claim 1 wherein said etchstop layer comprises a layer of oxide adjacent said dielectric layer and a layer of amorphous silicon overlying said oxide layer.
- 7. The structure of claim 1 wherein said bottom plate and said top plate comprise titanium.
Parent Case Info
This is a division of application Ser. No. 08/079,194, filed Jun. 17, 1993, now U.S. Pat. No. 5,300,456.
US Referenced Citations (3)
Divisions (1)
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Number |
Date |
Country |
Parent |
79194 |
Jun 1993 |
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