Patent Application
20060231732
The invention relates generally to semiconductor imaging devices, and more particularly to reducing the noticeability of fixed pattern noise in a solid state imager.
There is a current interest in CMOS active pixel imagers for use as low cost imaging devices. Active pixel sensors can have one or more active transistors within the pixel unit cell, can be made compatible with CMOS technologies, and promise higher readout rates compared to passive pixel sensors.
Signals stored in the readout circuit 242 can be read out sequentially column-by-column to an output stage 354, which is common to the entire array of pixels 330. Output stage 359 provides two output signals Vout1, Vout2 that correspond to the Vsig, Vrst signals, respectively. The analog output signals Vout1, Vout2 can then be sent, for example, to a differential analog circuit, which subtracts the reset and integrated charge signals and sends the subtracted signal to an analog-to-digital converter (ADC); alternatively, the reset and integrated charge signals can be supplied directly to the analog-to-digital converter.
During manufacture, each imaging pixel array is usually tested individually. Tests detect defective pixel circuits, pixel signal level, and other array attributes, and the information is stored based on lot and individual device identification numbers. The information developed during testing can be utilized to enhance the operation of the device by, for example, compensating for defective pixels, differing pixel signal levels, and other tested pixel attributes.
Because variances occur during manufacturing, the capacitance values of capacitors c_rst and c_sig will be different, ideally only slightly different. However, it is not easy or cheap to test the capacitance value of each capacitor c_rst, c_sig and then modify the capacitors to have the same capacitance value. Thus, capacitors c_rst and c_sig of each sample and hold circuit 351 will add a different amount of column-wise fixed pattern noise to the readout process.
Similarly, the bias current Iln will vary from column to column. Although the difference may not be large, nonetheless, the different Iln current values will add different amounts of gain during read out of each sample and hold circuit 351. Thus, the bias current Iln of each sample and hold circuit 351 will add a different amount of column-wise fixed pattern noise to the relevant process.
The human eye is sensitive to column-wise noise, which may manifest as a column in an image being different from surrounding columns of the image. Therefore, it is desirable to modify the imager to reduce the visual obviousness of column-wise fixed pattern noise
An imager is provided in an exemplary embodiment that reduces the visual obviousness of column-wise fixed pattern noise by randomly mixing and applying fixed pattern noise to different columns in the imager's array. In an exemplary embodiment of the invention, signals from the columns of the pixel array are read out to varying sample and hold circuits selected at random. In addition, pixel columns are randomly matched to sample and hold circuits.
These and other features and advantages of the invention will be more readily understood from the following detailed description of the invention which is provided in connection with the accompanying drawings, in which:
In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific exemplary embodiments of the invention. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to make and use the invention, and it is to be understood that structural, logical or other changes may be made to the specific embodiments disclosed without departing from the spirit and scope of the present invention.
The illustrated system 400 includes pixel array 230 connected to the readout circuit 442. Readout circuit 442 includes a first switching circuit 441, second switching circuit 443, and a controller 450 for controlling the switching circuits 441, 443. The readout circuit 442 is different from the conventional readout circuit 242 (
Each pixel column 349a-d is coupled to the first switching circuit 441. The switch setting of the first switching circuit 441 determines which pixel column 349a-d is selectively coupled to which sample and hold circuit 351a-d. For example,
The controller 450 provides signals to the first switching circuit 441 indicating which pixel column 349a-d is to be coupled to which sample and hold circuit 351a-d. In a preferred embodiment, the controller's 450 matching of pixel columns 349a-d and sample and hold circuits 351a-d is done on a random basis. Although described with respect to a random assignment, the invention is not so limited. For example, the matching may occur in pseudo-random, or any other varying matching fashion.
In an exemplary embodiment, the controller 450 re-matches, i.e., generates new matches between, pixel columns 349a-d and sample and hold circuits 351a-d before each read out from a row in the pixel array 230. For example, the controller 450 determines a match and then the selected row is readout, then the controller 450 determines a match and the next row is readout. In another aspect, the controller 450 re-matches periodically; that is to say that the time interval between the controller establishing another set of matches is a set time interval. The controller 450 establishes the time interval before reading out from the image array. For example, if the time interval is five, then the controller 450 rematches before each fifth read out from a row in the pixel array 230. In yet another aspect, the controller 450 re-matches at various time intervals, where the time intervals are generated on a varying fashion, ideally in a random fashion. For example, if the time interval to re-match is random, then the controller 450 re-matches before the first, fifth, and thirteenth read outs from rows in the pixel array 230. Although this invention is described with reference to a conventional readout from an array (e.g., sequentially reading a row from the first column on the left to the last column on the right and then repeating for the next row), the invention is not so limited. For example, the imager may be readout in an interleaved fashion. Additionally, there are times when not all of the rows or columns are read out, e.g., when varying the resolution of the imager.
The output of each sample and hold circuit 351a-d is coupled to the second switching circuit 443. The selection of the second switching circuit 443 determines which sample and hold circuit 351a-d is coupled to the output stage 354. The controller 450 provides signals to the second switching circuit 443 indicating which sample and hold circuit 351a-d is to be coupled to the output stage 354. The controller 450 provides a signal to the second switching circuit 443 before the read out of a sample and hold circuit 351a-d.
In a preferred embodiment, the controller's 450 matching of sample and hold circuits 351a-d to output stage 354 is performed based on the current matching of pixel columns 349a-d to sample and hold circuits 351a-d by the controller 450. For example, in conventional systems where a row is read out sequentially, left to right, and the controller matched the first pixel column 349a with the second sample and hold circuit 351b, the second pixel column 349b with the third sample and hold circuit 351c, the third pixel column 349c with the fourth sample and hold circuit 351d, and the fourth pixel column 349d with the first sample and hold circuit 351a, then the first sample and hold circuit to be readout to the output stage 354, is the second sample and hold circuit 351b. Therefore, the controller 450 provides an appropriate signal to the second switching circuit 443 to couple the second sample and hold circuit 351b to the output stage 354. For the next read out, the controller 450 provides an appropriate signal to the second switching circuit 443, to couple the third sample and hold circuit 351c to the output stage 354. For the next read out, the controller 450 provides an appropriate signal to the second switching circuit 443 to couple the fourth sample and hold circuit 351d to the output stage 354. For the next read out, the controller 450 provides an appropriate signal to the second switching circuit 443 to couple the first sample and hold circuit 351a to the output stage 354. In an alternative embodiment, the controller 450 provides a signal to a separate processing circuit (not shown) indicating the match for each row and the sample and hold circuits 351a-d will be read out sequentially left to right (i.e. circuits 351a to 351d). The separate processing circuit coordinates re-ordering the signals from each column such that they are representative of the order in which they originate in the image array. In this aspect of the invention, a second switching circuit 442 is not required as the sample and hold circuits 351a-d are coupled directly to the output stage 354.
Signals stored in the readout circuits 442 can then be read sequentially column-by-column to the output stage 354, which is common to the entire array of pixels 230. The analog output signals can then be sent, for example, to a differential analog circuit, which subtracts the reset and integrated charge signals and sends the subtracted signal to an analog-to-digital converter (ADC); alternatively, the reset and integrated charge signals can be supplied directly to the analog-to-digital converter.
Therefore, an imager is provided that reduces the visual obviousness of column-wise fixed pattern noise by randomly mixing and applying fixed pattern noise to different columns of the array. Fixed pattern noise is not necessarily reduced, however, fixed pattern noise from a sample and hold circuit is not always associated with a single pixel column but is instead associated with different pixels. As the noise is applied to different columns, the human eye is less likely to notice the noise.
System 1100, for example a camera system, generally comprises a central processing unit (CPU) 1110, such as a microprocessor, that communicates with an input/output (I/O) device 1150 over a bus 1170. Imaging device 400 also communicates with the CPU 1110 over the bus 1170. The system 1100 also includes random access memory (RAM) 1160, and can include removable memory 1130, such as flash memory, which also communicate with the CPU 1110 over the bus 1170. The imaging device 400 may be combined with a processor, such as a CPU, digital signal processor, or microprocessor, with or without memory storage on a single integrated circuit or on a different chip than the processor.
It should be appreciated that other embodiments of the invention include a method of manufacturing the circuit 1100. For example, in one exemplary embodiment, a method of manufacturing an CMOS readout circuit includes the steps of providing, over a portion of a substrate corresponding to a single integrated circuit, at least a pixel array and readout circuit of FIGS. 3 an 4 as described above using known semiconductor fabrication techniques. The method of manufacturing the readout circuit includes forming a plurality of sample and hold circuits over said substrate; and forming a switching circuit over said substrate for switchingly coupling one of said plurality of columns of pixels in said pixel array to one of said sample and hold circuits. The method of manufacturing may further include forming a control circuit over said substrate; and forming an electrical pathway for coupling said control circuit to said switching circuit. Additionally, the method of manufacturing may include the step of forming a second switching circuit over said substrate for switchingly coupling one of said sample and hold circuits to said downstream circuit.
While the invention has been described and illustrated with reference to specific exemplary embodiments, it should be understood that many modifications and substitutions can be made without departing from the spirit and scope of the invention. For example, although the invention is shown with respect to two switching circuits and the associated controller the invention is not meant to be so limiting. The controller functionality can be incorporated into the a controlling circuit already included in conventional system. Accordingly, the invention is not to be considered as limited by the foregoing description but is only limited by the scope of the claims.
