Claims
- 1. A method for calibrating an analog-to-digital converter (ADC) comprising the steps of:
- exciting a plurality of inputs of a digital-to-analog converter (DAC) from an excitation means generating known digital excitation signals, each said excitation signal being applied at a single digital bit input of the DAC and each said excitation signal being binary and orthogonal with respect to all other ones of said plurality of excitation signals, the sum of said excitation signals constituting a maximum entropy sequence of substantially uniform amplitude probability, said DAC producing an analog output signal, the transfer function of said DAC having been characterized by premeasured bit weighting values;
- providing said analog output signal of the DAC to an analog input of the analog-to-digital converter (ADC) under test, said ADC producing digital output signals;
- transforming said digital output signals from time domain digital signals into binary transform domain digital signals to obtain an output response weighting coefficient for each bit of the converter under test; and
- correcting each said output response weighting coefficient for bias errors induced by said DAC by adding to each output response weighting coefficient the corresponding difference between the ideal binary weights and said premeasured bit weighting values in a bias correction means in order to obtain unbiased weighting values of each bit specifying the transfer characteristic of the ADC under test.
- 2. The method according to claim 1 wherein the digital excitation signals are Walsh function signals.
- 3. The method according to claim 2 wherein the transforming step comprises transforming time domain digital signals into corresponding Walsh transform domain signals.
- 4. The method according to claim 3 wherein said digital excitation signals comprise together a digital representation of a linear amplitude ramp.
- 5. The method according to claim 1 wherein the unbiased weighting coefficient of the m.sup.th bit of analog-to-digital converter under test is represented by:
- a.sub.m =a.sub.m +c.sub.m
- where
- a.sub.m is the output response weighting coefficient of the m.sup.th bit; and
- c.sub.m is a coefficient based on the ideal output of said digital-to-analog converter and the corresponding premeasured weighting value of the digital-to-analog converter.
- 6. An apparatus for calibrating an analog-to-digital converter (ADC) comprising:
- means for exciting inputs of a digital-to-analog converter (DAC) from an excitation means operative to generate known digital excitation signals at selected digital excitation signal outputs, each said excitation signal output being adapted to be coupled to a single digital bit input of the DAC under test and each said excitation signal constituting a maximum entropy sequence of substantially uniform amplitude probability, said DAC producing an analog output signal at an analog output signal terminal, the transfer function of said DAC having been characterized by premeasured weighting values of a set of binary orthogonal functions;
- the ADC under test adapted to be coupled to said DAC analog output signal terminal, said ADC under test being operative to produce digital output signals in response to said analog output signal;
- means for transforming said digital output signals from time domain digital signals into binary transform domain digital signals to obtain an output response weighting coefficient for each bit of the converter under test; and
- means for correcting each said output response weighting coefficient for bias errors induced by said DAC by adding to each output response weighting coefficient the corresponding difference between the ideal binary weights and said premeasured weighting values in order to obtain unbiased weighting values of each bit specifying the transfer characteristic of the analog-to-digital converter under test.
- 7. The apparatus according to claim 6 wherein said exciting means is a Walsh function signal generator.
- 8. The apparatus according to claim 7 wherein the transforming means comprises means for transforming time domain digital signals into corresponding Walsh transform domain signals.
- 9. The apparatus according to claim 8 wherein said digital excitation signals comprise together a digital representation of a linear amplitude ramp.
- 10. The apparatus according to claim 6 wherein said unbiased weighting coefficient of the m.sup.th bit of a digital-to-analog converter under test is represented by:
- a.sub.m =a.sub.m c.sub.m
- where
- a.sub.m is the output response weighting coefficient of the m.sup.th bit; and
- c.sub.m is a coefficient based on the ideal output of said digital-to-analog converter and the corresponding premeasured weighting value of the digital-to-analog converter.
Parent Case Info
This application is a continuation-in-part of copending patent application Ser. No. 364,374 filed Apr. 1, 1982 now U.S. Pat. No. 4,465,995.
US Referenced Citations (2)
Number |
Name |
Date |
Kind |
4340856 |
Orlandi |
Jul 1982 |
|
4465995 |
Sloane |
Aug 1984 |
|
Non-Patent Literature Citations (2)
Entry |
L. F. Pau, "Fast Testing and Trimming of A/D and D/A Converters in Automatic Test Systems", Published in the Proceedings of Autotestcon 1978 IEEE Catalog 78CH1416-7, Nov. 1978, pp. 268-274. |
Sellier, "IBM Technical Disclosure Bulletin", vol. 22, No. 3, Aug. 1979, pp. 1039-1040. |
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
364374 |
Apr 1982 |
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