The technical field is mechanisms and methods for communications between processors in a multi-processor computer system.
Advanced computer architectures may employ multiple processors. Some advanced computer architectures may employ multiple microprocessors on one silicon chip. In a typical application, two microprocessors may be implemented on a single silicon chip, and the implementation may be referred to as a dual core processor. Two or more of the multiple microprocessors may operate in a lock step mode, meaning that each of the lock stepped microprocessors process the same code sequences, and should, therefore, produce identical outputs.
An apparatus, and a corresponding method, for communicating between lock step processors is disclosed. The apparatus is incorporated on two or more processors operating in a lock step mode. Each of the processors comprise processor logic to execute a code sequence, wherein an identical code sequence is executed by the processor logic of each of the two or more processors. The apparatus further comprises a lock step logic block including a processor-specific resource referenced by the code sequence, the processor-specific recourse comprising a unique processor core identification, and a multiplexer coupled to the processor-specific resource, wherein the multiplexer is controlled to read data based on the identification. Coupled to the processors is a lock step logic block operable to read and compare the output of each of the processors. The lock step logic determines if operation of the processors is in a lock step mode or in an independent processor mode. Such determination may be made by the lock step logic turning off, for example.
The corresponding method for communicating between two or more lock step processors comprises receiving a read instruction, determining a processor address associated with the read instruction, determining one or more bits associated with the processor address, comparing the one or more bits to the processor address to determine a location from which the read instruction is executed, and reading data from the determined location.
The detailed description will refer to the following figures, in which like numbers refer to like elements, and in which:
An apparatus, and a corresponding method, for communicating between processors in a multi-processor computer system are disclosed. The apparatus and method may advantageously be applied to a computer system employing lock step processors. Lock step processors, by definition, run identical code streams, and produce identical outputs.
The bus 126 interfaces with the lock step logic block 130 through interface 124. The lock step logic block 130 performs various checks to ensure the processors 110 and 120 operate in lock step, when lock step operation is the desired mode of operation. Also coupled to the processors 110 and 120 is cross bar switch 140, which maps arbitrary input ports to any arbitrary output port.
The arrangement of components shown in
The processors 110 and 120 may, on occasion, need to communicate directly. However, conventional communication means (e.g., using load and store instructions) will cause a loss of lock step operation.
To allow processor-to-processor communication, and not cause loss of lock step, communication means may be added to the system 100 shown in
In
More specifically, should the multiplexer 132 and the multiplexer 136 receive the “0,” then the processor 110 will receive (read) data from the MSR (600) 134, and the processor 120 will read data from the MSR (600) 138. If the multiplexers 132 and 138 receive the “1,” then the processor 110 will read data from the MSR 138 and the processor 120 will read data from the MSR 134. Thus, by controlling the multiplexers 132 and 136, communications between the processors 110 and 120 is possible without loss of lock step.
Because only one bit is used, the technique can be used on an arbitrary number of register pairs, and can be extended to more than two processors, by using a greater number of low-order bits in the address of the MSR. Thus, in operation, both the processor 110 and the processor 120 can write values out, and both processors 110 and 120 can read what the other processor wrote.
In the embodiment shown in
The terms and descriptions used herein are set forth by way of illustration only and are not meant as limitations. Those skilled in the art will recognize that many variations are possible within the spirit and scope of the invention as defined in the following claims, and there equivalents, in which all terms are to be understood in their broadest possible sense unless otherwise indicated.
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