Patent Application
20140270004
The present disclosure relates to wireless communication systems, and more particularly, some embodiments relate to methods and systems for compensating for frequency errors between a base station and a mobile station.
Cellular communication systems transmit at radio frequencies (RF) that are typically several orders of magnitude higher than the bandwidth of the cellular signal. Additionally, baseband systems for cellular mobile stations and base stations must use a frequency reference in order to generate a modulated baseband signal. Therefore, radio receivers, transmitters, and basebands are implemented using tuned oscillators. In a typical cellular system, on the downlink, tuned oscillators in the base station are used to create a signal and convert it to RF (using a mixer) in the transmitter. A mobile station receives the RF signal, converts it to baseband, and demodulates it using tuned oscillators. A similar approach is followed on the uplink, using tuned oscillators with the roles of base station and mobile station reversed.
The tuned oscillators at the base station and mobile station will each have a frequency error which can cause issues in the cellular system. First, the frequency error between base station and mobile station can either prevent synchronization between them or cause the synchronization to take a long time. Second, the frequency error can cause the demodulation of the cellular signal to fail. One additional problem associated with the frequency error is that it varies with environmental conditions, in particular temperature. Thus, even if the frequency error is small at one point in time, later when the temperature changes the error may also change, causing synchronization and demodulation issues.
In some embodiments of the present disclosure, an apparatus includes a reference oscillator and first and second fractional-N phase lock loop (PLL) frequency synthesizers. The reference oscillator is configured to provide a reference oscillation signal. The first PLL frequency synthesizer is configured to receive the reference oscillation signal as an input, output a baseband oscillation signal, and lock a frequency divided version of the baseband oscillation signal to a frequency divided version of the reference oscillation signal. The second PLL frequency synthesizer is configured to receive the reference oscillation signal as an input, output a first radio frequency (RF) oscillation signal, and lock a frequency divided version of the first RF oscillation signal to the frequency divided version of the reference oscillation signal. The first and second PLL frequency synthesizers have respective inputs for receiving a frequency adjustment signal. The first and second PLL frequency synthesizers are each further configured to compensate a frequency error of the corresponding output oscillation signal based on the frequency adjustment signal.
In some embodiments, a method includes generating a fixed reference oscillation signal at a first oscillator. At a second oscillator, a baseband oscillation signal is generated. A frequency divided version of the baseband oscillation signal is locked to a frequency divided version of the first reference oscillation signal. At a third oscillator, a first radio frequency (RF) oscillation signal is generated. A frequency divided version of the first RF oscillation signal is locked to the frequency divided version of the second reference oscillation signal. A frequency adjustment signal is provided as an input to the second and third oscillators. At the second oscillator, a frequency error of the baseband oscillation signal is compensated based on the frequency adjustment signal. At the third oscillator, a frequency error of the first RF oscillation signal is compensated based on the frequency adjustment signal.
In some embodiments, a method includes at a mobile station receiving a pilot signal from a base station. At the mobile station, a local version of the pilot signal is generated. At a physical layer processing module of the mobile station, a frequency error is measured between the received pilot signal and the local version of the pilot signal. A determination is made as to whether the measured frequency error exceeds a predetermined threshold. If the measured frequency error exceeds the predetermined threshold, a new divide term is computed based on the measured frequency error and a divider of a fractional-N phase lock loop (PLL) circuit is set to divide in frequency an output signal of said PLL circuit by the computed new divide term.
In some embodiments, a method includes retrieving, from a memory of the mobile station, a stored temperature of an oscillator of the mobile station. The stored temperature corresponds to a first time. A temperature differential at the oscillator, between the first time and a second time, is computed. A frequency differential for the oscillator is estimated based on the computed temperature differential. An initial divide term is computed based on the computed frequency differential. A fractional-N phase lock loop (PLL) circuit is operated. The PLL circuit has a reference signal as an input. An oscillator signal at an output of the PLL circuit is divided in frequency, at a divider of the PLL circuit, by the computed initial divide term.
In some embodiments, a method includes retrieving, from a memory of the mobile station, a stored time value, wherein the stored time value is a first time value corresponding to a previous wake-up event of the mobile station, and wherein a power-down event occurred between said previous wake-up event and said retrieving. A time differential is computed between the stored time value and a second time value, wherein the second time value is a time of a wake-up event immediately following said previous wake-up event. A frequency differential is estimated for said oscillator based on the computed time differential. An initial divide term is computed based on the computed frequency differential. A fractional-N phase lock loop (PLL) circuit is operated. The PLL circuit has a reference signal as an input. An oscillator signal at an output of the PLL circuit is divided in frequency, at a divider of said PLL circuit, by the computed initial divide term.
The following will be apparent from elements of the figures, which are provided for illustrative purposes and are not necessarily to scale.
This description of the exemplary embodiments is intended to be read in connection with the accompanying drawings, which are to be considered part of the entire written description. Terms concerning attachments, coupling and the like, such as “connected” and “interconnected,” refer to a relationship wherein structures are secured or attached to one another either directly or indirectly through intervening structures, as well as both movable or rigid attachments or relationships, unless expressly described otherwise. Likewise, terms concerning electrical coupling and the like, such as “coupled,” “connected” and “interconnected,” refer to a relationship wherein structures communicate with one another either directly or indirectly through intervening structures unless expressly described otherwise.
Various embodiments of the present disclosure provide a cost-effective solution to the above-described frequency offset (mismatch) problem in cellular mobile stations, so that frequency error is reduced to allow accurate reception and transmission. Also, various embodiments compensate for temperature variations in the frequency error at the cellular mobile station.
The baseband oscillator 110, receiver oscillator 112, and transmitter oscillator 114 of the mobile station are each implemented with fractional-N phase lock loops (PLL) frequency synthesizers that derive their respective output signals 120, 122, 124 from the fixed reference signal 105. The fractional-N architecture provides fast lock times and allows the output frequency of the respective PLLs to be adjusted in very small steps, e.g. 10-100 Hz. Unlike prior art techniques, additional circuitry and complexity is not needed in order to implement frequency tuning. A frequency adjustment signal (which may be a multi-bit signal) for reducing the frequency error is applied directly to the PLL circuits 110, 112, 114 that generate the tuned oscillator signals 120, 122, 124. Thus, unlike the prior art, the reference signal is fixed and the error in the tuned oscillator signals is reduced within the PLL circuits. This is possible due to the small frequency adjustment capability of the fractional-N synthesizers.
In some embodiments, external reference signals are derived from the baseband PLL in order to support other systems, e.g. Bluetooth, WiFi, GPS, and the like, as shown by modules 131 and 133 that include dividers 130, 132 and buffers 140, 142 as shown in
Adjustment of reference tuning to compensate for temperature variation is not necessary during normal operation where the AFC algorithm is used to adjust the frequency. However, in certain cases where the mobile station is turned off at one temperature and then is turned back on at a different temperature, the frequency reference will move and synchronization with the base station will take longer. Circuitry of oscillators 102, 1120, 112, and 114 are formed in a common semiconductor substrate which may be a silicon-based substrate. Since the temperature of this overall integrated circuit is known by conventional techniques, no additional circuits are required to either measure or compensate for any temperature drift in the reference.
A voltage controlled oscillator (VCO) 340 generates the output signal 342 for a desired channel (e.g., a signal at a desired channel frequency). A divider 350 (here shown as divide by N) is used to divide the frequency of the output signal 342 of the VCO by N, to a lower frequency where it can be phase locked to a reference. The divide term (sometimes called divide ratio) N can be either an integer or a fraction, depending on the implementation. Because the divide term N can be a fraction, the output frequency (frequency of signal 342) is adjustable in small steps (fine resolution).
The phase detector output 322 is filtered by a loop filter 330 (e.g., low-pass filter) to provide a smoothed average of the phase difference between the signals 312, 352. This smoothed output is used to adjust the frequency of oscillation of the VCO 340. Consequently, the VCO 340 is adjusted until the phase and frequency of signals 312 and 352 match. Since the divide term N may be fractional, the VCO output signal 342 can be adjusted in frequency steps limited only by the size of the fractional part of the division. The divide ratio N may be modified, as discussed further below, in order to tune the VCO to the correct frequency. Each synthesizer 110, 112, 114 may be operating at a different output frequency and thus may have a different value of N that is updated independently from the other synthesizers.
In some embodiments, synthesizer 300 also includes a charge pump (not shown), e.g., coupled between the phase detector 320 and the loop filter 330. The charge pump, which is optional, converts the voltage output of the phase detector and to current pulses.
In some embodiments, the baseband PLL 110 is tuned to match the cellular base station frequency using an automatic frequency correction (AFC) process as discussed below, and thus is more accurate than the fixed reference frequency signal 105.
For track mode AFC (
Assuming the FRO 102 is operating at 1.664 GHz and the frequency of the channel that is desired to be received is 2.1 GHz (i.e., receive channel frequency=2.1 GHz), then we can estimate that the fractional divide term N (amount divider 350 divides in frequency) as 2.1 GHz/26 MHz=80.769230769230769230769230769231 . . . . . Because the actual physical implementation is limited in the divide terms that can be achieved, the size of the fractional part of the divider is reduced. The number of decimal places to which the estimated fractional divide term N is rounded is determined by a predetermined limit on step size between frequency errors corresponding to adjacent divide terms (where “adjacent” is meant in the sense of a pair of divide terms that are each written out to the relevant number of decimal places and which only differ in the least significant digit position). For example, to achieve a frequency error step size of no more than 10 Hz between adjacent divide terms, the estimated divide ratio N may be rounded to seven decimal places. The nominal divide term is 80.7692308 and the adjacent divide terms are 80.7692307 and 80.7692309 (thus these three adjacent differ only in their least significant digits which are “7”, “8” and “9”, respectively). These divide terms yield frequency errors as follows:
Frequency error 1=26 MHz*80.7692307−2.1 GHz=−1.8 Hz
Frequency error 2=26 MHz*80.7692308−2.1 GHz=+0.8 Hz
Frequency error 3=26 MHz*80.7692309−2.1 GHz=+3.4 Hz
A frequency difference of 2.6 Hz is present between each of those adjacent frequency errors, which meets the desired limit of no more than 10 Hz.
In some embodiments, frequency error is measured (block 430) by digital baseband module 108, based on receiving a pilot or reference signal from the base station and comparing that to a version of the pilot that is locally generated at the mobile station, as shown by blocks 410 and 420 of
In tracking mode, if the starting (initial) divide term is 80.7692308 and the frequency error of +140 Hz is measured, and if the measured frequency error (block 430) exceeds a predetermined threshold (block 440) (e.g., the threshold may be 20 Hz), then the new divide term is calculated as Nnew=round ([2.1 GHz-140 Hz]/[2.1 GHz/Nold], 7 decimal places)=80.7692254. This computation is understood as follows. The divide term N is the ratio of the channel frequency (i.e., frequency of output of VCO 340) to the frequency at the input of phase detector 320. The numerator in that ratio is computed as the channel frequency minus the error, hence 2.1 GHz-140 Hz, and the denominator in that ratio is computed as the channel frequency divided by the previous (previous in the sense of time) divide term, hence 2.1 GHz/Nold.
Thus, a new RF frequency of 26 MHz*80.7692254=2.0999998604 GHz is computed, which is −139.6 Hz below 2.1 GHz.
As shown in
This AFC process will work whether the phase detector frequency is 26 MHz exactly or not (in fact, it is unlikely to be exactly 26 MHz). Since the new divide ratio is calculated based on the old divide ratio and not an assumed phase detector frequency, the actual frequency value is not important. In this way, new divide ratios can be continuously calculated and any drift in the frequency offset can be tracked out.
The AFC process shown in
FRO frequency change slope=[(166.4 kHz−166.4 kHz)/(100° C.−40° C.)]=2377.1429 Hz/° C.
FRO frequency change offset=166.4 kHz−slope*100=−71314 Hz (i.e., this is the frequency at 0° C.).
FRO frequency change estimate=(temperature in ° C.)*2377.1429−71314 Hz (i.e., frequency as a linear function of temperature).
If the cellular system requires a frequency offset error in the FRO of less than 10 kHz (as one example; any predetermined threshold can be used) in order to perform initial synchronization, then a temperature shift of more the [10 kHz/(2377.1429 Hz/° C.)]=4.2° C. will cause a frequency shift which is beyond that threshold. Therefore, a delta temperature threshold (threshold for temperature differential) may be set to ±4.2° C. To continue this example, suppose a temperature measurement (block 504) reveals that the temperature shifted from +30° C. to +40° C. since the last (previous) wakeup (i.e., a power-off event occurred between the previous measurement of +30° C. and the present measurement of +40° C.). Since the temperature shift (differential) is determined to be greater (in magnitude) than the predetermined threshold (in this case, 4.2° C.) (block 506), the FRO frequency is computed based on known characteristics (the parameters stored in the memory 109, in this case the parameters regarding slope and intercept for the linear equation relating frequency as a function of temperature) as:
FRO frequency shift estimate=[40*2377.1429−71314 Hz]−[30*2377.1429−71314 Hz]=23771 Hz=fdelta
Next, the starting divide ratio is computed (block 512) based on the estimated frequency shift. The stored information for the last (previous in time, when temperature was +30° C.) channel and divide ratio N are retrieved from memory in order to compute the target for a new channel at the new temperature. Specifically, the starting divide ratio may be computed as:
N
new=round(fchannelnew/[fchannelold/Nold+fdelta/P],7 decimal places)
The motivation for the above equation is understood as follows. The divide ratio N is the ratio between the channel frequency and the divided reference frequency. In this case, the numerator of that ratio is the new channel frequency (i.e., fchannelnew) and the denominator can be expressed as the sum of the old divided reference frequency (which can be written as fchannelold/Nold because the two inputs to phase detector 320 have the same frequency due to lock) and a term fdelta/P accounting for the divided frequency shift.
As a specific example, assume that the last channel used was 2 GHz and the divide ratio N was 76.9230769. If the new channel is 2.1 GHz, then the starting divide term may be computed as:
N
new=round(2.1 GHz/[2 GHz/76.9230769+23771 Hz/64],7 decimal places)=80.7680769
The synthesizer (any of synthesizers 110, 112, 114) is tuned (block 516) using this computed divide term, i.e., the synthesizer is operated with this value of N (i.e., 80.7680769) until phase lock is achieved. An attempt to synchronize the mobile station to the base station is initiated (block 518). If the synchronization attempt succeeds, then the process ends; otherwise, a new fractional divide term is computed using a frequency offset as described below. In general, a search may be performed using the starting divide term as a starting point. The search corresponds to trying various frequency offsets iteratively (one after the other) until a terminating condition is achieved (such as successful synchronization or end of iteration range). Consider a typical range and step size over which to search in order to account for differences in base station frequency and errors in estimation. If, as indicated above, a FRO frequency error of less than 10 kHz is needed for synchronization, then for this example a frequency offset step of 5 kHz may be used for the search. A frequency offset step that is too coarse may result in failed operation for the following reasoning. Suppose a 25 kHz step were used, and suppose the frequency error (due to FRO frequency that shifted) is 38 kHz. If tested with offset steps of 0 kHz, −25 kHz, +25 kHz, −50 kHz, +50 kHz, the actual error would be 38 kHz, 13 kHz, 63 Khz, −12 kHz, 88 kHz, etc., and would never be less than the 10 kHz needed for successful synchronization. The number of offset frequencies to search may be determined based on the worst case estimate of possible total error in the estimation of frequency. For example, assume that a ±100 kHz window is sufficient. In this case, the maximum value of k=[(100 kHz−(−100 kHz))/5 kHz]+1=41. Here, k is an index for indexing the offset frequencies, and the search will iterate over each of these indices k, starting with k=1 (block 514).
The variable foffset is generated based on the range to search and is a function of k (is indexed by k). For the above example assuming linear spacing, foffset=−100 kHz, −95 kHz, −90 kHz, . . . 90 kHz, 95 kHz, 100 kHz for the various values of k from 2 to 41 in some order (e.g., where the starting value k=1 corresponds to foffset=0). Given the foregoing example, the following formula may be used to compute the successive values of the divide ratio (for respective iterations k):
N
new=round(fchannelnew/[fchannelold/Nold+fdelta/P+foffsetk/P],7 decimal places)
This equation is similar to the above equation for computing the starting divide term but includes an additional term foffsetk/P which corresponds to the current iteration of the search.
So for k=2, the new divide term is:
N
new=round(2.1 GHz/[2 GHz/76.9230769+23771 Hz/64+(−100 kHz)/64],7 decimal places)
As shown in
Thus, various embodiments remove or reduce frequency error without requiring additional complicated tuning circuits. The technical problem of reducing the frequency error is solved without the use of a crystal oscillator (an expensive component) which has been used in prior approaches. Additionally, the temperature measurement, compensation and frequency tuning of the FRO 102 do not require additional circuits, as the temperature of the FRO 102 is the same as the temperature of the PLLs 110, 112, 114.
Referring to
Based on this estimated frequency shift fdelta, a starting fractional divide term is computed (block 612), and after initialization of the index k to 1 (block 614), the synthesizer (synthesizer 110 or 112) is tuned using the computed divide term (block 616). An iterative search may be performed with respective frequency offsets until synchronization is successful, as shown in the remainder of
Although examples are illustrated and described herein, embodiments are nevertheless not limited to the details shown, since various modifications and structural changes may be made therein by those of ordinary skill within the scope and range of equivalents of the claims.
