Method and apparatus for data permutation/division and recording medium with data permutation/division program recorded thereon

BACKGROUND OF THE INVENTION

The present invention relates to a method and apparatus for efficient implementation of data permutation and division processing in the field of cryptography and a recording medium with a data permutation/division program recorded thereon.

Data encryption is intended to conceal data. Data encryption techniques fall into a common key cryptosystem and a public key cryptosystem.

The public key cryptosystem uses different keys for data encryption and for decryption; usually, the encryption key is made public and the decryption key is held by a user in secrecy. It is believed that the description key could not be derived from the encryption key within a practical amount of time even with modern mathematical theories and the computing power of the present-day computer.

On the other hand, the common key cryptosystem uses the same key for data encryption and decryption. To implement a fast and secure common key cipher, there is proposed a block encipherment scheme that divides data to be enciphered into blocks of an appropriate length and enciphers them one by one. Many of the block ciphers have a structure called a Feistel network. With this structure, an input of 2n bits is divided to right and left pieces of n-bit data, a function f is operated on the right n-bit data, then its output is exclusive ORed with the left n-bit data, then the right and left pieces of data are swapped, and the same operation is repeated. This structure is shown in, “Bruce Schneier, Applied Cryptography, 2

nd

edition, John-Wiley and Sons, p347, 1996.”

The common key cryptosystem is smaller in computational complexity than the public key cryptosystem, and the amount of data that can be encrypted per unit time in the former cryptosystem is tens to hundreds of times larger than in the latter cryptosystem. For this reason, there are tendencies to use the common key cryptosystem when fast encryption processing is necessary.

The common key cryptosystem is required to have security against cryptanalysis as well as the above-mentioned high-speed performance. In recent years there have been proposed several methods of cryptanalysis for common key encryption algorithms. It is necessary, therefore, that a common key encryption algorithm to be newly developed be always secure against such cryptanalysis methods. These cryptanalysis methods are described, for example, in “Bruce Schneier, Applied Cryptography, 2nd edition, John-Wiley and Sons, pp.285-293, 1996.”

There have also been studied schemes that would not allow easy application of the cryptanalysis methods, and it can be expected that such preventive schemes will increase the security of the common key encryption algorithm. According to one of such preventive schemes, a value of some kind available from an encryption key is exclusive ORed with input and output data so as to protect the input and output data for the basic encryption, algorithm from an attacker. This scheme is described in “Bruce Schneier, Applied Cryptography, 2nd edition, John-Wiley and Sons, pp.366-367, 1996.” Many of common key encryption algorithms proposed in recent years are designed using this scheme.

With the above scheme, the input data exclusive ORed with the value of some kind available from the encryption key is used as input data of the basic encryption algorithm. In the case of using the afore-mentioned Feistel network, the input data needs to be divided to right and left data. Some of recently developed common key encryption algorithms are intended to provide increased security not only by dividing the input data to right and left but also by dividing the input data to right and left even after permutation. An example of such algorithms is an E2 cipher (Masayuki KANDA, et al., “A New 128-bit Block Cipher E2,” Technical Report of IEICE, ISEC98-12 (hereinafter referred to simply as literature E2). In the E2 algorithm, a permutation processing called a BP function is defined and then the input data is divided to right and left for input into the Feistel network.

FIG. 1

depicts a basic configuration of an E2 cryptographic device, in which no key scheduling part is shown for brevity. The E2 cryptographic device is made up of an initial transformation part

10

, twelve round processing stages RND

1

to RND

12

, and a final transformation part

30

. The size of each key is, for instance, 128-bit. The initial transformation part

10

comprises: an XOR operation part

11

that exclusive ORs an input plaintext M of, for example, 128 bits with a subkey k

13

; a multiplication part

12

that calculates the product of the output from the XOR operation part

11

and a subkey k

14

; and a byte permutation part (hereinafter referred to as a BP function part)

13

that performs byte permutation of the multiplied output from the multiplication part

12

. To increase the operation efficiency, setting the computation size of a CPU of the computer used, for example, at 32 bits, the operation is carried out for each of four 32-bit subblocks divided from the 128-bit data.

The initial transformation part (hereinafter referred to as an IT function part)

10

performs the following operation for an input X=M using the subkeys k

13

and k

14

.

A=IT

(

X, k

13

, k

14

) (1)

More specifically, letting

X=

(

x

1

, x

2

, x

3

, x

4

)

Y=

(

y

1

, y

2

, y

3

, y

4

)

Z=

(

z

1

, z

2

, z

4

, z

4

)

the following operation is performed by the XOR operation part

11

and the multiplication part

12

.

Z

=(

X⊕k

13

){circle around (×)}

k

14

=Y{circle around (×)}k

14

(2)

In the above, if k

14

=(K

1

, K

2

, K

3

, K

4

), the multiplication Y{circle around (×)}k

14

by the multiplication part

12

is performed as follows:

z

i

=y

i

(

K

i

(hex)

)mod 2

32

for

i=

1,2,3,4 (3)

The operation symbol ab represents the OR of a and b for every corresponding bit. Setting

(

z

i

(1)

, z

i

(2)

, z

i

(3)

, z

i

(4)

)=

z

i

for

i=

1,2,3,4 (4)

Z′

=(

z

1

′, z

2

′, z

3

′, z

4

′)

The operation processing of the BP function part

13

is expressed by the following equation:

z

i

′=(

z′

i

(1)

, z′

i+1

(2)

, z′

i+2

(3)

, z′

i+3

(4)

), i=1,2,3,4, (5)

where

z′

i+4

(j)

=z′

i

(j)

, j=

1,2,3,4 (6)

where i represents the subblock number for each 32 bits and j the data number of each byte in the subblock. In

FIG. 3

there are shown permutations expressed by Eqs. (5) and (6). The four bytes of each piece of data z

1

, z

2

, z

3

and z

4

are distributed to four different output data groups.

The output from the byte permutation part (that is, the BP function part)

13

is divided to right data R

0

and left data L

0

, which are provided to the round processing stage RND

1

. The i-th round processing stage RND

i

performs substitution-permutation processing of right data R

i−1

in a round function part

22

by using a subkey k

i

, and provides the substitution result to an XOR operation part

21

, wherein it is exclusive ORed with left data L

i−1

fed thereto. The right data R

i−1

input to the i-th stage and the output from the XOR operation part

21

are exchanged in position, and they are provided as left data L

i

and right data R

i

to the next round processing stage RND

i+1

.

This is expressed as follows:

R

i

=L

i−1

⊕F

(

R

i−1

, k

i

) (7)

L

i

=R

i−1

, i

=1, 2, . . . , 12 (8)

Each round function part

22

comprises, as depicted in

FIG. 2

, eight XOR operation parts

22

X

1

, eight S-boxes (S function)

22

S

1

, a linear permutation part (a P function part)

22

P, eight XOR operation parts

22

X

2

, and eight S-boxes

22

S

2

. 64-bit right data R is input to the i-th round processing stage RND

i

. In the round function part

22

, setting the input R

i−1

R

i−1

=(

r

1

, r

2

, r

3

, r

4

, r

5

, r

6

, r

7

, r

8)

k

i

=(

K

(1)

, K

(2)

)=(

K

1

(1)

, K

2

(1)

, . . . , K

8

(1)

, K

1

(2)

, K

2

(2)

, . . . , K

8

(2)

)

the outputs from the S-boxes

22

S

1

is given by the following equation:

(

u

1

, u

2

, . . . , u

8

)=(

s

(

r

1

⊕K

1

(1)

),

s

(

r

2

⊕K

2

(1)

), . . . ,

s

(

r

8

⊕K

8

(1)

)) (9)

The output from the linear permutation part

22

P can be expressed as follows:

u′

1

=u

2

⊕u

3

⊕u

4

⊕u

5

⊕u

6

⊕u

7

u′

2

=u

1

⊕u

3

⊕u

4

⊕u

6

⊕u

7

⊕u

8

u′

3

=u

1

⊕u

2

⊕u

4

⊕u

5

⊕u

7

⊕u

8

u′

4

=u

1

⊕u

2

⊕u

3

⊕u

5

⊕u

6

⊕u

8

u′

5

=u

1

⊕u

2

⊕u

4

⊕u

5

⊕u

6

u′

6

=u

1

⊕u

2

⊕u

3

⊕u

6

⊕u

7

u′

7

=u

2

⊕u

3

⊕u

4

⊕u

7

⊕u

8

u′

8

=u

1

⊕u

3

⊕u

4

⊕u

5

⊕u

8

(10)

The outputs from the S-boxes

22

S

2

are expressed by the following equation:

(

v

1

,v

2

,v

3

,v

4

,v

5

,v

6

,v

7

,v

8

)=(

s

(

u′

1

⊕K

1

(2)

),

s

(

u′

2

⊕K

2

(2)

), . . . ,

s

(

u′

8

⊕K

8

(2)

)) (11)

These outputs are subjected to byte rotation and then output from the round function part

22

.

In the case of

FIG. 1

, twelve such round processing stages are cascade-connected, and left and right data L

12

and R

12

output from the 12-th round processing part RND

12

are concatenated into 128-bit data, which is fed to a BP

−1

function part

31

of the final transformation part

30

.

The final transformation part

30

obtains, as a ciphertext X=C, X=FT(Z′, k

15

, k

16

) from the input thereto Z′=(z

1

′, z

2

′, z

3

′, z

4

′) and keys k

15

, k

16

. More specifically, the BP

−1

function part

31

performs inverse processing of the BP function part

13

by the following equation to obtain the output Z.

(

z′

i

(1)

, z′

i

(2)

, z′

i

(3)

, z′

i

(4)

)=

z′

i

, i=

1, 2, 3, 4

z

i

=(

z′

i

(1)

, z′

i−1

(2)

, z′

i−2

(3)

, z′

i−3

(4)

)

i=

1,2,3,4 (12)

where

z′

i−4

(j)

=z′

i

(j)

j=

1,2,3,4 (13)

Z

=(

z

1

, z

2

, z

3

, z

4

)

The output Z is provided to a division part

32

, which performs the division of the following equation using a subkey k

15

=(K

1

,K

2

,K

3

,K

4

).

y

i

=z

i

(

K

i

(hex)

)

−1

mod 2

32

, i=

1,2,3,4 (14)

A variable in Eq. (14) is z

i

alone. Hence, it is possible to provide increased efficiency of calculation to precalculate and prestore the value of an inverse element G

i

=(K

i

(hex)

)

−1

mod 2

32

in a memory, since the stored value can be used to calculate y

i

=z

i

G

i

mod 2

32

for each input data z

i

. The calculation result Y=(y

1

,y

2

,y

3

,y

4

) is exclusive ORed with a subkey k

16

in an XOR operation part

33

by the following equation, and the resulting output X is provided as the ciphertext C.

C=X=Y⊕k

16

(15)

FIG. 3

depicts the input/output relationship by the byte permutation using the BP functions expressed by Eqs. (5) and (6). As shown, the four pieces of 4-byte data z

1

, z

2

, z

3

and z

4

are rearranged on a bytewise basis to obtain the four pieces of 4-byte data z

1

′, z

2

′, z

3

′ and z

4

′. Conventionally, this byte permutation is implemented by performing the operation expressed by the following equation:

z

1

′=(

z

1

ff000000)(

z

2

00ff0000)(

z

3

0000ff00)(

z

4

000000ff)

z

2

′=(

z

2

000000)(

z

3

00ff0000)(

z

4

0000ff00)(

z

1

000000ff)

z

3

′=(

z

3

000000)(

z

4

00ff0000)(

z

1

0000ff00)(

z

2

000000ff)

z

4

′=(

z

4

000000)(

z

1

00ff0000)(

z

2

0000ff00)(

z

3

000000ff) (16)

where the symbol represents the AND for each bit and the symbol the OR for each bit and “f” and “0” are hexadecimal values. This operation is performed as depicted in FIG.

4

. For the sake of brevity, the entire data Z=z

i

(j)

(where i=1,2,3,4; j=1,2,3,4) is represented by a sequence of data a

0

, a

1

, . . . , a

15

. For example, 4-byte data z

1

of a register RG

1

and 4-byte mask data MD

1

of a mask register MRG

1

are ANDed to obtain z

1

ff000000, which is stored in a register RG

1

′. Then, the AND of data z

2

and mask data MD

2

, z

2

00ff0000, is calculated and is ORed with the data read out of the register RG

1

′, and the OR thus obtained is overwritten on the register RG

1

′. By performing the same processing for mask data MD

3

and MD

4

as well, the data z

1

′ is provided in the register RG

1

′. The same calculation processing as described above is also carried out for the data z

2

′, z

3

′ and z

4

′ by Eq. (16). Thus the byte permutation results are obtained in registers RG

1

′ to RG

4

′. In the implementation of this calculation scheme, there have been pointed out such problems as mentioned below. That is, the processing by the BP function is byte-byte permutation processing, but a one-word register built in recent CPUs involves masking and shift operations, and hence it consumes much processing time. And, even if the permutation can be made after the ORs are once copied to a memory, the time for memory access inevitably increases, resulting in the processing time increasing. These problems constitute an obstacle to the realization of high-speed performance of the common key cryptosystem.

In the division part

32

in

FIG. 1

a precalculated inverse element can be used. In general, it is possible to utilize, for the execution of an inverse element calculation to modulus N, an extended Euclidian algorithm set forth, for instance, in Okamoto and Ohta, coeditors, “Cipher/Zero Knowledge Proof/Number Theory,” Kyouritsu Shuppan, 1995, pp.120-121. In the case of Eq. (14), however, since the modulus has a special form of

2

m

, the inverse element can efficiently be calculated by the use of a Hensel Lifting method (a natural method of raising the root of a polynomial from mod b

m

to mod b

m+1

). In the calculation of the inverse element with software, when m is about one word length, a Zassenhaus's proposed method which is a quadratic version of the Hensel Lifting (H. Zassenhaus, “On Hensel Factorization, I,” Journal of number theory, vol.1, pp.291-311, 1969) is effective because the word multiplication is relatively fast on recent CPUs.

Letting the input be represented by x, the output by y and auxiliary or temporary variables by a and b and letting [x] represent a Gauss symbol (the maximum integer which does not exceed x), the Zassenhaus method provides an algorithm for calculating an inverse y=x

−1

mod 2

m

as given below assuming that the bit position is given 0 as the least significant bit and that the bit lengths of x, y, a and b are m, where m=2

n

(n≧1):

Step 1: Input x.

Step 2: Initialize y:=1 and b:=[x/2]

Step 3: Do the following for i=0, 1, . . . , n−1

1. Set a as low-order 2

i

bits of y×(2

2

i

−(low-order 2

i

bits of b)).

2. Pad 2

i

-th to (2

i+1

−1)-th bits of y with low-order 2

i

bits of a.

3. Store 2

i

-th to (2

n

−2

i

−1)-th bits of xa+b in b.

Step 4: Output y.

This bit processing is such as shown in

FIG. 5

, in which the contents of the register having stored therein the output y for state changes of i are represented by binary numbers.

“1” indicates bits whose value is always 1, “.” calculated bits, and “?” unknown bits. In the result with i=2 calculated using i=1, fourth to seventh bits are determined. To arrange data in the fourth to seventh bits will hereinafter be referred to as “padding.”

The configuration of the RSA cipher, which is a typical public key cryptosystem, is described, for example, in the above-mentioned literature “Cipher/Zero Knowledge Proof/Number Theory,” p.220. The RSA cipher requires a power calculation over Z/NZ, that is, what is called a modular exponentiation. For fast execution of this modular exponentiation, it is effective to use the Montgomery modular arithmetic algorithm introduced in the above-mentioned literature on pages 179-181. The execution of the Montgomery modular arithmetic algorithm involves an inverse calculation in mod 2

m

using m as a natural number.

The above-mentioned Zassenhaus scheme involves bitwise processing such as extraction and padding of low-order 2

i

bits and, in the case of software implementation, the masking operation increases, and hence efficiency is not so high.

The round function part

22

of the round processing stage depicted in

FIG. 2

is formed by a combination of the substitution by the S function part

22

S

1

and the permutation by the P function part

22

P.

The substitution-permutation is a concept of a considerably broad meaning. To meet a demand for software implementation in recent years, there has widely been used the substitution-permutation in the following form:

\begin{matrix} [\begin{matrix} y_{1} \\ y_{2} \\ ⋮ \\ y_{m} \end{matrix}] = P [\begin{matrix} s_{1} (x_{1}) \\ s_{2} (x_{2}) \\ ⋮ \\ s_{n} (x_{n}) \end{matrix}] & (17) \end{matrix}

In this instance, operations are all performed over the ring R. The permutation is given by

\begin{matrix} P = [\begin{matrix} p_{11} & p_{12} & \dots & p_{1 n} \\ p_{21} & p_{22} & \dots & p_{2 n} \\ ⋮ & ⋮ & ⋰ & ⋮ \\ p_{m1} & p_{m2} & \dots & p_{mn} \end{matrix}] & (18) \end{matrix}

and the substitution is set to s

j

:R→R(j=1, 2, . . . , n). That is, the product of the matrix is considered as permutation.

The substitution-permutation expressed by Eq. (17) is also used in the cipher SHARK that is defined in V. Rijmen, et al. “The Cipher SHARK,” Fast Software Encryption-Third International Workshop, Lecture Notes in Computer Science 1039, pp. 99-111, Springer-Verlag 1996 (hereinafter referred to simply as Literature S). In Literature S there is also described a method in which the following modified equation is used

\begin{matrix} [\begin{matrix} p_{11} & p_{12} & \dots & p_{1 n} \\ p_{21} & p_{22} & \dots & p_{2 n} \\ ⋮ & ⋮ & ⋰ & ⋮ \\ p_{m1} & p_{m2} & \dots & p_{mn} \end{matrix}] [\begin{matrix} s_{1} (x_{1}) \\ s_{2} (x_{2}) \\ ⋮ \\ s_{n} (x_{n}) \end{matrix}] = &AutoLeftMatch; [\begin{matrix} p_{11} s_{1} (x_{1}) \\ p_{21} s_{1} (x_{1}) \\ ⋮ \\ p_{m1} s_{1} (x_{1}) \end{matrix}] + [\begin{matrix} p_{12} s_{2} (x_{2}) \\ p_{22} s_{2} (x_{2}) \\ ⋮ \\ p_{m2} s_{2} (x_{2}) \end{matrix}] + \dots + [\begin{matrix} p_{1 n} s_{n} (x_{n}) \\ p_{2 n} s_{n} (x_{n}) \\ ⋮ \\ p_{mn} s_{n} (x_{n}) \end{matrix}] & (19) \end{matrix}

and the output value of the function SP

i

expressed by the following equation (20) is precalculated corresponding to every x

j

and prestored, for example, in a memory to thereby efficiently calculate Eq. (17).

\begin{matrix} S P_{j} : R ⟶ R^{m}; S P_{j} (x_{j}) = [\begin{matrix} p_{1 j} s_{j} (x_{j}) \\ p_{2 j} s_{j} (x_{j}) \\ ⋮ \\ p_{mj} s_{j} (x_{j}) \end{matrix}] (j = 1, 2, \dots, n) & (20) \end{matrix}

In the cipher utilizing the substitution-permutation scheme, there is a case where no permutation is performed at the end of processing but only substitution is used. That is, the following processing is also necessary for cipher implementation.

\begin{matrix} [\begin{matrix} y_{1} \\ y_{2} \\ ⋮ \\ y_{n} \end{matrix}] = [\begin{matrix} s_{1} (x_{1}) \\ s_{2} (x_{2}) \\ ⋮ \\ s_{n} (x_{n}) \end{matrix}] & (21) \end{matrix}

When the size of the element in R is smaller than the word length that is the operation unit in the computer used, it is necessary in straightforward implementation that the calculation of individual values of s

j

(X

j

) be followed by shifting them to their correct vector positions. In this instance, the necessity for the data position adjustment process can be avoided by Modifying Eq. (21) to

\begin{matrix} [\begin{matrix} y_{1} \\ y_{2} \\ ⋮ \\ ⋮ \\ y_{n} \end{matrix}] = [\begin{matrix} s_{1} (x_{1}) \\ 0 \\ ⋮ \\ ⋮ \\ 0 \end{matrix}] + [\begin{matrix} 0 \\ s_{2} (x_{2}) \\ 0 \\ ⋮ \\ 0 \end{matrix}] + \dots + [\begin{matrix} 0 \\ ⋮ \\ ⋮ \\ 0 \\ s_{n} (x_{n}) \end{matrix}] & (22) \end{matrix}

as is the case with Eq. (17) and by precalculating a table in which the positions of vector elements have been adjusted so that 0s would be provided except at the j-th position.

The calculation for the substitution and permutation described in Literature S is disadvantageous in that it involves a large number of memory references and requires a large memory capacity.

As described previously, letting the input data be (u

1

, u

2

, . . . , u

8

) and the output data b (u

1

′, u

2

′, . . . , u

8

′), the P function part

22

P in the cipher E2 shown in

FIG. 2

, for instance, performs an operation using the product expressed by the following equation.

\begin{matrix} [\begin{matrix} u_{1}^{'} \\ u_{2}^{'} \\ u_{3}^{'} \\ u_{4}^{'} \\ u_{5}^{'} \\ u_{6}^{'} \\ u_{7}^{'} \\ u_{8}^{'} \end{matrix}] = P [\begin{matrix} u_{1} \\ u_{2} \\ u_{3} \\ u_{4} \\ u_{5} \\ u_{6} \\ u_{7} \\ u_{8} \end{matrix}], P = [\begin{matrix} 0 & 1 & 1 & 1 & 1 & 1 & 1 & 0 \\ 1 & 0 & 1 & 1 & 0 & 1 & 1 & 1 \\ 1 & 1 & 0 & 1 & 1 & 0 & 1 & 1 \\ 1 & 1 & 1 & 0 & 1 & 1 & 0 & 1 \\ 1 & 1 & 0 & 1 & 1 & 1 & 0 & 0 \\ 1 & 1 & 1 & 0 & 0 & 1 & 1 & 0 \\ 0 & 1 & 1 & 1 & 0 & 0 & 1 & 1 \\ 1 & 0 & 1 & 1 & 1 & 0 & 0 & 1 \end{matrix}] & (23) \end{matrix}

where: u

i

, u

j

′εR

This operation is expressed merely as the product of a matrix and is the same as Eq. (10). In an environment where a permutation operation using masked data or a permutation operation using a bit shift or cyclic shift is possible by processing every 32 bits, the required number of processing steps is small, and hence fast processing can be achieved. However, since such operation processing cannot be performed in a hardware environment formed by an 8-bit accumulator type CPU, a small number of registers and a small amount of memory capacity as in the case of a low-end smart card, the operation of Eq. (10) needs to be executed successively, and hence high-speed processing is difficult to perform.

The following description will be given on the assumption that in an implementation environment formed by one 8-bit accumulator, a small number of registers and a small amount of memory, the input data (u

1

, u

2

, . . . , u

8

) is stored in the memory and is read out therefrom, and the permutation output data u

1

′, u

2

′, . . . , u

8

′ is calculated and stored in the memory; the computational complexity in this instance is evaluated. The evaluation is made in terms of the number of times an addition/subtraction is performed, the number of times the memory is written and the number of times the memory is read. And let it be assumed that the permutation operation is performed by calculating Eq. (23) using the above-mentioned matrix P.

Conventional scheme 1: If the permutation operation of Eq. (23) is carried out as defined, then Eq. (10) needs to be calculated successively. The computational complexity in this case is as follows:

Number of additions/subtractions: 36

Number of memory reads: 44

Number of memory writes: 8

With this scheme, the number of memory reads is equal to the total number of elements of the matrix P which have a “1” component. Accordingly, the computational complexity increases with an increase in the number of elements whose components are “1s”.

Conventional scheme 2: In Literature E2 there is described, as the permutation scheme using the matrix P, a scheme that uses GF(2

8

) as the ring R and calculates the following equations.

a

5

= u

5

+u

1

b

1

= u

1

+ a

7

u

5

′ = a

5

+ b

4

u

1

′ = b

1

+ u

5

′

a

6

= u

6

+u

2

b

2

= u

2

+ a

8

u

6

′ = a

6

+ b

1

u

2

′ = b

2

+ u

6

′

a

7

= u

7

+u

3

b

3

= u

3

+ a

5

u

7

′ = a

7

+ b

2

u

3

′ = b

3

+ u

7

′

a

8

= u

8

+u

4

b

4

= u

4

+ a

6

u

8

′ = a

8

+ b

3

u

4

′ = b

4

+ u

8

′

The computational complexity of this scheme is as follows:

Number of additions/subtractions: 16

Number of memory reads: 32

Number of memory writes: 16

This scheme is more effective than scheme 1 in the case where the number of registers used is large and addition instructions are orthogonal (the addition instructions can be executed for all the registers). However, this scheme has such disadvantages such listed below.

(a) Since the scheme essential utilizes that the characteristic of R is 2, it cannot be used when the characteristic is not 2.

(b) Since a large number of registers cannot be used, this scheme is not always efficient in some implementation environments.

(c) The computational complexity depends largely on the component configuration of the matrix P.

Conventional scheme 3: When the number of “1” components is large as in the case of the matrix P, the following calculation scheme can be used.

σ

=u

1

+u

2

+u

3

+u

4

+u

5

+u

6

+u

7

+u

8

u

1

′=σ−u

1

−u

8

u

2

′=σ−u

2

−u

5

u

3

′=σ−u

3

−u

6

u

4

′=σ−u

4

−u

7

u

5

′=σ−u

3

−u

7

−u

8

u

6

′=σ−u

4

−u

5

−u

8

u

7

′=σ−u

1

−u

5

−u

6

u

8

′=σ−u

2

−u

6

−u

7

The computational complexity of this scheme is as follows:

Number of additions/subtractions: 27

Number of memory reads: 36

Number of memory writes: 9

This scheme is more efficient than scheme 1 when the number of elements of the matrix P having the “1” component accounts for more than 60% of the total number of elements.

In any of the above conventional schemes, the efficiency of the permutation by the matrix P depends on how {0, 1} components of the matrix P are distributed; in particular, the computational complexity is determined by the rate at which the elements of the “1” component are present. That is, there is a possibility that scheme 1 or 3 becomes efficient according to the configuration of the matrix P; hence, these schemes are not versatile. Which of these schemes becomes more efficient depends on whether the number of elements of the matrix P having the “1” component is more than 60% of the total number of elements.

To implement secure permutation that can be used in cryptography, it is desirable that the rates of “0” and “1” components in the matrix P be well balanced. For example, in the case of the above matrix P used for the permutation in the cipher E2, the elements of the “1 ” component is about ⅔ of the total number of matrix elements. Since this value is close to the point of determining which scheme becomes more efficient, schemes 1 to 3 are almost common in the number of times the memory is read. This means that these conventional schemes produce substantially no effects of increasing the processing speed, because reading from or writing to the memory is several times lower in speed than addition and subtraction; therefore, the implementation of any of the schemes will not answer the intended purpose of faster permutation operation.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a data permutation method and apparatus which permit fast processing for the permutation of data with the BP function in the cipher E2 and the division of data to left and right pieces in the Feistel network through the use of one-word registers.

Another object of the present invention is to provide an inverse calculating method and apparatus which permit reduction of the number of masking operations involved.

Another object of the present invention is to provide a substitution-permutation method and apparatus which permit reduction of the number of memory reference and the required storage capacity.

Still another object of the present invention is to provide an operation method which permits reduction of computational complexity in the permutation using the matrix P.

According to a first aspect of the present invention, there is provided a data permutation method by which, letting one byte be k-bit, k being an integer equal to or greater than 1, input data of 16 bytes set, in units of four bytes, in 4k-bit long first to fourth registers is permutated, the method comprising the steps of:

(a) ANDing 4-byte first mask data with the data of said first register and 4-byte second mask data with the data of said third register, and ORing the two ANDs as first output data;

(b) ANDing 4-byte third mask data with the data of said second register and 4-byte fourth mask data with the data of said fourth register, and ORing the two ANDs as second output data;

(c) ANDing said second mask data with the data of said first register and said first mask data with the data of said third register, and ORing the two ANDs as third output data;

(d) ANDing said fourth mask data with the data of said second register and said third mask data with the data of said fourth register, and ORing the two ANDs as fourth output data; and

(e) outputting said first to fourth data as permutated data;

wherein all bits of predetermined two of four bytes of said first mask data are “1s,” all bits of the remaining two bytes are “0s,” said second mask data is complementary to said first mask data, said third mask data is a 1-byte-rotated version of said first mask data, and said fourth mask data is complementary to said third mask data.

Alternatively, according to a first aspect of the present invention, there is provided a data permutation method by which, letting one byte be k-bit, k being an integer equal to or greater than 1, input data of 16 bytes set, in units of four bytes, in 4k-bit long first to fourth registers is permutated, the method comprising the steps of:

(a) rotating the data of said first and third registers one byte in one direction, and concatenating them to form first concatenated data;

(b) concatenating the data of said second and fourth registers to form second concatenated data;

(c) shifting said first and second concatenated data two bytes in one direction, and extracting, as first and second output data, two pieces of 4-byte data from said shifted first and second concatenated data at one end thereof in the shift direction;

(d) concatenating said rotated data of said third and first registers to form third concatenated data;

(e) concatenating the data of said fourth and second registers to form fourth concatenated data;

(f) shifting said third and fourth concatenated data two bytes in one direction, and extracting, as third and fourth output data, two pieces of 4-byte data from said shifted third and fourth concatenated data at one end thereof in the shift direction; and

(g) outputting said first to fourth output data as permutated data.

According to a second aspect of the present invention, there is provided an inverse calculating apparatus comprising:

input means for storing an input x in storage means;

storage means for storing integers n and i (where n is equal to or greater than 1) and 2

n

-bit integers x, y, a and b;

first b-initialization means for calculating [x/2] by using said x stored in said storage means (where [x] is the maximum integer not exceeding said x), and for storing the calculation result as b in said storage means;

a-initialization means for storing, as said a, in said storage means the least significant bit of said b stored in said storage means;

second b-initialization means for calculating [(ax+b)/2] by using said a, x and b stored in said storage means and for updating said b stored in said storage means with the calculation result;

y-updating means for calculating y+a×2{circumflex over ( )}(2

i

) using said a, y and i stored in said storage means and updating said y stored in said storage means with the calculation result (where p{circumflex over ( )}q represents the q-th power of p);

i-updating means for updating said i stored in said storage means to i+1;

a-updating means for calculating −by by using said b and y stored in, said storage means and for updating said a stored in said storage means with the calculation result;

b-updating means for calculating [(b+ax)/(2{circumflex over ( )}(2

i

))] by using a, b, x and i stored in said storage means and for updating said b stored in said storage means;

y-updating means for calculating y+a×2{circumflex over ( )}(2

i

) by using said a, y and i stored in said storage means and for updating said y stored in said storage means with the calculation result;

i-updating means for updating said i stored in said storage means to i+1;

control means for reading out said i and n stored in said storage means and actuating said a-updating means, said b-updating means, said y-updating means and said i-updating means one after another until i=n; and

output means for outputting said y stored in said storage means.

According to a third aspect of the present invention, there is provided a substitution-permutation apparatus which, by the following substitution-permutation over a ring R

[\begin{matrix} y_{1} \\ y_{2} \\ ⋮ \\ y_{m} \end{matrix}] = P [\begin{matrix} s_{1} (x_{1}) \\ s_{2} (x_{2}) \\ ⋮ \\ s_{n} (x_{n}) \end{matrix}] where P = [\begin{matrix} p_{11} & p_{12} & \dots & p_{1 n} \\ p_{21} & p_{22} & p_{2 n} \\ ⋮ & ⋮ \\ p_{m1} & p_{m2} & \dots & p_{mn} \end{matrix}]

p_{ij} \in R, s_{j} : R ⟶ R i = 1, 2, \dots, m j = 1, 2, \dots, n

performs a substitution-permutation operation of an input data sequence (x

j

) to calculate a data sequence (y

i

), said apparatus comprising:

storage means for storing: precalculated values of v

i

(whose dimensions are up to m and may differ individually) over said ring R necessary for said substitution-permutation, obtained by swapping rows or columns of said matrix P for some p

ij

or s

j

of the same values; a precalculated value of a function S

k

:R→R

m

; precalculated values of n vectors w

k

εR

m

; and an integer k;

input means for storing said input data sequence x

j

in said storage means;

k-initialization means for setting said integer k to 0;

k-updating means for updating said k in said storage means to k+1;

S

k

calculating means for reading out each S

k

and input data (x

k

) from said storage means to obtain the result of calculation of a vector S

k

(x

k

) and for storing said vector as a vector w

k

in said storage means;

u

k

-generating means for reading out of said storage means a set of vectors {v

1

} necessary for forming a k-th column of said matrix P and for generating a vector u

k

;

u

k

*S

k

calculating means for reading out said w

k

from said storage means and calculating the product for each element and for updating said w

k

with the calculation result;

control means for reading out said k stored in said storage means and for actuating said S

k

calculating means, said u

k

*S

k

calculating means and said k-updating means one after another until k=n; and

output means for reading out each w

k

stored in said storage means and for calculating and outputting their sum.

Alternatively, according to a third aspect of the present invention, a substitution-permutation apparatus which, by the following substitution-permutation over a ring R

[\begin{matrix} y_{1} \\ y_{2} \\ ⋮ \\ y_{m} \end{matrix}] = P [\begin{matrix} s_{1} (x_{1}) \\ s_{2} (x_{2}) \\ ⋮ \\ s_{n} (x_{n}) \end{matrix}] where P = [\begin{matrix} p_{11} & p_{12} & \dots & p_{1 n} \\ p_{21} & p_{22} & p_{2 n} \\ ⋮ & ⋮ \\ p_{m1} & p_{m2} & \dots & p_{mn} \end{matrix}]

p_{ij} \in R, s_{j} : R ⟶ R i = 1, 2, \dots, m j = 1, 2, \dots, n

performs a substitution-permutation operation of an input data sequence (x

j

) to produce a data sequence (y

i

), comprisies:

storage means for storing a precalculated value of the following equation with rows of a matrix P rearranged

S P_{1 j} (x_{j}) = [\begin{matrix} p_{t (q1) j} s_{j} (x_{j}) \\ p_{t (q1 + 1) j} s_{j} (x_{j}) \\ ⋮ \\ p_{t (r1) j} s_{j} (x_{j}) \end{matrix}]

(where b(j) is a natural number equal to or greater than 1 but equal to or smaller than m, l=1, 2, . . . , b(j), t:{1, 2, . . . , m}→{1, 2, . . . , m} is permutation, and ql and rl are natural numbers equal to or greater than 1 but equal to or smaller than n, ql≦rl) together with precalculated values of n vectors w

k

εR

m

and an integer k;

input means for storing said input data sequence (x

i

) in said storage means;

k-initialization means for setting said integer k to 0;

k-updating means for updating said k stored in said storage means to. k+1;

SP

k

calculating means for reading out input data x

k

and SP

lj

(x

k

) from said storage means, for calculating said SP

lj

(x

k

) for each l (where l=1, 2, . . . , b(j)) and concatenating the calculated results in correspondence to a k-th column of said rearranged matrix P to obtain an m-dimensional vector, and: for updating said w

k

stored in said storage means with said m-dimensional vector as w

k

;

control means for reading out said k stored in said storage means and for actuating said SP

k

calculating means and said k-updating means one after the other until k=n; and

output means for reading out each w

k

stored in said storage means and for calculating and outputting their sum.

According to a fourth aspect of the present invention, there is provided a permutation method in which an operating apparatus including an accumulator type CPU and registers is used to permute input data u

1

, u

2

, . . . , u

n

by the following equation using an m by n matrix P of predetermined {0, 1} elements to obtain permuted data (u

1

′, u

2

′, . . . , u

m

′)

[\begin{matrix} u_{1}^{'} \\ u_{2}^{'} \\ ⋮ \\ u_{n}^{'} \end{matrix}] = P [\begin{matrix} u_{1} \\ u_{2} \\ ⋮ \\ u_{n} \end{matrix}]

said method comprising the steps of:

(a) setting each piece of said permuted data u

j

′ by the following equation using already calculated u

i

′

u

j

′=u

i

′+D

i

where j≠i, and j are integers equal to or greater than 1 and equal to or smaller than n, n is an integer equal to or greater than 2 and D

i

is given by the difference D

i

=u

j

′-u

i

′ between said permuted data u

j

′ and u

i

′ defined by said matrix P using said input data u

1

, u

2

, . . . , u

n

; and

(b) calculating said u

j

′ for all of said j.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1

is a block diagram illustrating the configuration of an E2 cryptographic device that is an example of application of the present invention;

FIG. 2

is a block diagram depicting the configuration of a round function part

22

of each round processing stage in

FIG. 1

;

FIG. 3

is a diagram depicting the relationship between data arrangements before and after permutation by a byte permutation part

13

in

FIG. 1

;

FIG. 4

is a diagram for explaining the procedure by which the permutation of

FIG. 3

is performed by a logical operation using mask data;

FIG. 5

is a diagram depicting the register contents in the case of performing an inverse calculation by a conventional method in a division part

32

in

FIG. 1

;

FIG. 6

is a diagram showing an example of the byte permutation by the present invention;

FIG. 7

is a diagram showing another example of the byte permutation by the present invention;

FIG. 8

is a diagram depicting the procedure which is followed in performing the byte permutation of

FIG. 6

by a logical operation using mask data;

FIG. 9

is a diagram depicting the procedure which is followed in performing the byte permutation of

FIG. 7

by a bit shift and a cyclic shift;

FIG. 10

is a block diagram depicting the configuration of a byte permutation part

13

;

FIG. 11

is a flowchart showing the procedure of an inverse calculation by the present invention;

FIG. 12

is a block diagram depicting an example of the configuration of an apparatus for the inverse calculation of

FIG. 11

;

FIG. 13

is a block diagram depicting an example of the configuration of an apparatus for performing the substitution-permutation by this invention method in an S and P function parts in the round function part

22

of

FIG. 2

;

FIG. 14

is a block diagram depicting another example of the configuration of the apparatus for performing the substitution-permutation by this invention method in an S and P function parts in the round function part

22

of

FIG. 2

; and

FIG. 15

is a block diagram illustrating an example of the configuration of an apparatus for performing the operation of a P function part

22

P in FIG.

2

.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiment 1

A description will be given first of the procedure by the present invention which facilitates the operation in the byte permutation part, that is, the BP function part

13

in

FIG. 1

in the cipher E2. In the following description, 16 pieces of input k-bit byte data will be identified as a

0

, a

1

, . . . a

15

, and permutated output data as A

1

,A

2

,A

3

,A

4

. The BP function part

13

is supplied with 16 pieces of 1-byte input data a

0

, a

1

, . . . , a

15

and outputs byte-permutated data as right and left data. In this embodiment the arrangement of output data is appropriately chosen and the permutation for rearranging the data as chosen is performed by a procedure involving a smaller number of steps than in the prior art.

In this embodiment, the four pieces of data {a

4i+j

} (where 0≦j≦3) are stored as a

4i+0

, a

4i+1

, a

4i+2

, a

4i+3

in each 4k-bit register T

i

(where i=0, 1, 2, 3) shown in

FIG. 8

; the four pieces of data are included in 16 pieces of k-bit data {a

4i+j

} (where 0≦i≦3, 0≦j≦3) which are input into the BP function part

13

(FIG.

1

). The data stored in this form will hereinafter be described as follows:

T

i

=[a

4i+0

a

4i+1

a

4i+2

a

4i+3

] (24)

The left data set [L] and the right data set [R] at the output of the BP function part

13

are defined in the cipher E2 as follows:

\begin{matrix} \begin{matrix} [L] = {a_{4 (i + j \mod 4) + j} | 0 \leq i \leq 1, 0 \leq j \leq 3} \\ = {a_{0}, a_{3}, a_{4}, a_{5}, a_{9}, a_{10}, a_{14}, a_{15}} \end{matrix} & (25A) \\ \begin{matrix} [R] = {a_{4 (i + j \mod 4) + j} | 2 \leq i \leq 3, 0 \leq j \leq 3} \\ = {a_{1}, a_{2}, a_{6}, a_{7}, a_{8}, a_{11}, a_{12}, a_{13}} \end{matrix} & (25B) \end{matrix}

This embodiment also performs the permutation and division of data accordingly. Incidentally, in the specification of the cipher E2, it does not matter even if the right and left data sets differ in the order of 8-byte data; hence, in the present invention, the order of data in either of the right and left data sets is chosen as to achieve the intended reduction of the computationaal complexity in the permutation using masking operations and in the permutation using shift operations.

The input 16-byte data a

0

,a

1

. . . , a

15

is rearranged not on such a byte-by-byte basis as depicted in

FIG. 3

but, for example, every two bytes as depicted in

FIG. 6

or

7

. This permits reduction of procedure steps as described below.

In this embodiment, 1 byte is k-bit and k can be implemented by an arbitrary integer; but k is set at 8 for the sake of brevity. In the following description, let it be assumed that pieces of data “O” and “I” represent binary numbers “00000000” and “11111111,” respectively. They will also be denoted by “00” and “ff” in the hexadecimal notation.

FIG. 8

depicts the procedure by which the byte permutation shown in

FIG. 6

is performed using mask data. The registers T

0

, T

1

, . . . , T

3

are 4k-bit; long registers, which are used to permute and divide 16 pieces of k-bit data {a

4i+j

} (0≦i≦3, 0≦j≦3) into a set {a

4(i+j mod 4)+j

} (0≦i≦1, 0≦j≦3) and a set {a

4(i+j mod 4)+j

} (2≦i≦3, 0≦j≦3) as described below.

Step 1: Data {a

4i+j

} (i=0,1,2,3; j=0,1,2,3) is stored in each register T

i

. Data (O, a

1

, a

2

, O) obtained by ANDing the value (a

0

,a

1

,a

2

,a

3

) of the register T

0

and mask data MD

0

=(2

3k

−2

k

)=(O, I, I, O) of a mask register MRG0 is stored in a register T

0

′; data (a

8

, O, O, a

11

) obtained by ANDing the value (a

8

,a

9

,a

10

,a

11

) of the register T

2

and mask data MD

2

=(2

4k

−2

3k

+2

k

−1)=(I, O, O, I) of a mask register MRG2 is stored in a register T

2

′; and the value (a

8

,a

1

,a

2

,a

11

) obtained by ORing the values of the registers T

0

′ and T

2

′ is stored in a register T

4

.

Step 2: Data (O, O, a

6

, a

7

) obtained by ANDing the value (a

4

,a

5

,a

6

,a

7

) of the register T

1

and mask data MD

1

=(2

2k

−1)=(O, O, I, I) of a mask register MRG1 is stored in a register T

1

′; data (a

12

, a

13

, O, O) obtained by ANDing the value (a

12

,a

13

,a

14

,a

15

) of the register T

3

and mask data MD

3

=(2

4k

−2

2k

)=(I, I, O, O) of a mask register MRG3 is stored in a register T

3

′; and the value (a

12

,a

13

,a

6

,a

7

) obtained by ORing the values of the registers T

1

′ and T

3

′ is stored in a register T

5

.

Step 3: Data (a

0

, O, O, a

3

) obtained by ANDing the value (a

0

,a

1

,a

2

,a

3

) of the register T

0

and mask data (2

4k

−2

3k

+2

k

−1)=(I, O, O, I) of a mask register MRG0′ is stored in a register T

0

″; data (O, a

9

, a

10

, O) obtained by ANDing the value (a

8

,a

9

a

10

,a

11

) of the register T

2

and mask data (2

3k

−2

k

)=(O, I, I, O) of a mask register MRG2′ is stored in a register T

2

″; and the OR (a

0

,a

9

,a

10

,a

3

) of the values of the registers T

0

″ and T

2

″ is stored in a register T

6

.

Step 4: Data (a

4

, a

5

, O, O) obtained by ANDing the value (a

4

,a

5

,a

6

,a

7

) of the register T

1

and mask data (2

4k

−2

2k

)=(I, I, O, O) of a mask register MRG1′ is stored in a register T

1

″; data (O, O, a

14

, a

15

) obtained by ANDing the value (a

12

,a

13

,a

14

,a

15

) of the register T

4

and mask data (2

2k

−1)=(O, O, I, I) of a mask register MRG3′ is stored in a register T

3

″; and the OR (a

4

,a

5

,a

14

,a

15

) of the values of the registers T

1

″ and T

3

″ is stored in a register T

7

.

Step 5: The pieces of data of the two register groups T

6

-T

7

and T

4

-T

5

are output as left and right pieces of data.

The permutation processing using mask data as described above can be expressed by the following logical operation, in which the data is represented in hexadecimal.

A

1

=(

z

1

ff0000ff)(

z

3

00ffff00)

A

2

=(

z

2

ffff0000)(

z

4

0000ffff)

A

3

=(

z

3

ff0000ff)(

z

1

00ffff00)

A

4

=(

z

4

ffff000)(

z

2

0000ffff) (26)

As is evident from the above equation, the numbers of AND and OR operations using mask data involved in obtaining the permuted outputs A

1

,A

2

,A

3

,A

4

are eight and four, which are smaller than in the prior art example described previously with reference to Eq. (16).

FIG. 9

depicts the procedure for the permutation shown in FIG.

7

. In the

FIG. 7

example, too, each piece of 4-byte data is rearranged in units of two bytes. This permutation is carried out as depicted in

FIG. 9

using, for instance, shift and cyclic shift (i.e., rotation) techniques.

Each register T

i

is 4k-bit long and k=8 in this example, too. This is a data permutation-division method which permute and divide 16 pieces of k-bit data {a

4i+j

} (0≦i≦3, 0≦j≦3) into a set {a

4(i+j mod 4)+j

} (0≦i≦1, 0≦j≦3) and a set {a

4(i+j mod 4)+j

} (2≦i≦3, 0≦j≦3).

Step 1: The data {a

4i+j

} (0≦i≦3, 0≦j≦3) is stored in each register T

i

(i=0, 1,2,3).

Step 2: The values of (a

0

,a

1

,a

2

,a

3

) and (a

8

,a

9

,a

10

,a

11

) of the registers T

0

and T

2

are rotated k-bit in one direction, in this example, to right.

Step 3: The registers T

0

and T

2

are concatenated into an apparently 8k-bit long register T

0

′; its data is shifted left 2k bits and then 4k-bit data (a

1

,a

2

,a

11

,a

8

) extracted from the register at the end in the shift direction is stored in the register T

4

. The registers T

1

and T

3

are concatenated into an apparently 8k-bit long register T

2

′; its data is shifted left 2k bits and then 4k-bit data (a

6

,a

7

,a

12

,a

13

) extracted from the register at the end in the shift direction is stored in the register T

5

.

Step 4: The registers T

2

and T

0

are concatenated into an apparently 8k-bit long register T

0

″; its data is shifted right 2k bits and then 4k-bit data (a

9

,a

10

,a

3

,a

0

) extracted from the register at the end in the shift direction is stored in the register T

6

. The registers T

3

and T

1

are concatenated into an apparently 8k-bit long register T

2

″; its data is shifted right 2k bits and then 4k-bit data (a

14

,a

15

,a

4

,a

5

) extracted from the register at the end in the shift direction is stored in the register T

7

.

Step 5: The pieces of data A

1

, A

2

and A

3

, A

4

of the two register groups T

6

-T

7

and T

4

-T

5

are output as left and right pieces of data.

In the example of

FIG. 9

, the same results are obtained irrespective of the shift direction in steps 3 and 4. When the direction of rotation is reversed in step 2, the resulting pieces of data are the same as in the case where the contents of the registers T

4

and T

6

are exchanged, thus achieving similar permutation-division.

The processing depicted in

FIG. 9

can be expressed by the following operation, in which the following definitions are used.

x<<b: b

-bit left shift of

x

x>>b: b

-bit right shift of

x

ROL

(

x,y

)=(

x<<b

)(

x

>>(

w−k

)), where

w

is the number of bits of

x.

ROR

(

x,b

)=(

x>>b

)(

x

>>(

w−b

)), where

w

is the number of bits of

x.

SHLD

(

x,y,b

)=(

x<<b

)(

y

>>(

w−b

)), where

w

is the number of bits of

y.

SHRD

(

x,y,b

)=(

x>>b

)(

y

<<(

w−b

)), where

w

is the number of bits of

y.

A

1

=SHRD

(

ROR

(

z

3

,k

),

ROR

(

z

1

,k

),2

k

)

A

2

=SHRD

(

z

4

,z

2

,2

k

)

A

3

=SHLD

(

ROR

(

z

1

,k

),

ROR

(

z

3

,k

),2

k

)

A

4

=SHLD

(

z

2

,z

4

,2

k

) (27)

With this method, the permuted results A

1

,A

2

,A

3

,A

4

obtained by two cyclic shifts and four concatenated shifts.

The byte permutation could also be performed by the combined use of the first-mentioned method (utilizing mask data) and the second-mentioned method (utilizing bit shift and cyclic shift). For example, in the first method, the second method may be used to calculate A

2

and A

4

in Eq. (26) by the following equation:

A

2

=SHRD

(

z

4

,z

2

,2

k

)

A

4

=SHLD

(

z

2

,z

4

,2

k

) (28)

Also it is possible to use the second method to calculate A

1

and A

3

in Eq.(26) by the following equation:

A

1

=SHRD

(

ROR

(

z

3

,k

),

ROR

(

z

1

,k

),2

k

)

A

3

=SHLD

(

ROR

(z

1

,k

),

ROR

(

z

3

,k

),2

k

) (29)

Conversely, in the method using Eq. (27), the first method may also be used to calculate A

2

and A

4

by the following equation:

A

2

=(

z

4

0000ffff)(

z

2

ffff0000)=(

a

4

,a

5

,a

14

,a

15

)

A

4

=(

z

2

0000ffff)(

z

4

ffff000)=(

a

12

a

13

, a

6

,a

7

) (30)

It is also possible to use the first method to calculate A

1

and A

3

in Eq. (27) by the following equation:

A

1

=(

z

3

00ffff00)(

z

1

ff0000ff)=(

a

0

,a

9

,a

10

,a

3

)

A

3

=(

z

1

00ffff00)(

z

3

ff0000ff)=(

a

9

,a

1

,a

2

,a

11

) (31)

The above byte permutation method is also applicable to the BP

−1

function part (

FIG. 1

) that performs inverse processing. For example, when the permutation shown in

FIG. 6

is performed in the BP function part

13

, the inverse processing needs only to be carried out by the following equation:

z

1

=(

A

1

ff0000ff)(

A

3

00ffff00)

z

2

=(

A

2

ffff0000)(

A

4

0000ffff)

z

3

=(

A

3

ff0000ff)(

A

1

00ffff00)

z

4

=(

A

4

ffff0000)(

A

2

0000ffff) (32)

Similarly, when the permutation of

FIG. 7

has been carried out, the inverse processing is done by the following equation:

z

1

=ROL

(

SHLD

(

A

1

,A

3

,2

k

),

k

)

z

2

=SHLD

(

A

2

,A

4

,2

k

)

z

3

=ROL

(

SHRD

(

A

1

,A

3

,2

k

),

k

)

z

4

=SHRD

(

A

2

,A

4

,2

k

) (33)

All of the ORs in the above-described first embodiment may also be replaced with additions or XORs.

FIG. 10

illustrates in block form the BP function part

13

that performs the permutation depicted in

FIG. 8

or

9

. A control part

131

controls respective processing parts following a byte permutation execution program prestored in a memory

130

. In an input data storage part

135

there is held input data {a

4i+j

} (0≦i≦3, 0≦j≦3), which is set in registers T

0

to T

3

in a register part

134

of an operation processing part

132

under the control of the control part

131

. The control part

131

follows the permutation executing program to issue register data shift and rotation instructions to predetermined registers SH and RO, controls the data transfer between each shift register and a logical operation part

133

, and issues to the latter operation instructions for ORing, ANDing and other logical operations and an instruction for the use of mask data of the mask register MRG in such logical operations. The permuted data is transferred from registers T

4

, T

5

, T

6

and T

7

of the register part

134

to an output data storage part

136

, from which it is output as right and left data.

As depicted in

FIG. 3

, according to the specification of the cipher E2, the 4 bytes retained in each register of the input part will each be distributed to one of the four registers of the output part when the input data to the BP function part is stored in units of 4 bytes in the four registers from left to right. In the case of an instruction which is used to perform an operation for one register and store therein the operation result as in ordinary MPUs, only one byte can be processed for one instruction; hence, at least 16 instructions are needed to perform the permutation depicted in FIG.

3

. In practice, more than 16 instructions are required to perform masking, ORing and other logical operations.

It is considered that 16 instructions may sometimes be enough when each byte of the registers is used directly as an instruction; in this case, however, some MPUs incur a penalty attributable to their configuration, resulting in the processing time becoming longer than in the case of using 16 instructions as usual. Also it is possible to use a method in which input data once written in a memory is read out therefrom and into the BP function part on a byte-wise basis for the permutation therein. In recent MPUs, however, access to the memory causes a penalty in many cases, and in some cases the penalty occurs owing to the MPU configuration as in the above; in these instances, too, the processing time becomes longer than those needed to execute 16 instructions.

In contrast thereto, according to the present invention, the operation procedure by Eq. (27) enables the byte permutation in the cipher E2 to be performed by two rotate instructions and four instruction for shifting right or left the data of the two concatenated registers and for storing the right or left data concerned in a predetermined register. The instructions for latter half processing are standard with, for example, Intel 80386 MPU or later, and hence they can be implemented without any problems. Accordingly, this invention method permits faster processing of the BP function operation than the existing methods.

In an MPU on which such instructions are not concretely implemented, they can be substituted with two masking instructions and one ORing instruction. That is, while in the above the permuted data A

1

in Eq. (27) has been described to be calculated by the processing in which the registers T

2

and T

0

after the cyclic shift are concatenated into a virtually 8k-bit long register T

0

″ and the data of the rightmost 4k-bit data of the register T

0

″ after the 2k-bit right shift is stored as the data A

1

of the register T

6

, the permuted data A

1

can also be obtained by such processing as indicated by Eq. (31), in which data (O, a

9

, a

10

, O) obtained by ANDing data Z

3

of the register T

2

and mask data (2

3k

−2

k

)=(00ffff00) is stored in a register T

1

″ (not shown), data (a

0

, O, O, a

3

) obtained by ANDing data z

1

of the register T

0

and mask data (2

4k

−2

3k

+2

k

−1)=(ff0000ff) is stored in a register T

3

″ (not shown) and the value (a

0

, a

9

, a

10

, a

3

) obtained ORing the data of the register T

1

″ and the data of the register T

3

″ is stored in the register T

6

. The operation for the data A

3

in Eq. (31) can also be made in a similar way. The operation does not involve the execution of any cyclic shift instruction, and hence it can be described by a total of 12 instructions, ensuring faster operation of the BP function than does the prior art.

Incidentally, the value A

1

by Eq. (31) and the value A

1

held in the register T

6

in

FIG. 9

differ in that they have been rotated one byte relative to each other. In either case, however, the register T

6

holds four pieces of data a

0

, a

3

, a

9

and a

10

—this guarantees that the registers T

6

and T

7

hold the value of the set [R] just enough. The same is true of the relationship between the value A

3

by Eq. (31) and the value A

3

held in the register T

4

in FIG.

9

.

In the cipher E2, since the basic encryption processing part performs byte-by-byte processing, the arrangement of, for example, the right-hand data need not always conform to the specification. That is, the implementation part of the encryption part needs only to correspond to the rearranged byte sequence.

Further, in this embodiment, the sets of bytes after permutation are divided to right and left in a correct order though different from the specified one. With the recent MPUs, it is possible to achieve particularly fast implementation of the BP function part in the cipher E2 for the data permutation and division used in cryptographic technology even when instructions for concatenating two registers into a virtually single register, shifting its data and storing high- or low-order data in the register are implemented on the MPUs. Such data permutation-division by the BP function in the cipher E2 is implemented using a data permutation-division: program, which is offered as being recorded on a recording medium. This facilitates the distribution of the program.

Embodiment 2

A second embodiment of the present invention is intended to efficiently perform an inverse calculation over an integral residue class ring, for example, in the division part

32

of the final transformation part

30

in FIG.

1

. In step 3-2 of the afore-mentioned Zassenhaus algorithm, this embodiment immerses a in y not intact but by addition. This utilizes the property of the Zassenhaus algorithm that correct results could be obtained by reversing the sign even without masking in step 3-1.

That is, this embodiment calculates an inverse element y=x

−1

mod 2

m

of the input x. Let a and b be temporary variables, m=2

n

(n≧1) and m be bit lengths of x, y, a and b. According to this embodiment, x is input and stored in storage means, followed by an initial process which: reads out x; calculates [x/2]; stores the calculated result as b in the storage means; stores the least significant bit as a in the storage means; reads out a, x and b; calculates [(ax+b)/2]; updates b with the calculated result; reads out x; and stores low-order two bits of x as y in the storage means.

Next, b and y area read out for i=1, 2, . . . , n−1; −by is calculated; a in the storage means is updated with −by; b, a and x are read out of the storage means and are used to calculate [(b+ax)/(2{circumflex over ( )}(2

i

))]; b in the storage means is updated with the calculated value; y and a are read out of the storage means; and are used to calculate y+a×2{circumflex over ( )}(2

i

); and y in the storage means is updated with the calculated value. Note that p{circumflex over ( )}q denotes the q-th power of p.

Next, y is read out of the storage means and output as the result of the inverse calculation.

FIG. 11

depicts the procedure of the inverse calculation described above.

Let a and b be temporary or auxiliary variables, [x] be a Gauss' symbol (the maximum integer not exceeding x) and m=2

n

(n≧1). The inverse calculation is performed as described below. In this case, x, y, a and b have a bit length of m.

Step 1: Input x.

Step 2: Perform the following calculations as initial processing.

2-1. b:=[x/2]

2-2. a:=the least significant bit of b (S2 in

FIG. 11

)

2-3. b:=[(ax+b)/2]

2-4. y:=low-order two bits of x (S3 in

FIG. 11

)

2-5. i:=1(S4 in

FIG. 11

)

Step 3: Perform the following calculations for i=1, 2, . . . , n−1

3-1. a:=−by

3-2. b:=[(b+ax)/(2{circumflex over ( )}(2

i

))]

3-3. y:=y+a×2{circumflex over ( )}(2

i

) (S5 in

FIG. 11

)

3-4. i:=i+1(S6 in

FIG. 11

)

Step 4: Output y.

In Step 2, substeps 2-1, 2-2 and 2-3 are performed in this order. Substeps 2-4 and 2-5 may be performed at arbitrary timing in Step 2.

Step 3 may be performed in the order 3-1→3-2→3-3 or 3-1→3-3→3-2, but on recent computers it is preferable from their data dependency to perform step 3 in the order 3-1→3-2→3-3. When i=n−1, b is not necessary, and hence substep 3-2 need not be carried out.

The loop of the algorithm may be described in a developed from of its interations in advance. (The number of iterations of the loop comes into play only on the order of the logarithm of the bit count of the inverse element to be calculated.) With the loop described in advance, it is possible to make the inverse calculation faster by precalculating i-dependent constants.

On ordinary processors divisions and multiplications by 2

n

can be made faster by shift operations.

The validity of the above inverse calculation algorithm is described in the Appendix to this specification

FIG. 12

illustrates the functional configuration of the inverse calculating apparatus according to this embodiment.

The input data x is stored by an input part

32

C in an x-storage area of a storage device

32

B. The stored data x is read out of the storage device

32

B by first b-initializing means

32

A

1

in an operation device

32

A, wherein it is used to calculate [x/2], which is stored as b in a b-storage area

32

B

4

of the storage device

32

B.

The stored data b is read out by an a-initializing means

32

A

2

from the storage device

32

B, and the least significant bit of the read-out data b is stored in a-storage area

32

B

3

. By second b-initializing means

32

A

3

a, x and b are read out of the storage device

32

B, then [(ax+b)/2] is calculated, and the calculated value is used as b to update the stored content of a b-storage area

32

B

4

.

By y-initializing means

32

A

4

the stored data x in the storage device

32

B is read out therefrom, and its low-order two bits are stored as y in a y-storage area

32

B

2

of the storage device

32

B. By i-initializing means

32

A

51

is set as i in an i-storage area

32

B

5

of the storage device

32

B.

By a-updating means

32

A

6

stored data b and y in the storage device

32

B are read out therefrom, and −by is calculated, with which the stored data a in the a-storage area

32

B

3

is updated. By b-updating means

32

A

7

the stored data a, b, x and i in the storage device

32

B are read out therefrom, and [(b+ax)/2{circumflex over ( )}(2

i

)] is calculated, with which the stored data in the b-storage area

32

B

4

is updated.

By y-updating means

32

A

8

the stored data a, y and i in the storage device

32

B are read out therefrom, and y+ax2{circumflex over ( )}(2

i

) is calculated, with which the stored data y in the y-storage area

32

B

2

is updated. By i-updating means

32

A

9

the stored data i in the storage device

32

B is read out therefrom, and i+1 is calculated, with which the stored data i in the i-storage area

32

B

5

is updated.

By control means

32

A

10

the stored data i and n are read out of the i-storage area

32

B

5

and an n-storage area

32

B

6

of the storage device

32

B, then the a-updating means

32

A

6

, the b-updating means

32

A

7

, the y-updating means

32

A

8

and the i-updating means

32

A

9

are sequentially actuated until, i=n, and when i becomes equal to n, the stored data y in the storage device

32

B is read out therefrom by an output part

32

D and output therethrough.

The apparatus of the present invention is capable of performing its respective functions by a computer under program control.

As will be seen from substeps 3-1, 3-2 and 3-3 of Step 3, this embodiment does not involve the bit padding operation, and hence it reduces the workload of bit processing that has been an obstacle to the software implementation of the Zassenhaus algorithm. Thus this embodiment permits faster inverse calculation in mod 2

m

.

The “Zassenhaus method” and the inverse calculating method of the present invention were implemented on a general purpose workstation by C language and compared in terms of processing speed for n=5 (i.e. 32 bits). The input x was determined generating a random number and the operation was repeated for all x's; the two methods were compared, with OS overhead removed. The comparison showed that the inverse calculating method of the present invention was more than 10% faster than the “Zassenhaus method.”

While Embodiment 2 has been described as being applied to the inverse calculation in the division part

32

of the cipher E2 shown in

FIG. 1

, it is also applicable, for example, to the inverse calculation in mod 2

m

by the Montgomery algorithm that is used in the modular exponentiation operation over Z/NZ

Embodiment 3

This embodiment is intended to reduce the numbers of memory references and additions involved and the storage capacity required in the substitution-permutation processing by the round function part

22

in the cipher E2 depicted in FIG.

2

. In practice, the substitution and permutation of the type indicated by Eq. (17) are not usual and have such properties as listed below in many cases.

(1) Some of pieces of data p

ij

or s

j

are equal.

(2) Even if columns of the input or output are swapped or exchanged, the swap can be accommodated at a different part without decreasing the processing speed, and hence it can be transformed equivalently in terms of algorithm.

(3)The element of R

n

is stored in a register for storing a word that is the calculation unit on a computer, and can be calculated for each element.

Since the property (3) is implemented on recent processors as typified by an MMX instruction implemented on Intel processors, and since R is widely used which permits the element-by-element calculation of R

n

by and AND operation feasible on almost all processors, the property is considered to be a practical assumption.

This embodiment reduces the number of memory references and the storage capacity through utilization of the above-mentioned properties.

That is, according to this embodiment, when some of pieces of data p

ij

or s

j

are equal to one another in the afore-mentioned equations (17) and (18) expressing the substitution and permutation on the ring R

\begin{matrix} [\begin{matrix} y_{1} \\ y_{2} \\ ⋮ \\ y_{m} \end{matrix}] = P [\begin{matrix} s_{1} (x_{1}) \\ s_{2} (x_{2}) \\ ⋮ \\ s_{n} (x_{n}) \end{matrix}] & (17) \end{matrix}

where

\begin{matrix} P = [\begin{matrix} p_{11} & p_{12} & \dots & p_{1 n} \\ p_{21} & p_{22} & \dots & p_{2 n} \\ ⋮ & ⋮ & ⋰ & ⋮ \\ p_{m1} & p_{m2} & \dots & p_{mn} \end{matrix}] p_{ij} \in R, s_{j} : R ⟶ R i = 1, 2, \dots, m j = 1, 2, \dots, n & (18) \end{matrix}

rows of the matrix P expressing the permutation are rearranged, then vector v

1

εR

r

(The dimension r is up to m and the vectors may differ in dimension.) on the ring R and the function S

k

R→R

r

(where k=1, 2, . . . n, r≦m), which are necessary for the substitution and permutation, are precalcuated for each x

i

, and the precalculated values are stored in storage means. For the input x

i

: S

k

is read out of the storage means, and a vector S

k

(x

i

) is calculated; a set of vectors {v

i

} necessary for forming a k-th column of the matrix P is read out of the storage means and a vector u

k

is generated; then u

k

S

k

(x

i

) (where * is the product for each vector element) is calculated, and these values are added together to obtain a data sequence y

i

.

This embodiment will be described below concretely. In practice, the actual substitution and permutation mostly use a field as the ring R, and hence R will be limited specifically to a unitary ring (including the unit element of multiplication). In the interests of simplicity, this embodiment will be described in connection with the case where the calculation of Eq. (17) is P

ij

ε{0, 1} and the pieces of data s

j

are identical. When the data s

j

have several kinds of pieces and some of them are equal, or when the data p

ij

have pieces taking other values than 0 and 1 and some of them are equal, the operation is less efficient than the examples described below but more efficient than in the case of the conventional method set forth in Literature S.

Embodiment 3-1

Consider the case of calculating Eq. (17). When all pieces of data s

j

are the same s, setting

\begin{matrix} v_{j} = [\begin{matrix} p_{1 j} \\ p_{2 j} \\ ⋮ \\ p_{mj} \end{matrix}] j = 1, 2, \dots, n & (32) \\ S : R ⟶ R^{m}; S (x) = [\begin{matrix} s (x) \\ s (x) \\ ⋮ \\ s (x) \end{matrix}] & (33) \end{matrix}

enables Eq. (20) to be written as follows:

\begin{matrix} S P : R ⟶ R^{m}; S P_{j} (x) = [\begin{matrix} p_{1 j} s (x_{j}) \\ p_{2 j} s (x_{j}) \\ ⋮ \\ p_{mj} s (x_{j}) \end{matrix}] = v_{j} * S (x_{j}), j = 1, 2, \dots, n & (34) \end{matrix}

where * is the product for each element of the vector.

From the above it will be understood that, by precalculating S and prestoring the calculated value in a memory, Eq. (17) can be calculated with n memory references for x

l

to x

n

, n multiplications to obtain the product * for each vector element and n−1 additions of n column vectors. The prior art stores SP

l

to SP

n

, but this embodiment stores only S and hence reduces the amount of data stored down to 1/n.

Embodiment 3-2

Consider the case of calculating Eq. (17) in an environment where the calculation unit is smaller than R

[(m+1)/2]

(where [(m+1)/2] is the maximum integer not exceeding (m+1)/2). The following example is applicable to ordinary matrices P. To facilitate a better understanding of the invention, consider the application of the invention to the case of the following matrix (Eq. 35) used in the cipher E2, that is, to the substitution and permutation (Eq. 36).

\begin{matrix} P = [\begin{matrix} 0 & 1 & 1 & 1 & 1 & 1 & 1 & 0 \\ 1 & 0 & 1 & 1 & 0 & 1 & 1 & 1 \\ 1 & 1 & 0 & 1 & 1 & 0 & 1 & 1 \\ 1 & 1 & 1 & 0 & 1 & 1 & 0 & 1 \\ 1 & 1 & 0 & 1 & 1 & 1 & 0 & 0 \\ 1 & 1 & 1 & 0 & 0 & 1 & 1 & 0 \\ 0 & 1 & 1 & 1 & 0 & 0 & 1 & 1 \\ 1 & 0 & 1 & 1 & 1 & 0 & 0 & 1 \end{matrix}] & (35) \\ [\begin{matrix} y_{0} \\ y_{1} \\ y_{2} \\ y_{3} \\ y_{4} \\ y_{5} \\ y_{6} \\ y_{7} \end{matrix}] = [\begin{matrix} 0 & 1 & 1 & 1 & 1 & 1 & 1 & 0 \\ 1 & 0 & 1 & 1 & 0 & 1 & 1 & 1 \\ 1 & 1 & 0 & 1 & 1 & 0 & 1 & 1 \\ 1 & 1 & 1 & 0 & 1 & 1 & 0 & 1 \\ 1 & 1 & 0 & 1 & 1 & 1 & 0 & 0 \\ 1 & 1 & 1 & 0 & 0 & 1 & 1 & 0 \\ 0 & 1 & 1 & 1 & 0 & 0 & 1 & 1 \\ 1 & 0 & 1 & 1 & 1 & 0 & 0 & 1 \end{matrix}] [\begin{matrix} s (x_{0}) \\ s (x_{1}) \\ s (x_{2}) \\ s (x_{3}) \\ s (x_{4}) \\ s (x_{5}) \\ s (x_{6}) \\ s (x_{7}) \end{matrix}] & (36) \end{matrix}

The horizontal line in the matrix of Eq. (36) is intended only to make it easy to see. It should be noted that a substitution with no permutation is also needed at end of the operation in the cipher E2.

To implement the substitution and permutation using the matrix P by the method proposed in Literature S, 4-element column vectors forming the upper half submatrix of P are four kinds vectors each containing a 0, the left-hand four column vectors forming the lower half matrix are also four kinds of vectors each containing a 0, and the right-hand column vectors of the lower: half matrix are four kinds of vectors each containing two 0s. Accordingly, to perform

[\begin{matrix} 0 \\ s (x) \\ s (x) \\ s (x) \end{matrix}], [\begin{matrix} s (x) \\ 0 \\ s (x) \\ s (x) \end{matrix}], [\begin{matrix} s (x) \\ s (x) \\ 0 \\ s (x) \end{matrix}], [\begin{matrix} s (x) \\ s (x) \\ s (x) \\ 0 \end{matrix}], [\begin{matrix} 0 \\ 0 \\ s (x) \\ s (x) \end{matrix}], [\begin{matrix} s (x) \\ 0 \\ 0 \\ s (x) \end{matrix}], [\begin{matrix} s (x) \\ s (x) \\ 0 \\ 0 \end{matrix}], [\begin{matrix} 0 \\ s (x) \\ s (x) \\ 0 \end{matrix}]

and only permutation, the following tables are required.

[\begin{matrix} s (x) \\ 0 \\ 0 \\ 0 \end{matrix}], [\begin{matrix} 0 \\ s (x) \\ 0 \\ 0 \end{matrix}], [\begin{matrix} 0 \\ 0 \\ s (x) \\ 0 \end{matrix}], [\begin{matrix} 0 \\ 0 \\ 0 \\ s (x) \end{matrix}]

In this instance, letting the memory capacity necessary for storing #R (where # represents the number of elements of a set) elements of R

4

be one unit (which definition will hereinafter be applied), the computation cost is as follows:

Required memory capacity: 12

Number of table references: 16

Number of additions: 14

In this embodiment, the order of calculation of Eq. (36) is changed by swapping columns of the matrix P to:

\begin{matrix} [\begin{matrix} y_{0} \\ y_{7} \\ y_{4} \\ y_{3} \\ y_{6} \\ y_{1} \\ y_{2} \\ y_{5} \end{matrix}] = [\begin{matrix} 0 & 1 & 1 & 1 & 1 & 1 & 1 & 0 \\ 1 & 0 & 1 & 1 & 1 & 0 & 0 & 1 \\ 1 & 1 & 0 & 1 & 1 & 1 & 0 & 0 \\ 1 & 1 & 1 & 0 & 1 & 1 & 0 & 1 \\ 0 & 1 & 1 & 1 & 0 & 0 & 1 & 1 \\ 1 & 0 & 1 & 1 & 0 & 1 & 1 & 1 \\ 1 & 1 & 0 & 1 & 1 & 0 & 1 & 1 \\ 1 & 1 & 1 & 0 & 0 & 1 & 1 & 0 \end{matrix}] [\begin{matrix} s (x_{0}) \\ s (x_{1}) \\ s (x_{2}) \\ s (x_{3}) \\ s (x_{4}) \\ s (x_{5}) \\ s (x_{6}) \\ s (x_{7}) \end{matrix}] & (37) \end{matrix}

The vertical and horizontal lines in the above matrix are intended to facilitate a better understanding of the description given below, and they have no particular meanings. As a result, the required table is formed by: four kinds of 4-element column vectors each containing a 0; one kind of 4-element column vector containing two 0s; one kind of 4-element column vector containing only 1s; and two kinds of 4-element column vector each containing only one 1. The column vectors containing one 1 are used for substitution as well as for permutation. Hence, only the following tables need to be stored:

[\begin{matrix} 0 \\ s (x) \\ s (x) \\ s (x) \end{matrix}], [\begin{matrix} s (x) \\ 0 \\ s (x) \\ s (x) \end{matrix}], [\begin{matrix} s (x) \\ s (x) \\ 0 \\ s (x) \end{matrix}], [\begin{matrix} s (x) \\ s (x) \\ s (x) \\ 0 \end{matrix}], [\begin{matrix} 0 \\ s (x) \\ 0 \\ s (x) \end{matrix}], [\begin{matrix} s (x) \\ s (x) \\ s (x) \\ s (x) \end{matrix}], [\begin{matrix} s (x) \\ 0 \\ 0 \\ 0 \end{matrix}], [\begin{matrix} 0 \\ s (x) \\ 0 \\ 0 \end{matrix}], [\begin{matrix} 0 \\ 0 \\ s (x) \\ 0 \end{matrix}], [\begin{matrix} 0 \\ 0 \\ 0 \\ s (x) \end{matrix}]

And the memory reference and addition for x

0

, x

1

, x

2

and x

3

can be made common thereto. Accordingly, the computation cost in this case is as follows:

Required memory capacity: 10

Number of table references: 12

Number of additions: 11

As compared with the method described in Literature S, the method of this embodiment permits reduction of all of the memory capacity, the number of table references and the number of additions. It must be noted here that, the arrangement of y

i

(0≦i≦7) on the left-hand side of Eq. (37) does not impair performance.

Embodiment 3—3

Consider the case of calculating Eq. (17) in an environment where the calculation unit is smaller than R

[(m+1)/2]

as is the case with Embodiment 3-2 and the following shift operation can be performed fast.

\begin{matrix} [\begin{matrix} x_{0} \\ x_{1} \\ x_{2} \\ x_{3} \\ ⋮ \\ ⋮ \\ x_{n} \end{matrix}] ⟶ [\begin{matrix} 0 \\ 0 \\ x_{0} \\ x_{1} \\ ⋮ \\ ⋮ \\ x_{n - 2} \end{matrix}] (Example  of  shift  of low-order  two  elements) & (38) \end{matrix}

As is the case with Embodiment 3-2, this embodiment is also applicable to ordinary matrices P, but for simplicity sake, this example will be described as being applied to the matrix P (see Eq. 35)) and substitution-permutation (see Eq. (36)) used in the cipher E2.

As is the case with Embodiment 3-2, the order of calculation is changed by swapping rows of the matrix P as follows:

\begin{matrix} [\begin{matrix} y_{0} \\ y_{1} \\ y_{3} \\ y_{2} \\ y_{6} \\ y_{7} \\ y_{5} \\ y_{4} \end{matrix}] = [\begin{matrix} 0 & 1 & 1 & 1 & 1 & 1 & 1 & 0 \\ 1 & 0 & 1 & 1 & 0 & 1 & 1 & 1 \\ 1 & 1 & 1 & 0 & 1 & 1 & 0 & 1 \\ 1 & 1 & 0 & 1 & 1 & 0 & 1 & 1 \\ 0 & 1 & 1 & 1 & 0 & 0 & 1 & 1 \\ 1 & 0 & 1 & 1 & 1 & 0 & 0 & 1 \\ 1 & 1 & 1 & 0 & 0 & 1 & 1 & 0 \\ 1 & 1 & 0 & 1 & 1 & 1 & 0 & 0 \end{matrix}] [\begin{matrix} s (x_{0}) \\ s (x_{1}) \\ s (x_{2}) \\ s (x_{3}) \\ s (x_{4}) \\ s (x_{5}) \\ s (x_{6}) \\ s (x_{7}) \end{matrix}] & (39) \end{matrix}

In the processing for x

4

, x

5

, x

6

, x

7

: as regards y

0

, y

1

, y

3

, y

2

, memory-stored reference tables are used intact; and as for y

6

, y

7

, y

5

and y

4

, values read out of the memory-stored reference tables for y

0

, y

1

, y

3

and y

2

are shifted down one element, down two elements, up one element and up two elements, respectively. That is, the leftmost column vector of the upper right submatrix of the matrix P is shifted down one element to obtain the leftmost column vector of the lower right submatrix, then the column vector second from the left-hand side of the upper right submatrix is shifted down two elements to obtain the column vector second from the left-hand side of the lower right submatrix, and thereafter the column vectors third and fourth from the left-hand side of the upper right submatrix are shifted up one element and two elements, respectively, to obtain the column vectors third and fourth from the left-hand side of the lower right submatrix.

Accordingly, all the tables that need to be stored are only such as follows:

S P_{0} (x) = [\begin{matrix} 0 \\ s (x) \\ s (x) \\ s (x) \end{matrix}], S P_{1} (x) = [\begin{matrix} s (x) \\ 0 \\ s (x) \\ s (x) \end{matrix}], S P_{2} (x) = [\begin{matrix} s (x) \\ s (x) \\ 0 \\ s (x) \end{matrix}], S P_{3} (x) = [\begin{matrix} s (x) \\ s (x) \\ s (x) \\ 0 \end{matrix}] [\begin{matrix} s (x) \\ 0 \\ 0 \\ 0 \end{matrix}], [\begin{matrix} 0 \\ s (x) \\ 0 \\ 0 \end{matrix}], [\begin{matrix} 0 \\ 0 \\ s (x) \\ 0 \end{matrix}], [\begin{matrix} 0 \\ 0 \\ 0 \\ s (x) \end{matrix}]

Letting the k-element up-shift operation and the k-element down-shift operation be represented by SU

k

and SD

k

, respectively, and setting

T←SP

0

(

x

0

)+

SP

1

(

x

1

)+

SP

3

(

x

2

)+

SP

2

(

x

3

)

U

0

←SP

1

(

x

4

)

U

1

←SP

3

(

x

5

)

U

2

←SP

2

(

x

6

)

U

3

←SP

0

(

x

7

) (40)

the following calculations can be conducted:

\begin{matrix} [\begin{matrix} y_{0} \\ y_{1} \\ y_{3} \\ y_{2} \end{matrix}] ⟵ T + U_{0} + U_{1} + U_{2} + U_{3} & (41) \\ [\begin{matrix} y_{6} \\ y_{7} \\ y_{5} \\ y_{4} \end{matrix}] ⟵ T + S D_{1} (U_{0}) + S D_{2} (U_{1}) + S U_{1} (U_{2}) + S U_{2} (U_{3}) & (42) \end{matrix}

Accordingly, this embodiment also reduces the computation cost as compared with the method of Literature S in terms of the memory capacity, the number of memory references and the number of additions as follows:

Required memory capacity: 8

Number of table references: 8

Number of additions: 11

Number of shifts: 4

In this embodiment, too, it should be noted that the arrangement of y

i

(0≦i≦7) on the left-hand side does not incur performance degradation.

Embodiment 3-4

This embodiment is also applicable to ordinary matrices P in some cases, but for the sake of simplicity, the embodiment will be described in connection with the case where the matrix P (see Eq. (35)) and substitution and permutation (see Eq. (36)) used in the cipher E2 are defined for a ring R of a characteristic 2.

As is the case with Embodiment 3-3, respective rows of the matrix P are swapped to obtain

\begin{matrix} [\begin{matrix} y_{0} \\ y_{1} \\ y_{2} \\ y_{3} \\ y_{6} \\ y_{7} \\ y_{4} \\ y_{5} \end{matrix}] = [\begin{matrix} 0 & 1 & 1 & 1 & 1 & 1 & 1 & 0 \\ 1 & 0 & 1 & 1 & 0 & 1 & 1 & 1 \\ 1 & 1 & 0 & 1 & 1 & 0 & 1 & 1 \\ 1 & 1 & 1 & 0 & 1 & 1 & 0 & 1 \\ 0 & 1 & 1 & 1 & 0 & 0 & 1 & 1 \\ 1 & 0 & 1 & 1 & 1 & 0 & 0 & 1 \\ 1 & 1 & 0 & 1 & 1 & 1 & 0 & 0 \\ 1 & 1 & 1 & 0 & 0 & 1 & 1 & 0 \end{matrix}] [\begin{matrix} s (x_{0}) \\ s (x_{1}) \\ s (x_{2}) \\ s (x_{3}) \\ s (x_{4}) \\ s (x_{5}) \\ s (x_{6}) \\ s (x_{7}) \end{matrix}] & (43) \end{matrix}

Note the upper right and lower right submatrices of the above matrix.

\begin{matrix} Q_{U} = [\begin{matrix} 1 & 1 & 1 & 0 \\ 0 & 1 & 1 & 1 \\ 1 & 0 & 1 & 1 \\ 1 & 1 & 0 & 1 \end{matrix}], Q_{D} = [\begin{matrix} 0 & 0 & 1 & 1 \\ 1 & 0 & 0 & 1 \\ 1 & 1 & 0 & 0 \\ 0 & 1 & 1 & 0 \end{matrix}] & (44) \end{matrix}

In this instance, the following equation holds:

\begin{matrix} Q_{U} - Q_{D} = [\begin{matrix} 1 & 1 & 0 & 1 \\ 1 & 1 & 1 & 0 \\ 0 & 1 & 1 & 1 \\ 1 & 0 & 1 & 1 \end{matrix}] = S D_{1} (Q_{U}) + S U_{3} (Q_{U}) & (45) \end{matrix}

It must be noted here that a ring of a character 2 is considered as R.

If the following table is prepared in advance as in the case of Embodiment 3—,

S P_{0} (x) = [\begin{matrix} 0 \\ s (x) \\ s (x) \\ s (x) \end{matrix}], S P_{1} (x) = [\begin{matrix} s (x) \\ 0 \\ s (x) \\ s (x) \end{matrix}], S P_{2} (x) = [\begin{matrix} s (x) \\ s (x) \\ 0 \\ s (x) \end{matrix}], S P_{3} (x) = [\begin{matrix} s (x) \\ s (x) \\ s (x) \\ 0 \end{matrix}]

the following calculation can be performed by Eq. (45):

T←SP

0

(

x

0

)+

SP

1

(

x

1

)+

SP hd

2

(

x

2

)+

SP

3

(

x

3

)

U←SP

1

(

x

4

)+

SP

2

(

x

5

)+

SP hd

3

(

x

6

)+

SP

0

(

x

7

)

\begin{matrix} \begin{matrix} [\begin{matrix} y_{0} \\ y_{1} \\ y_{2} \\ y_{3} \end{matrix}] ⟵ T + U \\ [\begin{matrix} y_{6} \\ y_{7} \\ y_{4} \\ y_{5} \end{matrix}] ⟵ [\begin{matrix} y_{0} \\ y_{1} \\ y_{2} \\ y_{3} \end{matrix}] - S D_{1} (U) - S D_{3} (U) \end{matrix} & (46) \end{matrix}

In this case, the computation cost is as follows:

Number of table references (for calculation of SP

j

): 8

Number of additions/subtractions (for calculation of +): 9

Number of shifts (for calculations of SU and SD): 2

Thus, this embodiment permits further reduction of the number of additions/subtractions and the number of shifts than does embodiment 3—3.

Embodiment 3-5

Some processors allow not only the use of the shift operations SU and SD but also the use of the following downward k-element rotation for n elements:

RD

k

(

x

)=

SD

k

(

x

)+SU

n-k

(

x

)

In this instance, by using the downward shift for the calculation of Eq. (46) in Embodiment 3-4, the following equation can be conducted.

\begin{matrix} [\begin{matrix} y_{6} \\ y_{7} \\ y_{4} \\ y_{5} \end{matrix}] ⟵ [\begin{matrix} y_{0} \\ y_{1} \\ y_{2} \\ y_{3} \end{matrix}] - R D_{1} (U) & (47) \end{matrix}

The computation cost in this case is as follows:

Number of table references (for calculation of SP

j

): 8

Number of additions (for ± calculation): 8

Number of rotations (for calculation of RD): 1

This embodiment permits further reduction of the number of additions as compare with that in the case of Embodiment 3-4.

FIG. 13

depicts the functional configuration of Embodiment 3-1. The input data x

i

is stored by input means

32

C in an x

i

-storage area

32

B

13

of a storage device

32

B; the permuted vector v

k

εR

r

is stored in a v

k

-storage area

32

B

14

; and the substitution function S

k

is stored in an S

k

-storage area

32

B

15

. Furthermore, the working vector w

k

is stored in a w

k

-storage area

32

B

16

, and the working parameter k is stored in a k-storage area

32

B

17

. By k-initializing means

32

A

19

in the operation device

32

A k is initialized to 0, and by S

k

-calculating means

32

A

21

the S

k

-storage area

32

B

15

is read out using the input data x

i

, and the calculated value of the vector S

k

(x

i

) is stored as w

k

in the w

k

-storage area

32

B

16

. From the storage means

32

B v

k

and w

k

are read out, and their product for each element is calculated by v

k

*S

k

calculating means

32

A

22

, and the calculated value is used to update w

k

. By k-updating means

32

A

23

k in the k-storage area

32

B

17

is updated by being incremented by 1. The S

k

-calculating means

32

A

21

, the v

k

*S

k

calculating means

32

A

22

and the k-updating means

32

A

23

are actuated one after another until k=n; respective w

k

in the storage means

32

B are read out therefrom, then their sum is calculated, and the calculated value is output via output means

32

D.

FIG. 14

there is depicted the functional configuration of Embodiment 3-2, in which the parts corresponding to those in

FIG. 13

are denoted by the same reference numerals. The v

k

-storage area

32

B

14

and the S

k

-storage area

32

B

1

in

FIG. 13

are substituted with SP

k

-storage area

32

B

31

, in which SP

k

is stored. By SP

k

calculating means

32

A

32

SP

k

(x

i

) is calculated in accordance with the input data x

i

, and the calculated value is stored as the vector w

k

in the w

k

-storage area

32

B

16

. Embodiment 3-2is identical in construction with Embodiment 3-1 except the above.

In Embodiment 3—3, the read-out SP

k

(x

i

) is shifted by shift means

32

A

33

in

FIG. 14

, and the shifted SP

k

(x

i

) is stored as the vector wk in the w

k

-storage area

32

B

16

.

Embodiment 4

With the calculation scheme as defined by Eq. (10), upon each calculation of u

i

′, the calculated value is discarded and the next u

i

′ is calculated by newly conducting an addition and a subtraction. However, since the defining equation for calculating each u

i

, contains two or more components common to those of the defining equation for calculating another u

i

′, that is, since the both defining equations are similar to some extent, it is possible to utilize the previous calculated value by expressing the current value u

i

′ as u

i

′=u

j

′+D

i

using its difference D

i

from the previous calculated value u

j

′. This embodiment is intended to reduce the number of times the memory is read.

Embodiment 4-1

In this embodiment, the value u

i

′ is expressed by u′

i+1

=u′

i

+D

i

and the permutation operation is performed by the following equation:

u

1

′=u

2

+u

3

+u

4

+u

5

+u

6

+u

7

u

2

′=u

1

′+u

1

−u

2

−u

5

+u

8

u

3

′=u

2

′+u

2

−u

3

+u

5

−u

6

u

4

′=u

3

′+u

3

−u

4

+u

6

−u

7

u

5

′=u

4

′−u

3

+u

4

−u

8

u

6

′=u

5

′+u

3

−u

4

−u

5

+u

7

u

7

′=u

6

′−u

1

+u

4

−u

6

+u

8

u

8

′=u

7

′+u

1

−u

2

+u

5

−u

7

(48)

The computation cost by this method is as follows:

Number of additions/subtractions: 32

Number of memory reads: 33

Number of memory writes: 8

As compared with conventional Scheme 1 described previously, this embodiment permits a 25% reduction of the number of memory writes. Incidentally, it must also noted here that since the value u

i

′ is held in an accumulator at the time of calculating u′

i+1

, no memory access for write is needed.

While this embodiment has been described as being applied to permutation using the matrix P in the cipher E2 for the sake of simplicity, this embodiment is not limited specifically to the matrix P but it may be applied to every permutation that is expressed by the matrix composed of elements {0, 1}. General properties of such application are described below.

The conventional Scheme 1 calculates each value u

i

′ (where i=1, 2, . . . , 8) after reading in the required value u

j

(where j=1, 2, 3, . . . , 8). On this account, the total number of memory reads is equal to the total number of “1” components in the matrix P. This means that the larger the total number of “1” components in the matrix P, the larger the number of memory reads and the lower the processing speed.

On the other hand, according to this embodiment, u′

i+1

can be calculated after reading in only u

j

(where j=1, 2, . . . , 8) that is the difference between u′

i+1

and u′

i

. In general, it is expected that the larger the total number of “1” components in the matrix P, the smaller the difference between u′

i+1

and u′

i

. This means that an increase in the total number of “1” components in the matrix P decreases the number of memory reads, providing increased processing speed.

Unlike the conventional Scheme 2, this embodiment is free from limitations on the method of implementing the matrix P, and hence it is versatile. Incidentally, it is not obvious whether the method this embodiment is superior to the conventional Scheme 3 when the total number of “1” components in the matrix P is extremely large.

Embodiment 4-2

Embodiment 4-1 has been described to calculate u′

i

in a sequential order starting first for i=1, but the calculation need not always be conducted in such a sequential order because u′

i

(where i=1, 2, . . . , 8) are described in parallel in the actual implementation. Then the computational complexity, can be reduced by utilizing u′

j

that decrease its difference from u

i

′. For example, the calculation of u

7

′ from u

6

′ requires reading-in of u

1

, u

4

, u

6

and u

8

, but the calculation of u

4

′ after u

6

′ requires reading-in of only u

5

, u

7

and u

8

, and hence it permits reduction of the numbers of memory reads and additions/subtractions by one.

By determining the order of calculation of u′

i

such that the total number of all differences, i.e. the number of memory reads becomes minimum, it is possible to optimize the calculation. Shown below is one of the optimum orders of calculation in the P function part

22

(

FIG. 2

) in the cipher E2.

u

6

′=u

1

+u

2

+u

3

+u

6

+u

7

u

4

′=u

6

′+u

5

−u

7

+u

8

u

5

′=u

4

′−u

3

+u

4

−u

8

u

3

′=u

5

′−u

6

+u

7

+u

8

u

8

′=u

3

′−u

2

+u

3

−u

7

u

2

′=u

8

′−u

5

+u

6

+u

7

u

7

′=u

2

′−u

1

+u

2

−u

6

u

1

′=u

7

′+u

5

+u

6

−u

8

(49)

The computational complexity for permutation by this method is as follows:

Number of additions/subtractions: 25

Number of memory reads: 26

Number of memory writes: 8

Accordingly, the number of memory reads is about 35% smaller than in the case of Scheme 1 and about 25% smaller than in Scheme 2.

While this embodiment has been described as being applied to permutation using the matrix P in the cipher E2 for the sake of simplicity, this embodiment is not limited specifically to the matrix P, and it is evident that the scheme of this embodiment may be applied to every permutation that is expressed by the matrix composed of elements {0, 1}. General properties of such application are described below.

The scheme of this embodiment is apparently improved from the scheme of Embodiment 4-1, and hence it is faster than the conventional Scheme 1 except an address calculation for the write of u

i

′. Besides, unlike the conventional Scheme 2, this embodiment is free from limitations on the method of implementing the matrix P, and hence it is versatile.

On the other hand, when the total number of “1” component in the matrix P is large, it is expected to provide an order of calculation that decreases the difference between u

i

′ and u′

j

as a whole, and in almost all cases it is implemented with the minimum number of memory reads. For example, in the case of Embodiment 4-2, there is such a method that u

j

′ can be derived from u

i

′ by three pieces of u

k

are read out of memories. In general, the number of memory reads necessary for obtaining u

i

′ from σ by the conventional Scheme 3 may be considered to be equal to or larger than the minimum number of memory reads in Embodiment 4-2. It can be safely said, therefore, that this embodiment is smaller, in almost all cases, than Scheme 3 in the total number of memory reads necessary for obtaining all u

i

′ (where i=1, 2,. . . , 8)

FIG. 15

illustrates in block form an apparatus that perform the permutation operation by the scheme of Embodiment 4-1 or 4-2. The pieces of input data u

1

, u

2

, . . . , u

8

to be permuted are held in an input data memory

221

. In a program memory

227

there is stored a program for executing the permutation operation of Eq. (48) or (49). A control device

220

follows the program to control an address generator

226

which generates addresses of pieces of data to be read out of the memory

221

one after another and addresses of an output data memory

222

into which pieces of data obtained by the calculation are written. At the same time, the control device

220

iteratively controls additions/subtractions (or XORing) using an accumulator

224

and registers

225

. Each calculated value u

i

′ is held in a temporary data memory

223

or accumulator

224

until it is used to calculate the next u

j

′.

While Embodiments 4-1 and 4-2 have been described in connection with the permutation operation using a 8 by 8 matrix as the matrix P, it is apparent that they are equally applicable to a permutation operation in which n and m are set at integers equal to or greater than 2, m by n matrix is generally used as the matrix P and permuted data (u

1

′, u

2

′, . . . , u

m

′) is calculated by the following equation.

[\begin{matrix} u_{1}^{'} \\ u_{2}^{'} \\ ⋮ \\ u_{m}^{'} \end{matrix}] = P [\begin{matrix} u_{1} \\ u_{2} \\ ⋮ \\ u_{n} \end{matrix}]

As described above, it is considered that this embodiment is the smallest in the total number of memory reads; in general, the memory read/write is slower than the addition/subtraction, and this embodiment is faster than any conventional schemes by the amount of address calculation included.

Effect of the Invention

As described above, the byte permutation according to the present invention permits reduction of the number of processing steps by simultaneously performing masking operations of 2 bytes. Alternatively, the processing steps can be decreased by the combined use of rotation and shifts.

In the inverse calculation in mod2

m

, the workload can be reduced by performing additive padding instead of using the bit padding in the Zassenhaus scheme.

In the substitution and permutation according to the present invention, the required memory capacity and the computational complexity can be reduced by rearranging rows of the matrix P based on the same components of the permutation matrix P or the same substituted components s

j

(x).

According to the permutation method of the present invention, the computational complexity can be reduced by expressing the current permuted data using the preceding permuted data and the difference between the current and the previous permuted data.

Appendix

Proof of Inverse Algorithm

1. Preparation

Letting C be a natural number and n be a natural number equal to or greater than 1,

C = c_{0} + \sum_{i = 1}^{n} c_{i} 2^{2^{i - 1}}

In the following each variable has a bit size of 2

n

; therefore, mod

2

n

will be omitted unless any particular problems arise. In principle, numbers themselves will be written in uppercase alphabetic characters and individual digits in the development will be in lower-case alphabetic characters (with some exceptions).

Algorithm 1 is shown below:

modinv1(X)

{

a

0

= x

0

−1

mod2;

B

0

= [Xa

0

mod2

2

n

/2];

Y

0

= a

0

;

for(i = 0;i ≦ n − 1;i ++){

β

i

= B

i

mod2

2

i

;

a

i+1

= −β

i

Y

i

mod2

2

i

;

Y

i+1

= Y

1

+ a

i+1

× 2

2

i

;

B

i+1

= [(Xa

i+1

+ B

i

)mod2

2

n−2i

/2

2

i

];

}

return(Y

n

);

}

Proposition 1.1([1]): If input X of Algorithm 1 meets the conditions 0<X<2

2

n

and (X, 2

2

n

)=1, then return value Y

2

will satisfy

XY

n

≡1(mod2

2

n

)

To prove this proposition, the following lemmas will be discussed first.

Lemma 1.1: For i≧0, B

i

=[XY

i

mod2

2

n

/2

2

i

].

Proof. For i=0, the statement is clear. For each k≧0 assume that the following equation holds:

XY

k

=B

k

2

2k

+R

(0

<R<

2

2

k

) (1)

For i=k,

z=[x/y]x=yz+x

mod

y

(2)

is used to obtain

(

Xa

k+1

+B

k

)mod2

2

n

−2

k

=B

k+1

2

2

k

+(

Xa

k+1

+B

k

)mod2

2

k

Multiplying the both sides by 2

2

k

, we have

2

2

k

(

Xa

k+1

+B

k

)mod2

2

n

=B

k+1

2

2

k+1

+2

2

k

(

Xa

k+1

+B

k

)mod2

2

k+1

(3)

It follows from Eq. (1) that

XY

k+1

=X

(

a

k+1

2

2

k

+Y

k

)=2

2

k

(

Xa

k+1

+B

k

)+

R

Substitution of this into Eq.(3) gives

(

XY

k+1

−R

)mod2

2

n

=B

k+1

2

2

k+1

+(

XY

k+1

−R

)mod2

2

k+1

(4)

Since 0<R<2

2

k

, we have

XY

k+1

mod2

2

n

−R=B

k+1

2

2

k+1

+XY

k+1

mod2

2

k+1

−R

and eliminate R from either side. Noting that

(

XY

k+1

mod2

2

n

)mod2

2

k+1

=XY

k+1

mod2

2

k+1

the use of Eq. (2) gives

B_{k + 1} = [\frac{{XY}_{k + 1} \mod 2^{2^{n}}}{2^{2^{k + 1}}}]

(Q.E.D.)

Next, the proposition will be proved.

Proof. It is sufficient to prove that XY

i

=1mod2

2

i

for each i. For i=0. the answer is evident from the algorithm. For each k≧0 assume that the statement is true for i=k. For i=k+1, we have

&AutoLeftMatch; \begin{matrix} {XY}_{k + 1} \mod 2^{2^{k + 1}} = X (a_{k + 1} 2^{2^{k}} + Y_{k}) \mod 2^{2^{k + 1}} \\ = (X (- β_{k} Y_{k} \mod 2^{2^{k}}) 2^{2^{k}} + Y_{k}) \mod 2^{2^{k + 1}} \\ = (- X β_{k} Y_{k} \mod 2^{2^{k}}) 2^{2^{k}} + {XY}_{k} \mod 2^{2^{k + 1}} \end{matrix}

We have XY

k

=1mod2

2

k

using the induction hypothesis, and (B

k

mod2

2

k

)2

2

k

=β

k

2

2

k

using B

k

[XY

k

mod2

2

n

/2

2

k

] from the lemma. Therefore, XY

k

mod2

2

k+1

=β

k

2

2

k

+1 holds. Finally we obtain

&AutoLeftMatch; \begin{matrix} {XY}_{k + 1} \mod 2^{2^{k + 1}} = (- X β_{k} Y_{k} \mod 2^{2^{k}}) 2^{2^{k}} + β_{k} 2^{2^{k}} + 1 \\ = ((β_{k} (1 - {XY}_{k})) \mod 2^{2^{k}}) 2^{2^{k}} + 1 \\ = ((β_{k} (1 - 1)) \mod 2^{2^{k}}) 2^{2^{k}} + 1 \\ = 1 \end{matrix}

2. Algorithm 2

Algorithm 2 is shown below:

modinv2(X)

{

B

0

= [X/2];

A

1

= B

0

& 1;

B

1

= [(XA

1

+ B

0

)/2];

Y

1

= B

1

& 3;

for(i = 1;i ≦ n − 1:i ++){

A

i+1

= −B

i

Y

i

;

B

i+1

= [(XA

i+1

+ B

i

)/2

2

i

];

Y

i+1

= Y

i

+ A

i+1

× 2

2

i

:

}

return(Y

n

);

}

Theorem 2.1: If the input X of algorithm 2 meets the condition0<X<2

2

n

and (X, 2

2

n

)=1, return value Y

n

will satisfy:

XY

n

≡1(mod2

2

n

)

Proof. Algorithm 2 is a modified version of Algorithm 1, and several modular arithmetics are omitted. Accordingly, the value of each variable of the algorithm is free from modular arithmetic, and hence it has some value (garbage) added to the value in Algorithm 1. The value in Algorithm 1, for example, the variable X will hereinafter be described as X

(0)

. For instance, Y

2

in Algorithm 1 is denoted by Y

2

(0)

, and the garbage is denoted by C and expressed by Y

2

=Y

2

(0)

+C. Note that the discussion on Algorithm 1 holds if every variable is described as X

(0)

.

For i≧1, it will be proved by induction that the following mathematical expressions hold in Algorithm 2:

C

i

=0mod2

2

i−1

(5)

\begin{matrix} B_{i} = B_{i}^{(0)} + X \times \frac{C_{i}}{2^{2^{i - 1}}} & (6) \end{matrix}

Y

i

=Y

i

(0)

+C

i

×2

2

i−1

(7)

Each C

i

is the afore-mentioned “garbage,” which is at least a multiple of 2

2

i−1

. B

i

and Y

i

have added thereto C

i

in the above form.

When i=1, each of A

1

, B

1

, Y

1

is a processing equivalent to Algorithm 1, and hence no “garbage” exists. Accordingly, C

1

=0, and Eqs. (5), (6) and (7) hold.

For each k≧1 assume that Eqs. (5), (6) and (7) hold for i=k. For i=k+1, we will show that Y

k+1

satisfies Eq. (7). To begin with,

A

k+1

=−B

k

Y

k

is calculated. As the calculation continues, we have

&AutoLeftMatch; \begin{matrix} A_{k + 1} = - (B_{k}^{(0)} + \frac{{XC}_{k}}{2^{2^{k - 1}}}) (Y_{k}^{(0)} + C_{k} \times 2^{2^{k - 1}}) \\ = - B_{k}^{(0)} Y_{k}^{(0)} - \frac{Y_{k}^{(0)} {XC}_{k}}{2^{2^{k - 1}}} - B_{k}^{(0)} C_{k} \times 2^{2^{k - 1}} - {XC}_{k} C_{k} \\ = a_{k + 1}^{(0)} + D_{k + 1} - \frac{Y_{k}^{(0)} {XC}_{k}}{2^{2^{k - 1}}} - B_{k}^{(0)} C_{k} \times 2^{2^{k - 1}} - {XC}_{k} C_{k} \end{matrix}

From Algorithm 1,

a

k+1

(0)

=−β

k

Y

k

mod2

2

k

=−B

k

Y

k

mod2

2

k

and

D

k+1

=[B

k

Y

k

/2

2

k

]×2

2

k

That is, low-order 2

k

bit portion of −B

k

Y

k

is expressed by a

k+1

(0)

, and the high order is expressed by D

k+1

. Note that D

k+1

is D

k+1

=0 mod 2

2

k

like C

k

. From the above, we have

&AutoLeftMatch; \begin{matrix} Y_{k + 1} = Y_{k} + A_{k + 1} \times 2^{2^{k}} \\ = Y_{k}^{(0)} + C_{k} \times 2^{2^{k - 1}} + \\ (a_{k + 1}^{(0)} + D_{k + 1} - \frac{Y_{k}^{(0)} {XC}_{k}}{2^{2^{k - 1}}} - B_{k}^{(0)} C_{k} \times 2^{2^{k - 1}} - {XC}_{k} C_{k}) \times 2^{2^{k}} \\ = Y_{k}^{(0)} + a_{k + 1}^{(0)} \times 2^{2^{k}} + \\ (\frac{C_{k}}{2^{2^{k - 1}}} + D_{k + 1} - \frac{Y_{k}^{(0)} {XC}_{k}}{2^{2^{k - 1}}} - B_{k}^{(0)} C_{k} \times 2^{2^{k - 1}} - {XC}_{k} C_{k}) \times 2^{2^{k}} \\ = Y_{k + 1}^{(0)} + \\ (\frac{C_{k}}{2^{2^{k - 1}}} + D_{k + 1} - \frac{Y_{k}^{(0)} {XC}_{k}}{2^{2^{k - 1}}} - B_{k}^{(0)} C_{k} \times 2^{2^{k - 1}} - {XC}_{k} C_{k}) \times 2^{2^{k}} \end{matrix}

Now, set

C_{k + 1} = (\frac{C_{k}}{2^{2^{k - 1}}} + D_{k + 1} - \frac{Y_{k}^{(0)} {XC}_{k}}{2^{2^{k - 1}}} - B_{k}^{(0)} C_{k} \times 2^{2^{k - 1}} - {XC}_{k} C_{k}) \mod 2^{2^{n} - 2^{k}}

Since each of individual variables has a bit size of 2

n

and since the second term on the right-hand side of the above has been multiplied by 2

2

k

, we see that even if C

k+1

is calculated under modulo 2

2

n

−2

k

, the following equation holds:

Y

k+1

=Y

k+1

(0)

+C

k+1

×2

2

k

(8)

Next we will show that C

k+1

satisfies Eq. (5), that C

k+1

satisfied Eq. (5), that is, C

k+1

is a multiple of 2

2

k

. Since C

k

=0 mod 2

2

k−1

, it is clear that XC

k

C

k

=0 mod 2

2

k

and that B

k

(0)

C

k

×2

2

k−i

=0 mod 2

2

k

. And, as mentioned previously, D

k+1

=0 mod 2

2

k

. Now,

\frac{C_{k}}{2^{2^{k - 1}}} - \frac{Y_{k}^{(0)} {XC}_{k}}{2^{2^{k - 1}}} = \frac{C_{k}}{2^{2^{k - 1}}} (1 - Y_{k}^{(0)} X)

but since XY

k

(0)

=1 mod 2

2

k

from the lemma, we have

(1−

Y

k

(0)

X

)=0mod2

2

k

Using C

k

=0mod2

2

k−1

, we have

\frac{C_{k}}{2^{2^{k - 1}}} (1 - Y_{k}^{(0)} X) = 0 \mod 2^{2^{k}} .

Thus it is proved that

C

k+1

=0 mod 2

2

k

(9)

From the above we find that Eqs. (5) and (7) hold also when i=k+1. If it is shown using this C

k+1

that when i=k+1, B

k+1

satisfies Eq. (6), then the theorem will be proved. Now, from Algorithm 2, B

k+1

becomes as follows:

B

k+1

=[(

XA

k+1

+B

k

)/2

2

k

]

Using Eq. (2) the above equation can be modified as follows:

XA

k+1

B

k

=B

k+1

×2

2

k

+(

XA

k+1

+B

k

)mod2

2

k

Since the bit size of each variable is 2

n

, and since B

k+1

is multiplied by 2

2

k

, there exist no problem even if the both sides are calculated under modulo 2

2

n

−2

k

. Accordingly, we have

(

XA

k+1

B

k

)mod2

2

n

−2

k

B

k+1

×2

2

k

+(

XA

k+1

+B

k

)mod2

2

k

(10)

Then we have

\begin{matrix} {XA}_{k + 1} + B_{k} = X (a_{k + 1}^{(0)} + D_{k + 1} - \frac{Y_{k}^{(0)} {XC}_{k}}{2^{2^{k - 1}}} - B_{k}^{(0)} C_{k} \times 2^{2^{k - 1}} - {XC}_{k} C_{k}) + \\ B_{k}^{(0)} + X \times \frac{C_{k}}{2^{2^{k - 1}}} \\ = {Xa}_{k + 1}^{(0)} + B_{k}^{(0)} + \\ X (\frac{C_{k}}{2^{2^{k - 1}}} + D_{k + 1} - \frac{Y_{k}^{(0)} {XC}_{k}}{2^{2^{k - 1}}} - B_{k}^{(0)} C_{k} \times 2^{2^{k - 1}} - {XC}_{k} C_{k}) \end{matrix}

Hence the left-hand side of Eq. (10) becomes as follows:

(

XA

k+1

+B

k

)mod2

2

n

−2

k

=(

Xa

k+1

(0)

+B

k

(0)

)mod2

2

n

−2

k

+XC

k+1

Furthermore, using Eq. (9), the second term on the right-hand side of Eq. (10) becomes as follows:

\begin{matrix} ({XA}_{k + 1} + B_{k}) \mod 2^{2^{k}} = ({Xa}_{k + 1}^{(0)} + B_{k}^{(0)} + C_{k + 1}) \mod 2^{2^{k}} \\ = ({Xa}_{k + 1}^{(0)} + B_{k}^{(0)}) \mod 2^{2^{k}} \end{matrix}

Therefore, we have

Xa

k+1

(0)

+B

k

(0)

)mod2

2

n

−2

k

+XC

k+1

=B

k+1

×2

2

k

+(

Xa

k+1

(0)

+B

k

(0)

)mod2

2

k

and

({Xa}_{k + 1}^{(0)} + B_{k}^{(0)}) \mod 2^{2^{n} - 2^{k}} = (B_{k + 1} - X \frac{C_{k + 1}}{2^{2^{k}}}) \times 2^{2^{k}} + ({Xa}_{k + 1}^{(0)} + B_{k}^{(0)}) \mod 2^{2^{k}}

And the following equation holds:

B_{k + 1} - X \frac{C_{k + 1}}{2^{2^{k}}} = [({Xa}_{k + 1}^{(0)} + B_{k}^{(0)}) \mod 2^{2^{n} - 2^{k}} / 2^{2^{k}}] = B_{k + 1}^{(0)}

Thus the following is proved:

\begin{matrix} B_{k + 1} = B_{k + 1}^{(0)} + X \frac{C_{k + 1}}{2^{2^{k}}} & (11) \end{matrix}

From the above, Eqs. (5), (6) and (7) hold also when i=k+1.

For i=n, since the “garbage” C

n

×2

2

n

becomes a multiple of 2

2

k

,and each variables has a bit size of 2

2n

, we obtain Y

n

=Y

n

(0)

; from the proposition

XY

n

=1mod2

2

n

holds. Thus the proposition is proved. (Q.E.D.)

Reference

[1] Kawamura, “New algorithms for inverse module a prime power,” SCIS'97-14C.

Number	Date	Country
11-010788	Jan 1999	JP
11-015525	Jan 1999	JP
11-016238	Jan 1999	JP
11-071255	Mar 1999	JP

Number	Name	Date	Kind
5539827	Liu	Jul 1996	A
5687238	Shimada	Nov 1997	A
5825886	Adams et al.	Oct 1998	A
6298136	Den Boer	Oct 2001	B1
6408075	Ohki et al.	Jun 2002	B1

Number	Date	Country
60-167062	Aug 1985	JP
11-071255	Mar 1999	JP

Method and apparatus for data permutation/division and recording medium with data permutation/division program recorded thereon

Information

Patent Number

Date Filed

Date Issued

Inventors

Original Assignees

Examiners

Agents

CPC

US Classifications

Field of Search

US

International Classifications

Abstract

Description

Claims

Priority Claims (4)

US Referenced Citations (5)

Foreign Referenced Citations (2)

Non-Patent Literature Citations (7)

Entry
The Cipher SHARK, Lecture Notes in Computer Science, Vincent Rijmen et al., vol. 1039, p. 99-111, Undated.
Kanda, Masayuki, et al., “A New 128-bit Block Cipher E2”, Technical Report of IEICE, The Institute of Electronics, Information and Communication Engineers, Jul. 1998.
Aoki, Kazumaro, et al., “Optimized Softwave Implementation of E2,” Presented at the AES, pp. 1-11, Undated.
Aoki, Kazumaro, et al., “Software Implementations for E2,” Proceedings of the 1999 Symposium on Crytography and Information Security, vol. 2, Jan. 26-29, 1999, pp. 801-806.
Schneiter, Bruce, Applied Crytography, 2nd Edition, John Wiley & Sons, Chapters 12.4-12.5, 14.10, and 15.5-15-6, pp. 285-293, 347, and 366-367, Undated.
Hans Zassenhaus, “On Hensel Factorization, I,” Journal of Number Theory, vol. 1, pp. 291-311, 1969.
Rijimen, Vincent, et al., “The Cipher SHARK,” Fast Software Encryption, Dieter Gollmann, Ed., Springer, pp. 99-110, Undated.