Patent Application
20250004772
This invention relates generally to the field of computer processors. More particularly, the invention relates to a method and apparatus for decompression hardware copy engine with efficient sequence overlapping copy.
An instruction set, or instruction set architecture (ISA), is the part of the computer architecture related to programming, including the native data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I/O). It should be noted that the term “instruction” generally refers herein to macro-instructions—that is instructions that are provided to the processor for execution—as opposed to micro-instructions or micro-ops—that is the result of a processor's decoder decoding macro-instructions. The micro-instructions or micro-ops can be configured to instruct an execution unit on the processor to perform operations to implement the logic associated with the macro-instruction.
The ISA is distinguished from the microarchitecture, which is the set of processor design techniques used to implement the instruction set. Processors with different microarchitectures can share a common instruction set. For example, Intel® Pentium 4 processors, Intel® Core™ processors, and processors from Advanced Micro Devices, Inc. of Sunnyvale CA implement nearly identical versions of the x86 instruction set (with some extensions that have been added with newer versions), but have different internal designs. For example, the same register architecture of the ISA may be implemented in different ways in different microarchitectures using well-known techniques, including dedicated physical registers, one or more dynamically allocated physical registers using a register renaming mechanism (e.g., the use of a Register Alias Table (RAT), a Reorder Buffer (ROB) and a retirement register file). Unless otherwise specified, the phrases register architecture, register file, and register are used herein to refer to that which is visible to the software/programmer and the manner in which instructions specify registers. Where a distinction is required, the adjective “logical,” “architectural,” or “software visible” will be used to indicate registers/files in the register architecture, while different adjectives will be used to designate registers in a given microarchitecture (e.g., physical register, reorder buffer, retirement register, register pool).
A better understanding of the present invention can be obtained from the following detailed description in conjunction with the following drawings, in which:
A better understanding of the present invention can be obtained from the following detailed description in conjunction with the following drawings, in which:
In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the invention described below. It will be apparent, however, to one skilled in the art that the embodiments of the invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form to avoid obscuring the underlying principles of the embodiments of the invention.
Detailed below are describes of exemplary computer architectures. Other system designs and configurations known in the arts for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, micro controllers, cell phones, portable media players, hand held devices, and various other electronic devices, are also suitable. In general, a huge variety of systems or electronic devices capable of incorporating a processor and/or other execution logic as disclosed herein are generally suitable.
Processors 170 and 180 are shown including integrated memory controller (IMC) units circuitry 172 and 182, respectively. Processor 170 also includes as part of its interconnect controller units point-to-point (P-P) interfaces 176 and 178; similarly, second processor 180 includes P-P interfaces 186 and 188. Processors 170, 180 may exchange information via the point-to-point (P-P) interconnect 150 using P-P interface circuits 178, 188. IMCs 172 and 182 couple the processors 170, 180 to respective memories, namely a memory 132 and a memory 134, which may be portions of main memory locally attached to the respective processors.
Processors 170, 180 may each exchange information with a chipset 190 via individual P-P interconnects 152, 154 using point to point interface circuits 176, 194, 186, 198. Chipset 190 may optionally exchange information with a coprocessor 138 via a high-performance interface 192. In some embodiments, the coprocessor 138 is a special-purpose processor, such as, for example, a high-throughput MIC processor, a network or communication processor, compression engine, graphics processor, GPGPU, embedded processor, or the like.
A shared cache (not shown) may be included in either processor 170, 180 or outside of both processors, yet connected with the processors via P-P interconnect, such that either or both processors' local cache information may be stored in the shared cache if a processor is placed into a low power mode.
Chipset 190 may be coupled to a first interconnect 116 via an interface 196. In some embodiments, first interconnect 116 may be a Peripheral Component Interconnect (PCI) interconnect, or an interconnect such as a PCI Express interconnect or another I/O interconnect. In some embodiments, one of the interconnects couples to a power control unit (PCU) 117, which may include circuitry, software, and/or firmware to perform power management operations with regard to the processors 170, 180 and/or co-processor 138. PCU 117 provides control information to a voltage regulator to cause the voltage regulator to generate the appropriate regulated voltage. PCU 117 also provides control information to control the operating voltage generated. In various embodiments, PCU 117 may include a variety of power management logic units (circuitry) to perform hardware-based power management. Such power management may be wholly processor controlled (e.g., by various processor hardware, and which may be triggered by workload and/or power, thermal or other processor constraints) and/or the power management may be performed responsive to external sources (such as a platform or power management source or system software).
PCU 117 is illustrated as being present as logic separate from the processor 170 and/or processor 180. In other cases, PCU 117 may execute on a given one or more of cores (not shown) of processor 170 or 180. In some cases, PCU 117 may be implemented as a microcontroller (dedicated or general-purpose) or other control logic configured to execute its own dedicated power management code, sometimes referred to as P-code. In yet other embodiments, power management operations to be performed by PCU 117 may be implemented externally to a processor, such as by way of a separate power management integrated circuit (PMIC) or another component external to the processor. In yet other embodiments, power management operations to be performed by PCU 117 may be implemented within BIOS or other system software.
Various I/O devices 114 may be coupled to first interconnect 116, along with an interconnect (bus) bridge 118 which couples first interconnect 116 to a second interconnect 120. In some embodiments, one or more additional processor(s) 115, such as coprocessors, high-throughput MIC processors, GPGPU's, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays (FPGAs), or any other processor, are coupled to first interconnect 116. In some embodiments, second interconnect 120 may be a low pin count (LPC) interconnect. Various devices may be coupled to second interconnect 120 including, for example, a keyboard and/or mouse 122, communication devices 127 and a storage unit circuitry 128. Storage unit circuitry 128 may be a disk drive or other mass storage device which may include instructions/code and data 130, in some embodiments. Further, an audio I/O 124 may be coupled to second interconnect 120. Note that other architectures than the point-to-point architecture described above are possible. For example, instead of the point-to-point architecture, a system such as multiprocessor system 100 may implement a multi-drop interconnect or other such architecture.
Processor cores may be implemented in different ways, for different purposes, and in different processors. For instance, implementations of such cores may include: 1) a general purpose in-order core intended for general-purpose computing; 2) a high performance general purpose out-of-order core intended for general-purpose computing; 3) a special purpose core intended primarily for graphics and/or scientific (throughput) computing. Implementations of different processors may include: 1) a CPU including one or more general purpose in-order cores intended for general-purpose computing and/or one or more general purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor including one or more special purpose cores intended primarily for graphics and/or scientific (throughput). Such different processors lead to different computer system architectures, which may include: 1) the coprocessor on a separate chip from the CPU; 2) the coprocessor on a separate die in the same package as a CPU; 3) the coprocessor on the same die as a CPU (in which case, such a coprocessor is sometimes referred to as special purpose logic, such as integrated graphics and/or scientific (throughput) logic, or as special purpose cores); and 4) a system on a chip that may include on the same die as the described CPU (sometimes referred to as the application core(s) or application processor(s)), the above described coprocessor, and additional functionality. Exemplary core architectures are described next, followed by descriptions of exemplary processors and computer architectures.
Thus, different implementations of the processor 200 may include: 1) a CPU with the special purpose logic 208 being integrated graphics and/or scientific (throughput) logic (which may include one or more cores, not shown), and the cores 202(A)-(N) being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, or a combination of the two); 2) a coprocessor with the cores 202(A)-(N) being a large number of special purpose cores intended primarily for graphics and/or scientific (throughput); and 3) a coprocessor with the cores 202(A)-(N) being a large number of general purpose in-order cores. Thus, the processor 200 may be a general-purpose processor, coprocessor or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit circuitry), a high-throughput many integrated core (MIC) coprocessor (including 30 or more cores), embedded processor, or the like. The processor may be implemented on one or more chips. The processor 200 may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BICMOS, CMOS, or NMOS.
A memory hierarchy includes one or more levels of cache unit(s) circuitry 204(A)-(N) within the cores 202(A)-(N), a set of one or more shared cache units circuitry 206, and external memory (not shown) coupled to the set of integrated memory controller units circuitry 214. The set of one or more shared cache units circuitry 206 may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, such as a last level cache (LLC), and/or combinations thereof. While in some embodiments ring-based interconnect network circuitry 212 interconnects the special purpose logic 208 (e.g., integrated graphics logic), the set of shared cache units circuitry 206, and the system agent unit circuitry 210, alternative embodiments use any number of well-known techniques for interconnecting such units. In some embodiments, coherency is maintained between one or more of the shared cache units circuitry 206 and cores 202(A)-(N).
In some embodiments, one or more of the cores 202(A)-(N) are capable of multi-threading. The system agent unit circuitry 210 includes those components coordinating and operating cores 202(A)-(N). The system agent unit circuitry 210 may include, for example, power control unit (PCU) circuitry and/or display unit circuitry (not shown). The PCU may be or may include logic and components needed for regulating the power state of the cores 202(A)-(N) and/or the special purpose logic 208 (e.g., integrated graphics logic). The display unit circuitry is for driving one or more externally connected displays.
The cores 202(A)-(N) may be homogenous or heterogeneous in terms of architecture instruction set; that is, two or more of the cores 202(A)-(N) may be capable of executing the same instruction set, while other cores may be capable of executing only a subset of that instruction set or a different instruction set.
In
By way of example, the exemplary register renaming, out-of-order issue/execution core architecture may implement the pipeline 300 as follows: 1) the instruction fetch 338 performs the fetch and length decoding stages 302 and 304; 2) the decode unit circuitry 340 performs the decode stage 306; 3) the rename/allocator unit circuitry 352 performs the allocation stage 308 and renaming stage 310; 4) the scheduler unit(s) circuitry 356 performs the schedule stage 312; 5) the physical register file(s) unit(s) circuitry 358 and the memory unit circuitry 370 perform the register read/memory read stage 314; the execution cluster 360 perform the execute stage 316; 6) the memory unit circuitry 370 and the physical register file(s) unit(s) circuitry 358 perform the write back/memory write stage 318; 7) various units (unit circuitry) may be involved in the exception handling stage 322; and 8) the retirement unit circuitry 354 and the physical register file(s) unit(s) circuitry 358 perform the commit stage 324.
The front end unit circuitry 330 may include branch prediction unit circuitry 332 coupled to an instruction cache unit circuitry 334, which is coupled to an instruction translation lookaside buffer (TLB) 336, which is coupled to instruction fetch unit circuitry 338, which is coupled to decode unit circuitry 340. In one embodiment, the instruction cache unit circuitry 334 is included in the memory unit circuitry 370 rather than the front-end unit circuitry 330. The decode unit circuitry 340 (or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decode unit circuitry 340 may further include an address generation unit circuitry (AGU, not shown). In one embodiment, the AGU generates an LSU address using forwarded register ports, and may further perform branch forwarding (e.g., immediate offset branch forwarding, LR register branch forwarding, etc.). The decode unit circuitry 340 may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. In one embodiment, the core 390 includes a microcode ROM (not shown) or other medium that stores microcode for certain macroinstructions (e.g., in decode unit circuitry 340 or otherwise within the front end unit circuitry 330). In one embodiment, the decode unit circuitry 340 includes a micro-operation (micro-op) or operation cache (not shown) to hold/cache decoded operations, micro-tags, or micro-operations generated during the decode or other stages of the processor pipeline 300. The decode unit circuitry 340 may be coupled to rename/allocator unit circuitry 352 in the execution engine unit circuitry 350.
The execution engine circuitry 350 includes the rename/allocator unit circuitry 352 coupled to a retirement unit circuitry 354 and a set of one or more scheduler(s) circuitry 356. The scheduler(s) circuitry 356 represents any number of different schedulers, including reservations stations, central instruction window, etc. In some embodiments, the scheduler(s) circuitry 356 can include arithmetic logic unit (ALU) scheduler/scheduling circuitry, ALU queues, arithmetic generation unit (AGU) scheduler/scheduling circuitry, AGU queues, etc. The scheduler(s) circuitry 356 is coupled to the physical register file(s) circuitry 358. Each of the physical register file(s) circuitry 358 represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating-point, packed integer, packed floating-point, vector integer, vector floating-point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one embodiment, the physical register file(s) unit circuitry 358 includes vector registers unit circuitry, writemask registers unit circuitry, and scalar register unit circuitry. These register units may provide architectural vector registers, vector mask registers, general-purpose registers, etc. The physical register file(s) unit(s) circuitry 358 is overlapped by the retirement unit circuitry 354 (also known as a retire queue or a retirement queue) to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) (ROB(s)) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit circuitry 354 and the physical register file(s) circuitry 358 are coupled to the execution cluster(s) 360. The execution cluster(s) 360 includes a set of one or more execution units circuitry 362 and a set of one or more memory access circuitry 364. The execution units circuitry 362 may perform various arithmetic, logic, floating-point or other types of operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating-point, packed integer, packed floating-point, vector integer, vector floating-point). While some embodiments may include a number of execution units or execution unit circuitry dedicated to specific functions or sets of functions, other embodiments may include only one execution unit circuitry or multiple execution units/execution unit circuitry that all perform all functions. The scheduler(s) circuitry 356, physical register file(s) unit(s) circuitry 358, and execution cluster(s) 360 are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating-point/packed integer/packed floating-point/vector integer/vector floating-point pipeline, and/or a memory access pipeline that each have their own scheduler circuitry, physical register file(s) unit circuitry, and/or execution cluster- and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s) circuitry 364). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.
In some embodiments, the execution engine unit circuitry 350 may perform load store unit (LSU) address/data pipelining to an Advanced Microcontroller Bus (AHB) interface (not shown), and address phase and writeback, data phase load, store, and branches.
The set of memory access circuitry 364 is coupled to the memory unit circuitry 370, which includes data TLB unit circuitry 372 coupled to a data cache circuitry 374 coupled to a level 2 (L2) cache circuitry 376. In one exemplary embodiment, the memory access units circuitry 364 may include a load unit circuitry, a store address unit circuit, and a store data unit circuitry, each of which is coupled to the data TLB circuitry 372 in the memory unit circuitry 370. The instruction cache circuitry 334 is further coupled to a level 2 (L2) cache unit circuitry 376 in the memory unit circuitry 370. In one embodiment, the instruction cache 334 and the data cache 374 are combined into a single instruction and data cache (not shown) in L2 cache unit circuitry 376, a level 3 (L3) cache unit circuitry (not shown), and/or main memory. The L2 cache unit circuitry 376 is coupled to one or more other levels of cache and eventually to a main memory.
The core 390 may support one or more instructions sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set; the ARM instruction set (with optional additional extensions such as NEON)), including the instruction(s) described herein. In one embodiment, the core 390 includes logic to support a packed data instruction set extension (e.g., AVX1, AVX2), thereby allowing the operations used by many multimedia applications to be performed using packed data.
In some embodiments, the register architecture 500 includes writemask/predicate registers 515. For example, in some embodiments, there are 8 writemask/predicate registers (sometimes called k0 through k7) that are each 16-bit, 32-bit, 64-bit, or 128-bit in size. Writemask/predicate registers 515 may allow for merging (e.g., allowing any set of elements in the destination to be protected from updates during the execution of any operation) and/or zeroing (e.g., zeroing vector masks allow any set of elements in the destination to be zeroed during the execution of any operation). In some embodiments, each data element position in a given writemask/predicate register 515 corresponds to a data element position of the destination. In other embodiments, the writemask/predicate registers 515 are scalable and consists of a set number of enable bits for a given vector element (e.g., 8 enable bits per 64-bit vector element).
The register architecture 500 includes a plurality of general-purpose registers 525. These registers may be 16-bit, 32-bit, 64-bit, etc. and can be used for scalar operations. In some embodiments, these registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.
In some embodiments, the register architecture 500 includes scalar floating-point register 545 which is used for scalar floating-point operations on 32/64/80-bit floating-point data using the x87 instruction set extension or as MMX registers to perform operations on 64-bit packed integer data, as well as to hold operands for some operations performed between the MMX and XMM registers.
One or more flag registers 540 (e.g., EFLAGS, RFLAGS, etc.) store status and control information for arithmetic, compare, and system operations. For example, the one or more flag registers 540 may store condition code information such as carry, parity, auxiliary carry, zero, sign, and overflow. In some embodiments, the one or more flag registers 540 are called program status and control registers.
Segment registers 520 contain segment points for use in accessing memory. In some embodiments, these registers are referenced by the names CS, DS, SS, ES, FS, and GS.
Machine specific registers (MSRs) 535 control and report on processor performance. Most MSRs 535 handle system-related functions and are not accessible to an application program. Machine check registers 560 consist of control, status, and error reporting MSRs that are used to detect and report on hardware errors.
One or more instruction pointer register(s) 530 store an instruction pointer value. Control register(s) 555 (e.g., CR0-CR4) determine the operating mode of a processor (e.g., processor 170, 180, 138, 115, and/or 200) and the characteristics of a currently executing task. Debug registers 550 control and allow for the monitoring of a processor or core's debugging operations.
Memory management registers 565 specify the locations of data structures used in protected mode memory management. These registers may include a GDTR, IDRT, task register, and a LDTR register.
Alternative embodiments of the invention may use wider or narrower registers. Additionally, alternative embodiments of the invention may use more, less, or different register files and registers.
An instruction set architecture (ISA) may include one or more instruction formats. A given instruction format may define various fields (e.g., number of bits, location of bits) to specify, among other things, the operation to be performed (e.g., opcode) and the operand(s) on which that operation is to be performed and/or other data field(s) (e.g., mask). Some instruction formats are further broken down though the definition of instruction templates (or sub-formats). For example, the instruction templates of a given instruction format may be defined to have different subsets of the instruction format's fields (the included fields are typically in the same order, but at least some have different bit positions because there are less fields included) and/or defined to have a given field interpreted differently. Thus, each instruction of an ISA is expressed using a given instruction format (and, if defined, in a given one of the instruction templates of that instruction format) and includes fields for specifying the operation and the operands. For example, an exemplary ADD instruction has a specific opcode and an instruction format that includes an opcode field to specify that opcode and operand fields to select operands (source1/destination and source2); and an occurrence of this ADD instruction in an instruction stream will have specific contents in the operand fields that select specific operands.
Embodiments of the instruction(s) described herein may be embodied in different formats. Additionally, exemplary systems, architectures, and pipelines are detailed below. Embodiments of the instruction(s) may be executed on such systems, architectures, and pipelines, but are not limited to those detailed.
The prefix(es) field(s) 601, when used, modifies an instruction. In some embodiments, one or more prefixes are used to repeat string instructions (e.g., 0xF0, 0xF2, 0xF3, etc.), to provide section overrides (e.g., 0x2E, 0x36, 0x3E, 0x26, 0x64, 0x65, 0x2E, 0x3E, etc.), to perform bus lock operations, and/or to change operand (e.g., 0x66) and address sizes (e.g., 0x67). Certain instructions require a mandatory prefix (e.g., 0x66, 0xF2, 0xF3, etc.). Certain of these prefixes may be considered “legacy” prefixes. Other prefixes, one or more examples of which are detailed herein, indicate, and/or provide further capability, such as specifying particular registers, etc. The other prefixes typically follow the “legacy” prefixes.
The opcode field 603 is used to at least partially define the operation to be performed upon a decoding of the instruction. In some embodiments, a primary opcode encoded in the opcode field 603 is 1, 2, or 3 bytes in length. In other embodiments, a primary opcode can be a different length. An additional 3-bit opcode field is sometimes encoded in another field.
The addressing field 605 is used to address one or more operands of the instruction, such as a location in memory or one or more registers.
The content of the MOD field 742 distinguishes between memory access and non-memory access modes. In some embodiments, when the MOD field 742 has a value of b11, a register-direct addressing mode is utilized, and otherwise register-indirect addressing is used.
The register field 744 may encode either the destination register operand or a source register operand, or may encode an opcode extension and not be used to encode any instruction operand. The content of register index field 744, directly or through address generation, specifies the locations of a source or destination operand (either in a register or in memory). In some embodiments, the register field 744 is supplemented with an additional bit from a prefix (e.g., prefix 601) to allow for greater addressing.
The R/M field 746 may be used to encode an instruction operand that references a memory address, or may be used to encode either the destination register operand or a source register operand. Note the R/M field 746 may be combined with the MOD field 742 to dictate an addressing mode in some embodiments.
The SIB byte 704 includes a scale field 752, an index field 754, and a base field 756 to be used in the generation of an address. The scale field 752 indicates scaling factor. The index field 754 specifies an index register to use. In some embodiments, the index field 754 is supplemented with an additional bit from a prefix (e.g., prefix 601) to allow for greater addressing. The base field 756 specifies a base register to use. In some embodiments, the base field 756 is supplemented with an additional bit from a prefix (e.g., prefix 601) to allow for greater addressing. In practice, the content of the scale field 752 allows for the scaling of the content of the index field 754 for memory address generation (e.g., for address generation that uses 2scale*index+base).
Some addressing forms utilize a displacement value to generate a memory address. For example, a memory address may be generated according to 2scale*index+base+displacement, index*scale+displacement, r/m+displacement, instruction pointer (RIP/EIP)+displacement, register+displacement, etc. The displacement may be a 1-byte, 2-byte, 4-byte, etc. value. In some embodiments, a displacement field 607 provides this value. Additionally, in some embodiments, a displacement factor usage is encoded in the MOD field of the addressing field 605 that indicates a compressed displacement scheme for which a displacement value is calculated by multiplying disp8 in conjunction with a scaling factor N that is determined based on the vector length, the value of a b bit, and the input element size of the instruction. The displacement value is stored in the displacement field 607.
In some embodiments, an immediate field 609 specifies an immediate for the instruction. An immediate may be encoded as a 1-byte value, a 2-byte value, a 4-byte value, etc.
Instructions using the first prefix 601(A) may specify up to three registers using 3-bit fields depending on the format: 1) using the reg field 744 and the R/M field 746 of the Mod R/M byte 702; 2) using the Mod R/M byte 702 with the SIB byte 704 including using the reg field 744 and the base field 756 and index field 754; or 3) using the register field of an opcode.
In the first prefix 601(A), bit positions 7:4 are set as 0100. Bit position 3 (W) can be used to determine the operand size, but may not solely determine operand width. As such, when W=0, the operand size is determined by a code segment descriptor (CS.D) and when W=1, the operand size is 64-bit.
Note that the addition of another bit allows for 16 (24) registers to be addressed, whereas the MOD R/M reg field 744 and MOD R/M R/M field 746 alone can each only address 8 registers.
In the first prefix 601(A), bit position 2 (R) may an extension of the MOD R/M reg field 744 and may be used to modify the ModR/M reg field 744 when that field encodes a general purpose register, a 64-bit packed data register (e.g., a SSE register), or a control or debug register. R is ignored when Mod R/M byte 702 specifies other registers or defines an extended opcode.
Bit position 1 (X) X bit may modify the SIB byte index field 754.
Bit position B (B) B may modify the base in the Mod R/M R/M field 746 or the SIB byte base field 756; or it may modify the opcode register field used for accessing general purpose registers (e.g., general purpose registers 525).
In some embodiments, the second prefix 601(B) comes in two forms—a two-byte form and a three-byte form. The two-byte second prefix 601(B) is used mainly for 128-bit, scalar, and some 256-bit instructions; while the three-byte second prefix 601(B) provides a compact replacement of the first prefix 601(A) and 3-byte opcode instructions.
Instructions that use this prefix may use the Mod R/M R/M field 746 to encode the instruction operand that references a memory address or encode either the destination register operand or a source register operand.
Instructions that use this prefix may use the Mod R/M reg field 744 to encode either the destination register operand or a source register operand, be treated as an opcode extension and not used to encode any instruction operand.
For instruction syntax that support four operands, vvvv, the Mod R/M R/M field 746 and the Mod R/M reg field 744 encode three of the four operands. Bits[7:4] of the immediate 609 are then used to encode the third source register operand.
Bit[7] of byte 21017 is used similar to W of the first prefix 601(A) including helping to determine promotable operand sizes. Bit[2] is used to dictate the length (L) of the vector (where a value of 0 is a scalar or 128-bit vector and a value of 1 is a 256-bit vector). Bits[1:0] provide opcode extensionality equivalent to some legacy prefixes (e.g., 00=no prefix, 01=66H, 10=F3H, and 11=F2H). Bits[6:3], shown as vvvv, may be used to: 1) encode the first source register operand, specified in inverted (1s complement) form and valid for instructions with 2 or more source operands; 2) encode the destination register operand, specified in 1s complement form for certain vector shifts; or 3) not encode any operand, the field is reserved and should contain a certain value, such as 1111b.
Instructions that use this prefix may use the Mod R/M R/M field 746 to encode the instruction operand that references a memory address or encode either the destination register operand or a source register operand.
Instructions that use this prefix may use the Mod R/M reg field 744 to encode either the destination register operand or a source register operand, be treated as an opcode extension and not used to encode any instruction operand.
For instruction syntax that support four operands, vvvv, the Mod R/M R/M field 746, and the Mod R/M reg field 744 encode three of the four operands. Bits[7:4] of the immediate 609 are then used to encode the third source register operand.
The third prefix 601(C) can encode 32 vector registers (e.g., 128-bit, 256-bit, and 512-bit registers) in 64-bit mode. In some embodiments, instructions that utilize a writemask/opmask (see discussion of registers in a previous figure, such as
The third prefix 601(C) may encode functionality that is specific to instruction classes (e.g., a packed instruction with “load+op” semantic can support embedded broadcast functionality, a floating-point instruction with rounding semantic can support static rounding functionality, a floating-point instruction with non-rounding arithmetic semantic can support “suppress all exceptions” functionality, etc.).
The first byte of the third prefix 601(C) is a format field 1111 that has a value, in one example, of 62H. Subsequent bytes are referred to as payload bytes 1115-1119 and collectively form a 24-bit value of P[23:0] providing specific capability in the form of one or more fields (detailed herein).
In some embodiments, P[1:0] of payload byte 1119 are identical to the low two mmmmm bits. P[3:2] are reserved in some embodiments. Bit P[4] (R′) allows access to the high 16 vector register set when combined with P[7] and the ModR/M reg field 744. P[6] can also provide access to a high 16 vector register when SIB-type addressing is not needed. P[7:5] consist of an R, X, and B which are operand specifier modifier bits for vector register, general purpose register, memory addressing and allow access to the next set of 8 registers beyond the low 8 registers when combined with the ModR/M register field 744 and ModR/M R/M field 746. P[9:8] provide opcode extensionality equivalent to some legacy prefixes (e.g., 00=no prefix, 01=66H, 10=F3H, and 11=F2H). P[10] in some embodiments is a fixed value of 1. P[14:11], shown as vvvv, may be used to: 1) encode the first source register operand, specified in inverted (1s complement) form and valid for instructions with 2 or more source operands; 2) encode the destination register operand, specified in 1s complement form for certain vector shifts; or 3) not encode any operand, the field is reserved and should contain a certain value, such as 1111b.
P[15] is similar to W of the first prefix 601(A) and second prefix 611(B) and may serve as an opcode extension bit or operand size promotion.
P[18:16] specify the index of a register in the opmask (writemask) registers (e.g., writemask/predicate registers 515). In one embodiment of the invention, the specific value aaa=000 has a special behavior implying no opmask is used for the particular instruction (this may be implemented in a variety of ways including the use of a opmask hardwired to all ones or hardware that bypasses the masking hardware). When merging, vector masks allow any set of elements in the destination to be protected from updates during the execution of any operation (specified by the base operation and the augmentation operation); in other one embodiment, preserving the old value of each element of the destination where the corresponding mask bit has a 0. In contrast, when zeroing vector masks allow any set of elements in the destination to be zeroed during the execution of any operation (specified by the base operation and the augmentation operation); in one embodiment, an element of the destination is set to 0 when the corresponding mask bit has a 0 value. A subset of this functionality is the ability to control the vector length of the operation being performed (that is, the span of elements being modified, from the first to the last one); however, it is not necessary that the elements that are modified be consecutive. Thus, the opmask field allows for partial vector operations, including loads, stores, arithmetic, logical, etc. While embodiments of the invention are described in which the opmask field's content selects one of a number of opmask registers that contains the opmask to be used (and thus the opmask field's content indirectly identifies that masking to be performed), alternative embodiments instead or additional allow the mask write field's content to directly specify the masking to be performed.
P[19] can be combined with P[14:11] to encode a second source vector register in a non-destructive source syntax which can access an upper 16 vector registers using P[19]. P[20] encodes multiple functionalities, which differs across different classes of instructions and can affect the meaning of the vector length/rounding control specifier field (P[22:21]). P[23] indicates support for merging-writemasking (e.g., when set to 0) or support for zeroing and merging-writemasking (e.g., when set to 1).
Exemplary embodiments of encoding of registers in instructions using the third prefix 601(C) are detailed in the following tables.
Program code may be applied to input instructions to perform the functions described herein and generate output information. The output information may be applied to one or more output devices, in known fashion. For purposes of this application, a processing system includes any system that has a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.
The program code may be implemented in a high-level procedural or object-oriented programming language to communicate with a processing system. The program code may also be implemented in assembly or machine language, if desired. In fact, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language may be a compiled or interpreted language.
Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Embodiments of the invention may be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.
One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium which represents various logic within the processor, which when read by a machine causes the machine to fabricate logic to perform the techniques described herein. Such representations, known as “IP cores” may be stored on a tangible, machine readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that actually make the logic or processor.
Such machine-readable storage media may include, without limitation, non-transitory, tangible arrangements of articles manufactured or formed by a machine or device, including storage media such as hard disks, any other type of disk including floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritable's (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), phase change memory (PCM), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.
Accordingly, embodiments of the invention also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such embodiments may also be referred to as program products.
In some cases, an instruction converter may be used to convert an instruction from a source instruction set to a target instruction set. For example, the instruction converter may translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), morph, emulate, or otherwise convert an instruction to one or more other instructions to be processed by the core. The instruction converter may be implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be on processor, off processor, or part on and part off processor.
Similarly,
Method and Apparatus for Decompression Hardware Copy Engine with Efficient Sequence Overlapping Copy
Embodiments of the invention include a hardware decompression copy engine which resolves dependencies across literals and sequences during a sequence copy operation, allowing multiple sequence copy operations to be executed in parallel. An instruction is also described which, when executed, configures and controls the hardware decompression copy engine.
The amount of data required for running applications has grown exponentially, particularly with respect to Artificial intelligence (AI) workloads. Given the power, performance and area constraints, certain processors employ compression/decompression to manage this large amount of data. Commercial organizations use different algorithms best suited for their products. For example, Google™ uses Brotli, Facebook™ prefers Zstandard and Apple™ uses the LZFSE (Lempel-Ziv Finite State Entropy) algorithm for meeting compression/decompression requirements.
The basic metrics for any compression algorithm are the speed at which compression/decompression are performed and the compression ratio. Data is generally compressed once and decompressed multiple times. Thus, the decompression portion of the algorithm is more frequently used as compared to the compression. For any Lempel-Ziv (LZ)-based decompression, the decompression operations can be categorized into the broad categories of 1) literals and 2) sequences. Literals are those entries which occur for the very first time in the decompression operation and sequences are repetitions of literals. Literals are decoded first and copied as per the decoded sequences to form the decompressed data.
For larger data, the compression operation is performed by creating multiple blocks of the original data to increase the speed and compression ratio. While decompressing, the relationship between literals and sequences needs to be honored across blocks along with the relationship between the different blocks. As a result, while decoding the sequences, literals may need to be copied from the same sequence/block or from different sequences/blocks or a combination of both (an overlapping copy). As used herein, an “overlapping” copy refers to a copy operation including data or regions of data which were previously copied. This data is sometimes referred to herein as “overlapping” data. By way of example, and not limitation, the overlapping data can include decoded literals and/or decompressed data of earlier blocks/frames. These copy operations can consume a significant amount of execution time and memory transactions, making them a bottleneck for accelerating the overall data decompression.
To address such cases, embodiments of the invention include a hardware decompression copy engine which operates in accordance with the dependencies between literals and sequences across different sequences/blocks, and does so without significantly altering the power, performance, and silicon area budgets.
Concepts associated with the decompression of a compressed data stream will be described with respect to
The construction of the decompression stream starts by reading the first sequence. Pointers are initialized at 1300 and the sequence is read at 1301. At 1302, a number of literals are copied based on the value of l, and the corresponding literal pointer is incremented at 1303. At 1304, the offset (o*) from the current decompression pointer is determined and, at 1305, the current pointer of the decompression stream is updated (e.g., decremented by the offset value o*). At 1306, from the updated decompression pointer, m* bytes are copied to the destination address, and the decompressed stream is written to the memory at 1307. If additional sequences need to be decoded, determined at 1308, then the process returns to 1301.
One embodiment of the invention specifically optimizes the relationship between different sequences and blocks by intelligently managing the overlapping copies. Referring to
In operation, decompression logic 1405 (e.g., implemented in software, hardware or a combination thereof) reads the compressed input stream from the input region 1402 in memory 1401 to generate decoded literals and sequences. The sequence pre-processor 1431 reads the decoded sequences and searches for overlapping sections. Although not shown with arrows, in one embodiment, the decompression logic 1405 writes the decoded sequences to a region in the memory 1401 from which the sequence pre-processor 1431 reads. Once the overlapping regions of the sequences are identified (between literals and sequences or between sequences/blocks) the sequence pre-processor 1431 generates a series of copy instructions for execution by the copy engine 1432.
In one embodiment, for non-overlapping regions, the sequence pre-processor 1430 generates copy instructions to perform basic sequence copy operations. For overlapping sequences, the sequence pre-processor 1430 generates copy instructions which ensure that the overlapping sequences are read only once from the memory 1401 by the copy engine 1432 and copied to all the required sequences, thereby significantly reducing the number of required memory operations and accelerating overall execution by executing multiple copy instructions in parallel. The sequence pre-processor 1431 analyzes a set/batch of decoded sequences to find the overlapping regions in them and, in one embodiment, works across different blocks to increase the overall efficiency without any major implications.
The copy engine 1432 executes the copy instructions and performs the memory-copy operations to construct the decompressed data stream. In particular, the copy engine 1432 writes the decoded literal entries to the memory, reads the literals as per the decoded sequence requirement, and constructs and writes the decompressed stream to memory. In one embodiment, decoded literals are stored in memory 1401 by the decompression logic 1405 and are read directly from memory by the copy engine 1432 which writes them back to memory in response to copy instructions.
Thus, the sequence pre-processor 1431 reads the decoded sequences and generates a set of copy instructions executed by the copy engine 1432 such that all the overlapping copy operations across the sequences are processed together by reading only once from the memory.
One embodiment of the sequence pre-processor 1431 generates instructions in accordance with the following instruction format:
To generate these copy instructions, one embodiment of the sequence pre-processor 1431 consumes a batch of sequences and performs a byte-by-byte comparison across those decoded sequences in each batch. The overlapping bytes are grouped together in a merged copy instruction targeting all the sequences that are impacted. Similarly, for the non-overlapping bytes, simple copy instructions are generated targeting only those sequences that are impacted.
One embodiment of a decompression method using these techniques is illustrated in
At 1503, a number of literals (l*) are copied and the corresponding literal pointer is incremented at 1504. At 1505, the offset (o*) from the current decompression pointer is determined and, at 1506, the current pointer of the decompression stream is updated (e.g., decremented by the offset value o*). At 1507, from the updated decompression pointer, m* bytes are copied to the destination address, and the decompressed stream is written to the memory at 1508. If all instructions have been executed for the current batch of sequences, determined at 1509, then the process returns to 1503 and the next l* literals are copied from the memory. When all instructions for the current batch of sequences have been executed, and if all sequences have been processed, determined at 1510, then the process ends. If additional sequences remain to be processed, then the process returns to 1501.
Thus, the copy engine 1432 executes the copy instructions produced by the pre-processor 1431, updating the pointers accordingly. As shown in
The movement of the literal base pointer (lp) 1512, which points to decoded literals in memory 1511, is shown to the right (1512A-E) as each copy instruction 1530 is executed. In addition, for the decompressed stream 1540, decoded literal pointers, dl1 and dl1, and decoded sequence pointers, ds1 and ds2, corresponding to sequences 1 and 2, respectively, are updated with the execution of each copy instruction 1530.
With traditional decoding techniques, this example would require 10 memory read operations, whereas using the embodiments of the invention as illustrated in
Some embodiments of the invention include an instruction to drive the sequence copy engine 1432, referred to as a Sequence Execution Copy for N Sequences (SECPN) instruction. The N in the SECPN instruction indicates the number of decoded sequences in a given batch. For example, if sequence execution is enabled for two decoded sequences (batch size=2), the instruction is referred to as SECP2. In these embodiments, literal writes may still be performed through store instructions.
In one implementation, the format of the SECPN instruction is: SECPN tdest, tsrc1, tsrc2, tsrc3. The tsrc1 field is the base address from where the literals are copied from the memory. The subsequent literals are stored in the next consecutive memory location. The tsrc2 field indicates the base address in memory where the decoded sequences are written. The tsrc3 field is a history-buffer pointer and indication of history-buffer size. This field is optional and may be used if the output-buffer is insufficient to retrieve very far back references. The entries in the history-buffer may be populated by software. The tdest field indicates the destination location in memory where the final decompressed data is written. In one embodiment, the number of literals and sequences are tracked using counters in the hardware to track dependencies between them.
In one embodiment, the instruction for literal write (LTWR) has a format comparable to store instructions: LTWR tdest, < #immediate value>, where the immediate value is written to the memory address indicated in the tdest register.
In one embodiment, the copy engine hardware 1432 also manages interrupts, saving all counters and register values within a local memory (e.g., memory 1401) and/or a memory subsystem of the host processor. This embodiment includes a stall bit to stall operation of the copy engine hardware 1432. Once the interrupt has completed, the stall bit is cleared and the operation continues from the same point where it was stalled. In some implementations, the copy engine hardware 1432 finishes current memory read operations before serving the interrupt. For example, as soon as the interrupt is received, the copy engine hardware 1432 stops issuing any further memory reads and waits for any inflight reads to return the data from memory before stalling and passing control back to the host.
During a literal copy operation, a counter 1612 is updated for every literal written to the memory. This counter value is used in the dependency check block 1622 to avoid the problem of sequences running ahead of literals. Once any dependencies are cleared by the dependency check block 1622, the literals are sent directly to registers 1627 of the copy engine 1432 which may write the literals to the specified regions of memory 1650 via a memory controller 1628.
For a sequence copy operation, the sequence queue 1614 is populated with decoded sequences, such as the <l,o,m> format described above, which are fetched by the sequence pre-processor 1431 based on the batch size. The sequence pre-processor 1431 writes the copy instructions to the instruction queue 1623. The dependency check block 1622 checks the dependencies of the current set of sequence copy instructions with literals or any other sequences. When the dependency check block 1622 determines that there are no dependencies preventing the current set of sequence copy instructions from being processed (e.g., based on the counter value and/or a dependency bit value which is not set to 1), the instructions are processed by the copy engine 1432 for performing read-merge-write operations for generating the decompressed stream (e.g., as described in the examples above). An instruction decoder 1625 reads the instructions from the instruction queue 1623 and decodes the instructions, updating one or more counters 1624. Address generation logic 1626 maintains the pointer addresses for the copy instructions based on the counters 1624. Memory read/write operations are handled through the memory controller 1628. Depending on the memory wordline, write registers can be designed so that output bytes can be collected into fixed size data blocks (e.g., 16/32/64 Bytes), and then written out to memory 1650 as full writes.
In one embodiment, the decompression software/logic 1405, which decodes the literals and sequences and populates the memory 1401 (as previously described), also checks for illegal sequences for decompression before writing to memory 1401. This ensures, for example, that no copies exceed the end buffer.
Pseudocode specifying operations performed by one embodiment of the sequence pre-processor 1431 is provided directly below:
For every sequence in a batch: for every batch overlapping copy must be read once from the memory.
The following is a specific example for reading sequences from far away in the memory:
Second copy instruction:->since o1>>ds1, this will result in a negative value. When this Instruction is decoded and sent to the address generation logic it will generate address, such as (total decompressed streams written till now to the memory (from counter value)+base address of output+ds1−o2), which is sent to the memory.
Fourth copy instruction:-> In this case, the address generation logic will generate an address such as (total decompressed streams written till now to the memory (from counter value)+base address of output+ds1+ds2−o2), which is sent to the memory.
General-purpose processors today use highly efficient load/store engines to perform sequences of copy operations. To enhance the operations further some of the available solutions employ a dedicated mem-copy engine which is largely dependent on software to provide the correct set of sequence data to execute the copy operations. This is true even with the industry leading data-centric organizations.
Moreover, solving dependencies through software optimizations involve codes with many branches, which can degrade performance. Thus, software-based solutions are relatively inefficient, making it difficult to accelerate the underlying operations. Further, the available mem-copy engines do not address the dependencies between the sequences/blocks. They instead read the data again and again from memory in the case of overlapping copies, increasing the overall memory transactions which consumes the energy budget of the chip.
In contrast, the embodiments of the invention dynamically generate copy instructions such that overlapping copies across a batch of sequences are processed together, reading only once from memory, which significantly reduces the number of memory transactions required for decompression. These embodiments also accelerate the overall execution time by executing independent copy instructions generated by the sequence pre-processor in parallel.
These embodiments are also highly scalable. The batch sizes of the sequences can be varied depending on the available resources. The same can also be scaled across different blocks to avoid frequent overlapping copies across the blocks as well.
In addition, these embodiments acknowledge the dependencies between literals and sequences, between sequences, and between sequences and blocks through a dedicated counter-based logic in the hardware which ensures that none of the relationships are violated. This is achieved by generating multiple instructions of smaller copy strides between the inter-dependent regions. The hardware compares all the sequences in a batch and tries to compare byte-by-byte for sequence copies. All the common overlapping regions are combined and included in a new set of copy instructions.
The sequence pre-processor can also be fine-tuned to work with any existing mem-copy solutions by generating the instructions in the required format. This allows embodiments of the invention to be applied in any architecture to realize the benefits.
Embodiments of the invention may include various steps, which have been described above. The steps may be embodied in machine-executable instructions which may be used to cause a general-purpose or special-purpose processor to perform the steps. Alternatively, these steps may be performed by specific hardware components that contain hardwired logic for performing the steps, or by any combination of programmed computer components and custom hardware components.
The following are example implementations of different embodiments of the invention.
Example 1. An apparatus, comprising: a plurality of processing cores, one or more of the plurality of processing cores to execute program code to produce a plurality of literals and a plurality of sequences from a compressed data stream; and decompression acceleration circuitry to generate a decompressed data stream based on the plurality of literals and sequences, the decompression acceleration circuitry comprising: a sequence pre-processor to process batches of sequences of the plurality of sequences and generate a plurality of copy instructions, the sequence pre-processor to merge multiple copy operations corresponding to multiple sequences into a merged copy instruction; and a copy engine to execute the copy instructions to produce the decompressed data stream.
Example 2. The apparatus of example 1 wherein the sequence pre-processor is to read a first batch of sequences from memory and analyze the batch of sequences to identify overlapping bytes, the sequence pre-processor to generate the merged copy instruction based on the overlapping bytes.
Example 3. The apparatus of examples 1 or 2 wherein the copy engine comprises: an instruction queue to store the copy instructions; an instruction decoder to read the copy instructions from the instruction queue and decode the copy instructions; and address generation logic to indicate pointer addresses identifying locations in a memory at which to copy each literal of the plurality of literals.
Example 4. The apparatus of any of examples 1-3 wherein the address generation logic is to generate the pointer addresses based on a counter value provided by one or more counters, the one or more counters to be updated responsive to the instruction decoder decoding the copy instructions.
Example 5. The apparatus of any of examples 1-4 wherein the decompression acceleration circuitry further comprises: a sequence queue to store the batches of sequences to be processed by the sequence pre-processor; a literal buffer to store each literal of the plurality of literals prior to being copied to the locations in the memory.
Example 6. The apparatus of any of examples 1-5 further comprising: a dependency checker to identify dependencies between the plurality of literals and sequences and to perform control operations to prevent one or more sequences in a batch of sequences from running ahead of corresponding literals of the plurality of literals.
Example 7. The apparatus of any of examples 1-6 wherein a copy instruction of the plurality of copy instructions comprises an opcode indicating a copy operation and a plurality of fields including a first field to indicate a number of literals of the plurality of literals to be copied, a second field to indicate a number of times to copy the literals, a third field to indicate at least one destination address to which the literals are to be copied, and a fourth field to indicate a source address associated with the literals.
Example 8. The apparatus of any of examples 1-7 wherein the decompression acceleration circuitry further comprises a plurality of literal pointers and a plurality of sequence pointers, each literal pointer of the plurality of literal pointers identifying a next literal to be read from the memory and each sequence pointer of the plurality of sequence pointers associated with a sequence.
Example 9. The apparatus of any of examples 1-8 wherein the plurality of literal pointers are equal in number to the plurality of sequence pointers, and wherein the number comprises the number of sequences included in the batch of sequences.
Example 10. A method, comprising: producing a plurality of literals and a plurality of sequences from a compressed data stream; and generating a decompressed data stream based on the plurality of literals and sequences by performing a sequence of operations comprising: processing batches of sequences of the plurality of sequences and generate a plurality of copy instructions, wherein multiple copy operations are to be merged into at least one merged copy instruction; and executing the copy instructions to produce the decompressed data stream.
Example 11. The method of example 10 wherein processing batches of sequences further comprises: reading a first batch of sequences from memory and analyzing the batch of sequences to identify overlapping bytes; and generating the merged copy instruction based on the overlapping bytes.
Example 12. The method of examples 10 or 11 further comprising: storing the copy instructions in an instruction queue; reading the copy instructions from the instruction queue and decoding the copy instructions; and generating or reading pointer addresses identifying locations in a memory at which to copy each literal of the plurality of literals.
Example 13. The method of any of examples 10-12 wherein the pointer addresses are to be generated based on a counter value provided by one or more counters, the one or more counters to be updated responsive to decoding of the copy instructions.
Example 14. The method of any of examples 10-13 further comprising: storing the batches of sequences to be processed by the sequence pre-processor in a sequence queue; storing each literal of the plurality of literals in a literal buffer prior to being copied to the locations in the memory.
Example 15. The method of any of examples 10-14 further comprising: identifying dependencies between the plurality of literals and sequences and to perform control operations to prevent one or more sequences in a batch of sequences from running ahead of corresponding literals of the plurality of literals.
Example 16. The method of any of examples 10-15 wherein a copy instruction of the plurality of copy instructions comprises an opcode indicating a copy operation and a plurality of fields including a first field to indicate a number of literals of the plurality of literals to be copied, a second field to indicate a number of times to copy the literals, a third field to indicate at least one destination address to which the literals are to be copied, and a fourth field to indicate a source address associated with the literals.
Example 17. A machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform operations, comprising: producing a plurality of literals and a plurality of sequences from a compressed data stream; and generating a decompressed data stream based on the plurality of literals and sequences by performing a sequence of operations comprising: processing batches of sequences of the plurality of sequences and generate a plurality of copy instructions, wherein multiple copy operations are to be merged into at least one merged copy instruction; and executing the copy instructions to produce the decompressed data stream.
Example 18. The machine-readable medium of example 17 wherein processing batches of sequences further comprises: reading a first batch of sequences from memory and analyzing the batch of sequences to identify overlapping bytes; and generating the merged copy instruction based on the overlapping bytes.
Example 19. The machine-readable medium of examples 17 or 18 further comprising program code to cause the machine to perform operations, comprising: storing the copy instructions in an instruction queue; reading the copy instructions from the instruction queue and decoding the copy instructions; and generating or reading pointer addresses identifying locations in a memory at which to copy each literal of the plurality of literals.
Example 20. The machine-readable medium of any of examples 17-19 wherein the pointer addresses are to be generated based on a counter value provided by one or more counters, the one or more counters to be updated responsive to decoding of the copy instructions.
As described herein, instructions may refer to specific configurations of hardware such as application specific integrated circuits (ASICs) configured to perform certain operations or having a predetermined functionality or software instructions stored in memory embodied in a non-transitory computer readable medium. Thus, the techniques shown in the Figures can be implemented using code and data stored and executed on one or more electronic devices (e.g., an end station, a network element, etc.). Such electronic devices store and communicate (internally and/or with other electronic devices over a network) code and data using computer machine-readable media, such as non-transitory computer machine-readable storage media (e.g., magnetic disks; optical disks; random access memory; read only memory; flash memory devices; phase-change memory) and transitory computer machine-readable communication media (e.g., electrical, optical, acoustical or other form of propagated signals-such as carrier waves, infrared signals, digital signals, etc.). In addition, such electronic devices typically include a set of one or more processors coupled to one or more other components, such as one or more storage devices (non-transitory machine-readable storage media), user input/output devices (e.g., a keyboard, a touchscreen, and/or a display), and network connections. The coupling of the set of processors and other components is typically through one or more busses and bridges (also termed as bus controllers). The storage device and signals carrying the network traffic respectively represent one or more machine-readable storage media and machine-readable communication media. Thus, the storage device of a given electronic device typically stores code and/or data for execution on the set of one or more processors of that electronic device. Of course, one or more parts of an embodiment of the invention may be implemented using different combinations of software, firmware, and/or hardware. Throughout this detailed description, for the purposes of explanation, numerous specific details were set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without some of these specific details. In certain instances, well known structures and functions were not described in elaborate detail in order to avoid obscuring the subject matter of the present invention. Accordingly, the scope and spirit of the invention should be judged in terms of the claims which follow.
