Claims
- 1. A method of designing the layout of the physical geometry of an integrated circuit, the layout comprising a plurality of layers formed on a surface of a substrate, each layer including a pattern of a material having predetermined electrical properties, said method comprising:
- identifying a plurality of design rule variables, each design rule variable relating to at least one geometric constraint with respect to a pattern on at least one of said layers;
- defining first and second virtual coordinate axes with respect to the surface of said substrate; and
- defining the position of at least a portion of the pattern in at least one of said layers relative to at least one of said coordinate axes as a function of at least one of said design rule variables and the position of at least a portion of a pattern in another of said layers.
- 2. The method of claim 1, further including the step of defining a module specification which describes the function and technology of said integrated circuit, and wherein said step of defining the positions of at least a portion of the pattern in at least one of said layers is performed as a function of said module specification.
- 3. The method of claim 1, further including the step of generating a simulation model of said integrated circuit to mathematically simulate said integrated circuit, thereby allowing the performance of said integrated circuit to be verified and tested.
- 4. The method of claim 1, further including the step of plotting the layout of said integrated circuit after the positions of said patterns have been defined.
- 5. The method of claim 1 wherein said first and second virtual coordinate axes have an origin and a predetermined relationship to the surface of said substrate, and wherein said step of defining the position of at least a portion of the pattern in at least one of said layers includes the steps of:
- defining landmark points among said pattern by expressing the coordinates of said pattern in terms of reference points along said first and second virtual coordinate axes, the definition of at least one reference point on said layer being given relative to said origin as a function of a reference point on another of said layers and a set of said design rule variables; and
- substituting respective values for said design rule variables into the definitions of said reference points.
- 6. A method of designing the layout of the physical geometry of an integrated circuit, the layout comprising a plurality of layers formed on a surface of a substrate, each layer including a pattern of a material having predetermined electrical properties, the pattern of materials interacting to form elemental electrical circuit features, such as transistors, contacts, and signal traces, which interfit with each other, at least one elemental electrical circuit feature being subject to at least one geometric constraint relative to another elemental electrical feature, the method comprising the steps of:
- identifying a plurality of design rule variables, each design rule variable relating to at least one of said geometric constraints;
- defining first and second virtual coordinate axes with respect to the surface of said substrate; and
- defining the positions of at least a portion of some of said elemental electrical circuit features in at least one of said integrated circuit layers relative to at least one of said coordinate axes as a function of at least one of said design rule variables and the position of at least one portion of another of said elemental electrical circuit features on the same integrated circuit layer.
- 7. The method of claim 6, further including the step of defining a module specification which describes the function and technology of said integrated circuit, and wherein said step of defining the positions of at least some of said elemental electrical circuit features is performed as a function of said module specification.
- 8. The method of claim 6, further including the step of generating a simulation model of said integrated circuit to mathematically simulate said integrated circuit, thereby allowing the performance of said integrated circuit to be verified and tested.
- 9. The method of claim 6, further including the step of plotting the layout of said integrated circuit after the positions of said elemental electrical circuit features have been defined.
- 10. The method of claim 6 wherein said first and second virtual coordinate axes have an origin and a predetermined relationship to the surface of said substrate, and wherein said step of defining the position of at least some of said elemental electrical circuit features in at least one of said layers includes the steps of:
- defining landmark points among said elemental electrical circuit features by expressing the coordinates of said circuit features in terms of reference points along said first and second virtual coordinate axes, the definition of at least one reference point on said layer being given relative to said origin as a function of a reference point on another of said layers and a set of said design rule variables; and
- substituting respective values for said design rule variables into the definitions of said reference points.
- 11. An apparatus for designing the layout of the physical geometry of an integrated circuit, the layout comprising a plurality of layers formed on a surface of a substrate, each layer including a pattern of a material having predetermined electrical properties, said apparatus comprising:
- input means for accepting a plurality of values corresponding to respective design rule variables, each design rule variable relating to at least one geometric constraint with respect to at least one of said layers;
- means for defining first and second virtual coordinate axes with respect to the surface of said substrate; and
- memory means for storing said plurality of values and said first and second virtual coordinate axes; and
- processing means for defining the position of at least a portion of the pattern in at least one of said layers relative to at least one of said coordinate axes as a function of at least one of said design rule variables and the position of at least a portion of a pattern in another of said layers.
- 12. The apparatus of claim 11, further including a simulation model generator for generating a mathematical model of said integrated circuit to simulate said integrated circuit, thereby allowing the performance of said integrated circuit to be verified and tested.
- 13. The apparatus of claim 11, further including means operatively connected to said processing means for plotting the layout of said integrated circuit after the positions of said patterns have been defined.
- 14. An apparatus for designing the layout of the physical geometry of an integrated circuit, the layout comprising a plurality of layers formed on a surface of a substrate, each layer including a pattern of a material having predetermined electrical properties, the patterns of materials interacting to form elemental electrical circuit features such as transistors, contacts, and signal traces, which interfit with each other, at least one elemental electrical circuit feature being subject to at least one geometric constraint relative to another elemental electrical feature, said apparatus comprising:
- input means for accepting a plurality of values corresponding to respective design rule variables,, each design rule variable relating to at least one of said geometric constraints;
- means for defining first and second virtual coordinate axes with respect to the surface of said substrate;
- memory means for storing said plurality of values and said first and second virtual coordinate axes; and
- processing means for defining the positions of at least a portion of some of said elemental electrical circuit features in at least one of said integrated circuit layers relative to at least one of said coordinate axes as a function of at least one of said design rule variables and the position of at least one portion of another of said elemental electrical circuit features on the same integrated circuit layer.
- 15. The apparatus of claim 14, further including a simulation model generator for generating a mathematical model of said integrated circuit to simulate said integrated circuit, thereby allowing the performance of said integrated circuit to be verified and tested.
- 16. The apparatus of claim 14, further including means operatively connected to said processing means for plotting the layout of said integrated circuit after the positions of said elemental electrical circuit features have been defined.
CROSS-REFERENCE TO RELATED APPLICATION
This application is a continuation of U.S. application Ser. No. 06/917,917 filed Oct. 10, 1986, now abandonned.
US Referenced Citations (11)
Continuations (1)
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Number |
Date |
Country |
Parent |
917917 |
Oct 1986 |
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