Popescu, V.; Schultz, M., Spracklen, J.; Gibson, G.; Lightner, B.; Isaman, D. IEEE Micro, vol. 11 Issue: 3, Jun. 1991. Page(s): 10-13, 63-73.* |
Keller, J., “The 21264: A Superscalar Alpha Processor with Out-of-Order Execution,” Paper present at the Microprocessor Forum on Oct. 22-23, 1996. |
Farrell, J.A. and Fischer, T.C., “Issue Logic for a 600-Mhz Out-of-Order Execution Microprocessor,” J. Solid-State Circuts 33(5): 707-712 (1998). |
Scott, A.P., et al., “Four-Way Superscalar PA-RISC Processors,” J. Hewlett-Packard 1:1-9 (Aug. 1997). |
Farrell, J.A. and Fischer, T.C., “Issue Logic for a 600-MHz Out-of-Order Execution Microprocessor,” Symposium on VLSI Circuits Digest of Technical Papers, pp. 11-12 (1997). |
A Tour of the P6 Microarchitecture [online], [retrieved on Mar. 10, 1999]. Retrieved from the Internet <URL:http://eecad.sogang.ac.kr/AboutSite+Others/Others/intel/procs/p6/p6white/p6white.htm>. |
A 56-Entry Instruction Reorder Buffer [online ], [retreined on Mar. 10, 1999]. Retrieved from the Internet <URL:http://www.hp.com/ahp/framed/technology/micropro/micropro/pa-8000/docs/56entry.html>. |
Fischer, T. and Liebholz, D., “Design Tradeoffs in Stall-Control Circuits for 600MHz Instruction Queues,” Paper presented at the IEEE International Solid-State Circuits Conference (Feb. 1998). |
Kessler, R.E., Compaq Computer Corporation, “The Alpha 21264 Microprocessor,” IEEE Micro 24-36 (Mar.-Apr. 1999). |
Gieseke, Bruce A. et al., Digital Semiconductor, Digital Equipment Corporation, “A 600MHz Superscalar RISC Microprocessor with Out-Of-Order Execution,” ISSCC97/Session 10/High-Performance Microprocessors/Paper FA 10.7, IEEE International Solid-State Circuits Conference, 176-177, 451, (1997). |
Gwennap, Linley, “Digital 21264 Sets New Standard,” Microdesign Resources, Microdesign Report (Oct. 28, 1996). |
Liebholz, Daniel and Razdan, Rahul, Digital Equipment Corporation, “The Alpha 21264: A 500 MHz Out-of-Order Execution Microprocessor,” from Compcon Feb., 1997 Proceedings. |