The present application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2006-349378 filed on Dec. 26, 2006, with the Japanese Patent Office, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention generally relates to a method and apparatus for dividing an information bit string. The present invention particularly relates to a method and apparatus for dividing an information bit string that performs error detection coding or decoding with respect to an information bit string.
2. Description of the Related Art
Error diction code is used in a data transmission system that is required to transmit data without error, and is also used in an external storage device or the like that is required to read data without error. Error detection code is used for the purpose of detecting transmission error.
The CRC (Cyclic Redundancy Check) code is one type of error detection code, and is more often used than other types of error detection codes due to its capability of detecting burst errors. In the generation of a CRC code on the transmitter side, n-bit information bits are treated as a polynomial, which is divided by a generator polynomial. An m-bit remainder generated in this manner is added to the information bits to produce an (n+m)-bit string, thereby generating code data that is divisible by the generator polynomial. On the receiver side, the received data is divided by the generator polynomial. Error detection is performed by finding no error if the remainder is zero and otherwise finding error. Division calculation needs to be performed for the coding and decoding of a CRC code. A divider for this purpose may be implemented as hardware by use of a relatively simple circuit.
In a divider used for the coding and decoding of a CRC code, there is a need to input all the bits of an input polynomial successively with its highest-order term first. For the purpose of performing division, thus, a number of steps corresponding to the number of input bits need to be performed, giving rise to the problem that there is a large delay in the processing time.
In this regard, there is a divider apparatus (Patent Document 1) that divides an input data string into a plurality of sub-blocks, and performs division calculations concurrently in these sub-blocks for the purpose of achieving faster division calculation. The method disclosed in Patent Document 1 obtains partial remainders by performing division calculations individually in the sub-blocks, and performs shifting on each remainder by use of a shift matrix matching the order of each sub-block, followed by combining (through modulo-2 summation) the shifted remainders to produce a final remainder.
[Patent Document 1] Patent Application No. 2003-587014 (WO2003/090362)
[Patent Document 2] Japanese Patent Application Publication No. 2004-15285
In the method disclosed in Patent Document 1, one shift matrix is necessary for one shift amount. When the degree of a generator polynomial is m, a shift matrix is a matrix with a size of m×m whose elements are either “0” or “1”. If the length of input data is variable, thus, there is a need for the means to produce a shift matrix corresponding to a given data length. With an implementation using a ROM table, a memory size of m2 bits per shift amount is necessary, resulting in the need for a large ROM capacity, which would negatively affect the circuit size. For example, a ROM size of 2.9 Mbits (=5114×24×24) is necessary if the length of input data is 5114 bits and the matrix size is 24×24 bits.
Accordingly, there is a need for a method and apparatus for dividing an information bit string that can perform the division of an information string at high speed. There is also a need for a method and apparatus for dividing an information bit string that can perform the division of an information string at high speed by use of a relatively small table size.
It is a general object of the present invention to provide a method and apparatus for dividing an information bit string that substantially obviate one or more problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be presented in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a method and apparatus for dividing an information bit string particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages in accordance with the purpose of the invention, the invention provides a method of dividing an information bit string by a generator polynomial in a calculation apparatus having a multiplication unit and an addition unit, which includes dividing the information bit string into a plurality of sub-bit strings A1 through AN, causing the multiplication unit to multiply a remainder value by each bit of a sub-bit string Ai (1≦i≦N) successively with a most significant bit first so as to produce a multiplication result corresponding to the sub-bit string Ai, the remainder value being obtained by dividing a polynomial representation by the generator polynomial wherein the polynomial representation represents a bit string in which a bit position in the information bit string corresponding to a least significant bit of the sub-bit string Ai is set to “1” and remaining bit positions are set to “0”, and dividing, by the generator polynomial, a polynomial representing a bit string obtained by the addition unit performing modulo-2 addition that adds up multiplication results corresponding to the sub-bit strings A1 through AN.
According to another aspect of the present invention, an apparatus for dividing an information bit string by a generator polynomial includes a division unit configured to divide the information bit string into a plurality of sub-bit strings A1 through AN, a multiplication unit configured to multiply a remainder value by each bit of a sub-bit string Ai (1≦i≦N) successively with a most significant bit first so as to produce a multiplication result corresponding to the sub-bit string Ai, the remainder value being obtained by dividing a polynomial representation by the generator polynomial wherein the polynomial representation represents a bit string in which a bit position in the information bit string corresponding to a least significant bit of the sub-bit string Ai is set to “1” and remaining bit positions are set to “0”, and an addition unit configured to obtain a summed bit string by performing modulo-2 addition that adds up multiplication results corresponding to the sub-bit strings A1 through AN; and a division unit configured to divide a polynomial representing the summed bit string by the generator polynomial.
According to another aspect of the present invention, an apparatus for dividing an information bit string includes a multiplication unit configured to multiply a remainder value by each bit of a sub-bit string successively with a most significant bit first so as to obtain a multiplication result, the sub-bit string being one of a plurality of sub-bit strings into which the information bit string is divided, and the remainder value being obtained by dividing a bit “1” corresponding to an order of a least significant bit of the sub-bit string by a generator polynomial, an addition unit configured to perform modulo-2 addition that adds multiplication results obtained by the multiplication unit to an existing remainder value so as to obtain a sum, and a division unit configured to successively divide the sum obtained by the addition unit by the generator polynomial to produce a remainder, which is retained as the existing remainder value.
According to another aspect of the present invention, an error-detection-coding apparatus includes a division unit configured to add to an information bit string on a least-significant-bit side thereof as many zeros as necessary for CRC bits so as to produce an extended bit string and to divide the extended bit string into a plurality of sub-bit strings, a multiplication unit configured to multiply a remainder value by each bit of one of the sub-bit strings successively with a most significant bit first so as to obtain a multiplication result, the remainder value being obtained by dividing a bit “1” corresponding to an order of a least significant bit of the one of the sub-bit strings by a generator polynomial, an addition unit configured to perform modulo-2 addition that adds multiplication results obtained by the multiplication unit to an existing remainder value so as to obtain a sum, and a division unit configured to successively divide the sum obtained by the addition unit by the generator polynomial to produce a remainder, which is retained as the existing remainder value.
According to another aspect of the present invention, an error-detection-coding apparatus includes a division unit configured to divide an information bit string into a plurality of sub-bit strings, a multiplication unit configured to multiply a remainder value by each bit of one of the sub-bit strings successively with a most significant bit first so as to obtain a multiplication result, the remainder value being obtained by dividing by a generator polynomial a bit “1” corresponding to an order of a least significant bit of the one of the sub-bit strings shifted left by as many bits as a number of CRC bits, an addition unit configured to perform modulo-2 addition that adds multiplication results obtained by the multiplication unit to an existing remainder value so as to obtain a sum, and a division unit configured to successively divide the sum obtained by the addition unit by the generator polynomial to produce a remainder, which is retained as the existing remainder value.
According to another aspect of the present invention, an error-detection-decoding apparatus includes a division unit configured to divide a received bit string inclusive of a CRC code into a plurality of sub-bit strings, a multiplication unit configured to multiply a remainder value by each bit of one of the sub-bit strings successively with a most significant bit first so as to obtain a multiplication result, the remainder value being obtained by dividing a bit “1” corresponding to an order of a least significant bit of the one of, the sub-bit strings by a generator polynomial, an addition unit configured to perform modulo-2 addition that adds multiplication results obtained by the multiplication unit to an existing remainder value so as to obtain a sum, a division unit configured to successively divide the sum obtained by the addition unit by the generator polynomial to produce a remainder, which is retained as the existing remainder value, and an error-detection unit configured to check whether all bits of a final remainder value obtained by the division unit are zero.
According to another aspect of the present invention, an error-detection-decoding apparatus includes a division unit configured to divide a received bit string having CRC bits thereof replaced with zeros into a plurality of sub-bit strings, a multiplication unit configured to multiply a remainder value by each bit of one of the sub-bit strings successively with a most significant bit first so as to obtain a multiplication result, the remainder value being obtained by dividing a bit “1” corresponding to an order of a least significant bit of the one of the sub-bit strings by a generator polynomial, an addition unit configured to perform modulo-2 addition that adds multiplication results obtained by the multiplication unit to an existing remainder value so as to obtain a sum, a division unit configured to successively divide the sum obtained by the addition unit by the generator polynomial to produce a remainder, which is retained as the existing remainder value, and an error-detection unit configured to check whether a final remainder value obtained by the division unit matches the CRC bits extracted from the received bit string.
According to another aspect of the present invention, an error-detection-decoding apparatus includes a division unit configured to divide an information bit string included in a received bit string inclusive of a CRC code into a plurality of sub-bit strings, a multiplication unit configured to multiply a remainder value by each bit of one of the sub-bit strings successively with a most significant bit first so as to obtain a multiplication result, the remainder value being obtained by dividing by a generator polynomial a bit “1” corresponding to an order of a least significant bit of the one of the sub-bit strings shifted left by as many bits as a number of CRC bits, an addition unit configured to perform modulo-2 addition that adds multiplication results obtained by the multiplication unit to an existing remainder value so as to obtain a sum, a division unit configured to successively divide the sum obtained by the addition unit by the generator polynomial to produce a remainder, which is retained as the existing remainder value, and an error-detection unit configured to check whether a final remainder value obtained by the division unit matches the CRC code extracted from the received bit string.
According to another aspect of the present invention, an apparatus for dividing an information bit string includes a multiplication unit configured to multiply a remainder value by each bit of a sub-bit string successively with a most significant bit first so as to obtain a multiplication result, the sub-bit string being one of a plurality of sub-bit strings into which an information bit string of each code block is divided, and the remainder value being obtained by dividing a bit “1” corresponding to an order of a least significant bit of the sub-bit string by a generator polynomial, an addition unit configured to perform modulo-2 addition that adds multiplication results obtained by the multiplication unit to an existing remainder value so as to obtain a sum, a division unit configured to successively divide the sum obtained by the addition unit by the generator polynomial to produce a remainder value, which is retained as the existing remainder value, and an attaching unit configured to attach a remainder value obtained by the division unit for a current code block to a highest-order sub-bit string of a next code block.
According to at least one embodiment of the present invention, a method and apparatus for dividing an information bit string is provided that can perform the division of an information string at high speed. Further, the division of an information bit string is performed with a relatively small table size. It suffices for the table for storing remainder values for division operations to have m-bit data stored for each order of an input bit string. The size of the table is thus reduced to 1/m, compared with the configuration used in Patent Document 1.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings, in which:
In the following, the principle of a division method according to the present invention will be described.
In the following, all operations are modulo-2 operations. An operator representing modulo-2 addition is “+”. Input data is represented by polynomial A(x), which is divided by a generator polynomial G(x) of the m-th order to produce a remainder. A(x) is divided into M sub-blocks Ak(x) (0≦k≦M−1). The number of bits in each sub-block is arbitrary, and the number of bits of Ak(x) is represented as nk. The index k is assigned such that the smaller the value of k, the smaller the order of the corresponding sub-block is. Input data A(x) is then represented as:
The polynomial expression of data of each sub-block is as follows.
ai,k is the i-th bit of the k-th sub-block, and assumes either “0” or “1”.
For the sake of simplicity of representation, the longest bit length among the sub-block bit lengths is denoted as n, and Ak(x) is redefined as follows where ai,k=0 for i≧nk.
The input polynomial is rewritten by incorporating expression (4) into expression (1) as follows.
The quotient polynomial obtained by dividing xNk by G(x) is represented as QNk(x), and the remainder polynomial is represented as RNk(x). xNk is then represented as:
x
N
=Q
N
(x)·G(x)+RN
The first term of expression (7) is divisible by G(x), so that the remainder of A(x)/G(x) is equal to the remainder obtained by dividing the second term by G(x). Namely, the remainder being sought is the remainder of the following.
Bi(x) is the summation of products for all the sub-blocks where each of the products is obtained by multiplying an input data bit of a given sub-block by remainder polynomial RNk(x) corresponding to the order of the given sub-block. Accordingly, Bi(x) is a polynomial whose order is smaller than or equal to m−1. Further, the remainder being sought is the remainder of the following.
This is obtainable by the circuits shown in
In the following, embodiments of the present invention will be described with reference to the accompanying drawings. Throughout the drawings, the same reference numbers are used to refer to the same or corresponding elements.
An example of the generator polynomial is G(x)=x24+x23+x6+x5+x+1. The remainder table 10 stores remainders R0 through R50000 at addresses corresponding to the orders of x (i.e., power value) as they are obtained with respect to A(x)=x0 through x50000 which are input. The remainder table 10 can be accessed based on the order of the least significant bit of any given one of the sub-blocks SB1 through SBM−1 that constitute input data A(x). In the first embodiment, the remainder table 10 is configured to store all possible remainders so as to be able to cope with any sub-bit length by taking into account the fact that the input information bit string is divided into sub-blocks having arbitrary sizes.
In
Preferably, sub-bit strings having a length shorter than the longest bit length among the sub-blocks A2 through A0 have bits “0” (zeros) attached thereto on their higher-order side as many as necessary to reach the longest bit length, thereby making it easier for the addition unit 25 to align the phase of addition for remainder elements m (i.e., sub-results m of multiplication generated by the multipliers 21). In the illustrated example, the longest bet length is 7 bits of the sub-block A0. Accordingly, three “0” bits are attached to the bits of the sub-block A2 on the most-significant-bit side, and two “0” bits are attached to the bits of the sub-block A1 on the most-significant-bit side. The addition of “0” bits to a sub-bit string on its most-significant-bit side does not affect the division calculation.
At the initial stage of division operation, remainder values R12=111 and R7=001 are read from the remainder table 10 for storage in the registers 222 and 221, respectively, where these remainder values R12 and R7 are remainders left after dividing the least significant bits x12 and x7 of the sub-blocks A2(x) and A1(x) by G(x)=x3+x+1. All the registers (i.e., flop-flops) 32 of the division unit 30 are in the initialized (reset) state.
Since the least significant bit x0=1 of the sub-block A0 cannot be divided by third-order G(x), there is no need to refer to the remainder table 10 to obtain its remainder value R0=001. Attention is now focused on m6 through m0 that are obtained by multiplying the remainder value R0=001 by each bit of the bit string of the sub-block A0 successively from the most-significant bit to the least-significant bit. The bit string “0010001” that is obtained by arranging the least significant bits of m6 through m0 is equal to the input bit string “0010001”. In the first embodiment, thus, a multiplier 210 is not provided for the least-significant sub-block A0, and the addition unit 25 is configured to extract the bits of the least-significant sub-block A0 one by one from the most-significant bit to the least significant bit for addition to the results of other multiplication operations. In the explanation of
In this state, the bit strings A2(x) through A0(x) of the respective sub-blocks A2 through A0 are supplied one bit by one bit with the most-significant bit first. The multiplier 212 multiplies the remainder value R12=111 by the most significant bit x18=0 (i.e., one of the attached “0” bits) of A2(x), thereby producing three-bit remainder element m18=000. At the same time, the multiplier 211 multiplies the remainder value R7=001 by the most significant bit x13=0 of A1(x), thereby producing three-bit remainder element m13=000, and the multiplier 210 multiplies the remainder value R0=001 by the most significant bit x6=0 of A0(x), thereby producing three-bit remainder element m6=000. There is no multiplier 210 for A0(x) in reality, so that the addition unit 25 extracts the most significant bit x6=0 of A0(x) at this timing, and retains the extracted bit as the least significant bit of the remainder element m6.
The addition unit 25 performs modulo-2 addition with respect to the remainder elements m18, m13, and m6, thereby supplying the first addition result s6=000 to the division unit 30. The division unit 30 adds (i.e., modulo-2 addition) the addition result s6=000 to the existing remainder value (all bits are “0” in the initial state), and shifts the obtained sum (i.e., 000) left by one bit. Since the most significant bit (i.e. flip-flop 323) is zero, the shifted sum is retained as the first remainder value “000”.
After this, the second addition result s5=000 is processed in the same manner, so that the second remainder value stored in the division unit 30 is “000”. The third addition result is s4=001. Since the most significant bit is zero after the addition and shifting, the third remainder value is “010”. Thereafter, the addition unit 25 performs modulo-2 addition with respect to the remainder elements m15, m10, and m3, thereby supplying the fourth addition result s3=111 to the division unit 30. The division unit 30 adds (i.e., modulo-2 addition) the fourth addition result s3=111 to the third remainder value “010”, and shifts the obtained sum (i.e., “101”) to the left by one bit. Since the most significant bit is “1”, the shifted sum is divided (subtracted) by the generator polynomial G(x)=1011, thereby generating the fourth remainder value “001”. The same processes are thereafter performed in the same manner. When the seventh addition result s0=110 is added to the sixth remainder value “010”, the division unit 30 retains the final remainder value R=100.
In the following, the principle of interpolation will be described. P represents a constant value that is arbitrarily chosen. Nk is then divided as: Nk=P·u+1 (0≦l≦P−1). The quotient polynomial obtained by dividing xNk by G(x) is represented as QNk(x), and the remainder polynomial is represented as RNk(x). xNk is then represented as:
The first term of expression (11) is divisible by G(x), so that the remainder of xNk/G(x) is equal to the remainder obtained by dividing the second term RPu(x)x1 by G(x). The computation of RPu(x)x1/G(x) can be performed by a divider that utilizes shift registers. The value of RPu(x)x1 is first set in the shift registers, which are then shifted by one cycle while entering the bit “0” one by one from the least significant bit of the shift registers.
In the second embodiment, the additional provision of a few exclusive OR gates for performing division operation in addition to the registers 221 through 22M-1 of the first embodiment makes it possible to implement the divider units 231 through 23M-1. Further, the division operation equal in length to the P−1 cycles at the maximum is all that is necessary at the time of making initial settings. The size of the remainder table 11, on the other hand, can be reduced to 1/P as large.
The computation of RPu(x)x1 is performed by repeatedly shifting RPu(x) read from the remainder table 11 to the left by one bit while entering the bit “0” from the position of the least significant bit. When the remainder value RPu(x) is shifted by m bits, the shifted RPu(x)x1 includes m+P−1 bits at the maximum. The computation that divides the shifted result RPu(x)x1 by G(x) is a division operation performed with respect to a fixed number of input bits that is as many as m+P−1. Such computation can thus be implemented by use of a unique fixed circuit comprised only of exclusive-OR gates. The initial settings can thus be performed at high speed in the third embodiment.
This table shows the relationships between 55-bit inputs I[54] through I[0] and 24-bit division results 0[23] through O[0] that are obtained from the inputs by the division unit. Here, the operator “+” represents an exclusive-OR operation (which corresponds to modulo-2 addition). The output bit 0[22] is formed as I[45]+I[40]+I[22], and the output bit 0[21] is formed as I[44]+I[39]+I[21], for example. The remaining output bits are obtained in the same manner.
When the whole information bit string input into the division unit of the fourth embodiment is compared with the information bit string shown in
In the fifth embodiment, a multiplier 211 and register 221 are provided for SB#0. Provision is made such that a remainder value corresponding to an input that is shifted left by m bits is multiplied by each bit of SB#0 in addition to each bit of SB#3 through SB#1. Further, the addition unit 25 is configured to perform modulo-2 addition with respect to all the multiplication results obtained for SB#3 through SB#0. Other aspects of the configuration are the same as those shown in
In
In the fifth embodiment, only input information bits are divided into three sub-blocks A2 through A0. A remainder value corresponding to an input that is shifted left by m bits (m=3) is retrieved from the remainder table 10 with respect to each of the sub-blocks A2 through A0 for storage in the registers 222 through 220. For example, the order of the least significant bit is 9 for the sub-block A2. The order of the least significant bit is 12 if the sub-block A2 is shifted left by 3 bits, so that a remainder value R12=111 corresponding to an order of 12 is retrieved from the remainder table 10. By the same token, a remainder value R7=001 corresponding to an order of 7 is retrieved with respect to the sub-block A1, and a remainder value R3=011 corresponding to an order of 3 is retrieved with respect to the sub-block A0. The same multiplication and addition as previously described are performed for these pieces of information, resulting in the final remainder value R=101 (i.e., CRC bits) being retained in the division unit 30 at the end of the division operation. Outputting the CRC bits “101” following the input information bits b12 and b0 generates a CRC code.
In the case of the coding apparatus shown in
The division operation that divides the received bit string inclusive of the CRC bits is substantially the same as the division operation performed by the error-detection-coding apparatus described in connection with the fourth embodiment. When the division of the sub-blocks SB#3 through SB#0 inclusive of the CRC bits being zero comes to an end, the division unit 30′ has the remainder value retained therein as CRC bit-string information that is generated only from the received information. The all-bit-match-check unit 53 compares the generated CRC data output from the division unit 30′ with the received CRC data output from the serial-to-parallel conversion unit 53. The all-bit-match-check unit 53 produces an output indicative of no CRC error if the comparison shows a match, and produces an output indicative of CRC error if the comparison shows no match.
The error-detection-decoding apparatus receives the error-correction-decoded sub-blocks SB#3 through SB#0 in parallel, and also receives the final remainder value of SB#0 obtained by the error checking of CB#0 as it is attached to the head of SB#3 of CB#1. Such process is performed with respect to all code blocks. If the remainder value R obtained for the last code block is zero, the CRC check indicates no error. Otherwise, the CRC check indicates the existence of error.
If the sizes of the error-correction-decoded sub-blocks are the same across all the code blocks, initial setting for the division apparatus may be performed only once.
Continuing the division operation by using G(x) with respect to the second code block CB#1 involves continuing the division operation by use of G(x) by attaching the remainder value R=100 obtained by the division of CB#0 to the most significant bit of CB#1 (i.e., the most significant bit b15 of the sub-block A2). This is illustrated in
In the above description, the division apparatus according to the ninth embodiment is directed to a configuration in which the error-detection-decoding apparatus performs error detection with respect to turbo-decoding results when turbo codes are used as error correction codes. The application of the ninth embodiment, however, is not limited to this configuration. The division apparatus carries over a sub-remainder obtained by dividing a current code block by G(x) to the division operation of a next code block when sub-bit strings are provided for a plurality of sub-blocks into which each code block is divided, and may be utilized as the means to obtain the final remainder value when the last code block is provided. Such division apparatus may not only be used as an error-detection-decoding apparatus as described above, but also be used as an error-detection-coding apparatus.
In the embodiments described above, the division apparatus described in connection with the first embodiment was mainly used. Such configuration is not intended to be a limiting example. It is apparent that the division apparatus according to the second or third embodiment may as well be used.
In the embodiments described above, the adding of multiplication results by the addition unit 25 and the dividing of the sum by the division unit 30 are concurrently performed. Such configuration is not intended to be a limiting example. All the sums of multiplication results may be obtained first, followed by division by G(x).
In the embodiments described above, a specific example of division of an information bit string into certain sub-blocks was used. This is not intended to be a limiting example. The information bit string may be divided into sub-blocks having any desired number of bits.
Further, the present invention is not limited to these embodiments, but various variations and modifications may be made without departing from the scope of the present invention.
Number | Date | Country | Kind |
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2006-349378 | Dec 2006 | JP | national |