Patent Application
20050104840
This application claims the benefit of Korean Patent Application No. P2003-81174 filed in Korea on Nov. 17, 2003, which is hereby incorporated by reference.
1. Field of the Invention
This invention relates to a liquid crystal display, and more particularly to a driving method and apparatus for a liquid crystal display that is adaptive for making a stable brightness variation of a back light in correspondence with a gray level value of data.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) controls light transmittance of liquid crystal cells in accordance with video signals to thereby display a picture. Such an LCD has been implemented by an active matrix type having a switching device for each cell, and applied to a display device such as a monitor for a computer, office equipments, a cellular phone and the like. The switching device for the active matrix LCD mainly employs a thin film transistor (TFT).
Referring to
The system 20 applies vertical/horizontal signals Vsync and Hsync, clock signals DCLK, a data enable signal DE and data R, G and B to the timing controller 10.
The liquid crystal display panel 2 includes a plurality of liquid crystal cells Clc arranged, in a matrix type, at the intersections between the data lines D1 to Dm and the gate lines G1 to Gn. The thin film transistor TFT provided at each liquid crystal cell Clc applies a data signal from each data line D1 to Dm to the liquid crystal cell Clc in response to a scanning signal from the gate line G. Further, each liquid crystal cell Clc is provided with a storage capacitor Cst. The storage capacitor Cst is provided between a pixel electrode of the liquid crystal cell Clc and a pre-stage gate line or between the pixel electrode of the liquid crystal cell Clc and a common electrode line, to thereby constantly keep a voltage of the liquid crystal cell Clc.
The gamma voltage supplier 8 applies a plurality of gamma voltages to the data driver 4.
The data driver 4 converts digital video data R, G and B into analog gamma voltages (i.e., data signals) corresponding to gray level values in response to a control signal CS from the timing controller 10, and applies the analog gamma voltages to the data lines D1 to Dm.
The gate driver 6 sequentially applies a scanning pulse to the gate lines G1 to Gn in response to a control signal CS from the timing controller 10 to thereby select horizontal lines of the liquid crystal display panel 2 supplied with the data signals.
The timing controller 10 generates the control signals CS for controlling the gate driver 6 and the data driver 4 using the vertical/horizontal synchronizing signals Vsync and Hsync and the clock signal DCLK inputted from the system 20. Herein, the control signal CS for controlling the gate driver 6 is comprised of a gate start pulse GSP, a gate shift clock GSC and a gate output enable signal GOE, etc. Further, the control signal CS for controlling the data driver 4 is comprised of a source start pulse SSP, a source shift clock SSC, a source output enable signal SOE and a polarity signal POL, etc. The timing controller 10 re-aligns the data R, G and B from the system 20 to apply them to the data driver 4.
The DC/DC converter 14 boosts or drops a voltage of 3.3V. inputted from the power supply 12 to generate a voltage supplied to the liquid crystal display panel 2. Such a DC/DC converter 14 generates a gamma reference voltage, a gate high voltage VGH, a gate low voltage VGL and a common voltage Vcom.
The inverter 16 applies a driving voltage (or driving current) for driving the back light 18 to the back light 18. The back light 18 generates light corresponding to the driving voltage (or driving current) from the inverter 16 to apply it to the liquid crystal display panel 2.
In order to display a vivid image at the liquid crystal display panel 2 driven in this manner, a distinct contrast between brightness and darkness is made in correspondence with the input data. However, since the conventional back light 18 always produces a constant degree of brightness irrespectively of the data, it is difficult to display a dynamic and fresh image.
The present invention provides a driving method and apparatus for a liquid crystal display that is adaptive stabilizing the brightness variation of a back light in correspondence with a gray level value of input data.
A method of driving a liquid crystal display according to one aspect of the present invention includes dividing gray levels in a frame into a plurality of brightness areas, converting input data into brightness components, extracting a most-frequent value and/or an average value after arranging the brightness components into a histogram of the gray levels, and controlling brightness of a back light to correspond to the brightness areas to which the extracted most-frequent value or the average value belongs.
In the method, the brightness of the back light is controlled such that a different brightness of light can be produced for each of the plurality of brightness areas.
The most-frequent value is the gray level that is occupied by the greatest number of brightness components.
The most-frequent value and/or the average value is extracted from the histogram, and the brightness of the back light is controlled to correspond to the brightness area to which the extracted value belongs.
The most-frequent value may be selected when the most-frequent value is occupied by 40% or more of the total number of brightness components and the average value extracted otherwise.
The brightness of the back light increases with an increase in the brightness area to which the extracted value belongs.
At least one of the brightness areas is an area in which a previous brightness value of the back light is maintained.
A method of driving a liquid crystal display according to another aspect of the present invention includes dividing gray levels in a frame into a plurality of brightness areas, converting input data into brightness components, extracting a most-frequent value and/or an average value after arranging the brightness components into a histogram, generating a flag signal to correspond to the brightness area to which the extracted most-frequent value or average value belongs, and controlling brightness of a back light using the extracted most-frequent value or average value and the flag signal.
In the method, the flag signal maintains a previous flag signal when the most-frequent value or the average value belongs to a particular brightness area while permitting the flag signal to change when not in the particular brightness area.
When the flag signal keeps the previous flag signal, the brightness of the back light is not changed irrespective of the area to which the most-frequent value or the average value belongs.
The particular brightness area is an area in which the brightness value of the back light is not changed.
Otherwise, when the flag signal is changed, the brightness of the back light is changed to correspond to an area at which the most-frequent value or the average value belongs.
The most-frequent value is extracted from the histogram when the most-frequent value is occupied by 40% or more of the total brightness components in the frame while the average value is extracted from the histogram otherwise.
A driving apparatus for driving a liquid crystal display according to another aspect of the present invention includes a brightness/color separator for converting data into brightness components; a histogram analyzer for arranging the brightness components into a histogram for each frame; and back light control for extracting a most-frequent value and/or an average value of the brightness components from the histogram and for controlling brightness of a back light using the extracted value. The back light control divides the brightness components into a plurality of areas and controls the brightness of the back light in correspondence with an area to which the extracted most-frequent value or average value belongs.
In the driving apparatus, the back light control includes a most-frequent and/or average value extractor for extracting the most-frequent and/or average value; a back light controller for controlling the brightness of the back light to correspond to the area at which the extracted value belongs; and a digital to analog converter for converting a digital output signal of the back light controller into an analog output signal to apply it to an inverter.
The most-frequent value may be selected when the most-frequent value is occupied by 40% or more of the total number of brightness components and the average value extracted otherwise.
The back light controller controls the back light such that a different brightness of light can be supplied for each area.
The back light control includes a most-frequent value extractor for extracting the most-frequent and/or average value; a flag generator for generating a flag signal to correspond to the area to which the extracted value belongs to; a back light controller, being supplied with the extracted value and the flag signal, for controlling the brightness of the back light to correspond to the area at which the extracted value belongs when the flag signal has been changed in comparison with the previous flag signal; and a digital to analog converter for converting a digital output signal of the back light controller into an analog output signal to apply it to an inverter.
As above, the most-frequent value may be selected when the most-frequent value is occupied by 40% or more of the total number of brightness components and the average value extracted otherwise.
The back light controller does not control the brightness of the back light when the flag signal has the same value as the previous flag signal.
The flag generator generates a flag signal identical to the previous flag signal in at least one area of the plurality of areas.
Embodiments of the invention will be apparent from the following detailed description of the embodiments of the present invention with reference to the accompanying drawings, in which:
Referring to
The system 40 applies first vertical/horizontal signals Vsync1 and Hsync1, a first clock signal DCLK1, a first data enable signal DE1 and first data Ri, Gi and Bi to the picture quality enhancer 42.
The liquid crystal display panel 22 includes a plurality of liquid crystal cells Clc arranged, in a matrix type, at the intersections between the data lines D1 to Dm and the gate lines G1 to Gn. The thin film transistor TFT provided at each liquid crystal cell Clc applies a data signal from each data line D1 to Dm to the liquid crystal, cell Clc in response to a scanning signal from the gate line G. Further, each liquid crystal cell Clc is provided with a storage capacitor Cst. The storage capacitor Cst is provided between a pixel electrode of the liquid crystal cell Clc and a pre-stage gate line or between the pixel electrode of the liquid crystal cell Clc and a common electrode line, to thereby constantly keep a voltage of the liquid crystal cell Clc.
The gamma voltage supplier 28 applies a plurality of gamma voltages to the data driver 24.
The data driver 24 converts digital video data Ro, Go and Bo into analog gamma voltages (i.e., data signals) corresponding to gray level values in response to a control signal CS from the timing controller 30, and applies the analog gamma voltages to the data lines D1 to Dm.
The gate driver 26 sequentially applies a scanning pulse to the gate lines G1 to Gn in response to a control signal CS from the timing controller 30 to thereby select horizontal lines of the liquid crystal display panel 22 supplied with the data signals.
The timing controller 30 generates the control signals CS for controlling the gate driver 26 and the data driver 24 using second vertical/horizontal synchronizing signals Vsync2 and Hsync2 and a second clock signal DCLK2 inputted from the picture quality enhancer 42. Herein, the control signal CS for controlling the gate driver 26 is comprised of a gate start pulse GSP, a gate shift clock GSC and a gate output enable signal GOE, etc. Further, the control signal CS for controlling the data driver 24 is comprised of a source start pulse SSP, a source shift clock SSC, a source output enable signal SOE and a polarity signal POL, etc. The timing controller 30 re-aligns second data Ro, Go and Bo from the picture quality enhancer 42 to apply them to the data driver 24.
The DC/DC converter 34 boosts or drops a voltage of 3.3V inputted from the power supply 32 to generate a voltage supplied to the liquid crystal display panel 22. Such a DC/DC converter 34 generates a gamma reference voltage, a gate high voltage VGH, a gate low voltage VGL and a common voltage Vcom.
The inverter 36 applies a driving voltage (or driving current) corresponding to the brightness control signal Dimming from the picture quality enhancer 42 to the back light 38. In other words, a driving voltage (or driving current) applied from the inverter 36 to the back light 38 is determined by the brightness control signal Dimming from the picture quality enhancer 42. The back light 38 applies light corresponding to the driving voltage (or driving current) from the inverter 36 to the liquid crystal display panel 22.
The picture quality enhancer 42 extracts brightness components using the first data Ri, Gi and Bi from the system 40, and generates second data Ro, Go and. Bo obtained by a change in gray level values of the first data Ri, Gi and Bi in correspondence with the extracted brightness components. In this case, the picture quality enhancer 42 generates the second data Ro, Go and Bo such that the contrast is selectively expanded with respect to the input data Ri, Gi and Bi.
Further, the picture quality enhancer 42 generates a brightness control signal Dimming corresponding to the brightness components to apply it to the inverter 36. For instance, the picture quality enhancer 42 extracts the most frequent value (i.e., the gray level value in the frame having the maximum number of brightness components) and/or an average value (i.e., an average value of the gray levels in the frame) from the brightness components, and generates the brightness control signal Dimming using the extracted most frequent value and/or average value. The picture quality enhancer 42 divides the brightness of the back light corresponding to gray levels of the brightness components into at least two regions, and generates the brightness control signal Dimming such that regions of the brightness are selected in correspondence with the control value.
Moreover, the picture quality enhancer 42 generates second vertical/horizontal synchronizing signals Vsync2 and Hsync2, a second clock signal DCLK2 and a second data enable signal DE2 synchronized with the second data Ro, Go and Bo with the aid of the first vertical/horizontal synchronizing signals Vsync1 and Hsync1, the first clock signal DCLK1 and the first data enable signal DE1 inputted from the system 40.
To this, end, as shown in
The image signal modulator 70 extracts the brightness components Y from the first data Ri, Gi and Bi, and generates the second data Ro, Go and Bo in which a contrast is partially emphasized with the aid of the extracted brightness components Y. To this end, the image signal modulator 70 includes a brightness/color separator 50, a delay 52, a brightness/color mixer 54, a histogram analyzer 56 and a data processor 58.
The brightness/color separator 50 separates the first data Ri, Gi and Bi into brightness components Y and chrominance components U and V. Herein, the brightness components Y and the chrominance components U and V are obtained by the following equations:
Y=0.229×Ri+0.587×Gi+0.114×Bi (1)
U=0.493×(Bi−Y) (2)
V=0.887×(Ri−Y) (3)
The histogram analyzer 56 divides the brightness components Y into gray levels for each frame. In other words, the histogram analyzer 56 arranges the brightness components Y for each frame to correspond to the gray levels, thereby obtaining a histogram as shown in
The data processor 58 generates modulated brightness components YM having a selectively emphasized contrast using the analyzed histogram from the histogram analyzer 56 by various methods. Such methods are disclosed in Korean Patent Applications Nos. 2003-036289, 2003-040127 and 2003-041127, etc. previously filed by the applicants and which are incorporated by reference herein.
The delay 52 delays chrominance components U and V until the brightness components YM modulated by the data processor 58 are produced. Further, the delay 52 applies the delayed chrominance components VD and UD to the brightness/color mixer 54 to be synchronized with the modulated brightness components YM.
The brightness/color mixer 54 generates second data Ro, Go and Bo with the aid of the modulated brightness components YM and the delayed chrominance components UD and VD. Herein, the second data Ro, Go and Bo is obtained by the following equations:
Ro=YM+0.000×UD+1.140×VD (4)
Go=YM−0.396×UD−0.581×VD− (5)
Bo=YM+2.029×UD+0.000×VD (6)
Since the second data Ro, Go and Bo obtained by the brightness/color mixer 54 has been produced from the modulated brightness components YM having an expanded contrast, they have more expanded contrast than the first data Ri, Gi and Bi. The second data Ro, Go and Bo produced such that the contrast can be expanded as mentioned above is applied to the timing controller 30.
The control unit 68 receives the first vertical/horizontal synchronizing signals Vsync1 and Hsync1, the first clock signal DCLK1 and the first data enable signal DE1 from the system 40. Further, the controller 68 generates the second vertical/horizontal synchronizing signals Vsync2 and Hsync2, the second clock signal DCLK2 and the second data enable signal DE2 in such a manner to be synchronized with the second data Ro, Go and Bo, and applies them to the timing controller 30.
The back light control 72 extracts the most-frequent value F from the histogram analyzer 56, and generates a brightness control signal Dimming using the extracted most-frequent value F.
To this end, the back light control 72 includes a most-frequent value extractor 60, a back light controller 64 and a digital to analog converter 66.
As shown in
The most-frequent value extractor 60 extracts the most-frequent value F from the histogram analyzer 56 to apply it to the back light controller 64.
The digital to analog converter 66 converts a digital control signal into an analog control signal (i.e., a brightness control signal) Dimming to apply it to the inverter 36.
An operation procedure of the back light control 72 will be described in detail below.
First, the most-frequent value extractor 60 extracts a most-frequent value F from a histogram analyzed by the histogram analyzer 56 to apply it to the back light controller 64. The back light controller 64 having received the most-frequent value F checks the area (i.e., gray level value) to which the most-frequent value F applied thereto belongs. In other words, the back light controller 64 checks the area to which the most-frequent value F inputted thereto belongs, of areas in
The brightness control signal Dimming from the back light controller 64 is applied to the digital to analog converter 66. The digital to analog converter 66 converts a brightness control signal Dimming applied thereto into an analog signal to apply it to the inverter 36. The inverter 36 controls the back light 38 such that light is applied to the liquid crystal display panel 22 in correspondence with the brightness control signal Dimming. In other words, the present back light control 72 divides gray levels into a plurality of areas and applies the brightness control signal Dimming such that light having a different brightness for each area is generated in correspondence with the most-frequent value F, thereby displaying a vivid image. That is to say, brightness of a light is controlled in accordance with the area to which the most-frequent value F belongs, thereby displaying a picture having a distinct contrast on the liquid crystal display panel 22.
However, in such an embodiment, the brightness of the back light 38 is sensitive to the most-frequent value F, which may cause sparkling. For instance, if the most-frequent value F moves between an area of middle brightness (F1<F<F2) and an area of low brightness (F<F1) and back again in adjacent frames, then the brightness of the back light 38 is changed dramatically in the adjacent frames. This is problematic if there is only a slight change in the brightness between frames but the most-frequent value F happens to fall close to the border between areas so that this slight change in the brightness is intensified by the change in the brightness of the back light 38 being supplied. Changing back and forth between two adjacent areas in successive frames causes sparkling in the liquid crystal display panel 22.
In order to overcome such a problem, a picture quality enhancer according another embodiment of the present invention is shown in
Referring to
To this end, the back light control 72 includes a most-frequent value extractor 60, a flag generator 62, a back light controller 64 and a digital to analog converter 66.
The most-frequent value extractor 60 extracts a most-frequent value F from the histogram analyzer 56 to apply it to the back light controller 64 and the flag generator 62.
The flag generator 62 applies a control signal of ‘0’ or ‘1’ to the back light controller 64 in correspondence with the most-frequent value F inputted thereto. An operation procedure of the flag generator 62 will be described in detail with reference to
The flag generator 62 includes a comparator array 98 for comparing gray levels of boundary values F1 to F4 dividing the areas of the brightness components Y with that of the most-frequent value F, a logical sum operation array 100 logically summing the output values of the comparator array 98, and an output part 96 for generating a control signal using the output value of the logical sum operation array 100.
The comparator array 98 includes a first comparator 80 for comparing the most-frequent value F with the first boundary value F1, a second comparator 82 for comparing the most-frequent value F with the second boundary value F2, a third comparator 84 for comparing the most-frequent value F with the third boundary value F3, and a fourth comparator 86 for comparing the most-frequent value F with the fourth boundary value F2.
The first to fourth boundary values F1 to F4 are value established so as to divide gray level values into a plurality of areas. Herein, each boundary value F1 to F4 are experimentally set such that a vivid image can be displayed. For instance, the third boundary value F3 is set to a gray level value of 64; the first boundary value F1 is set to a gray level value of 96; the second boundary value F2 is set to a gray level value of 160; and the fourth boundary value F4 is set to a gray level value of 190.
Firstly, the first comparator 80 compares the most-frequent value F and the first boundary value F1 to thereby output ‘1’ when the most-frequent value F is larger than the first boundary value F1 while outputting ‘0’ otherwise. The second comparator 82 compares the most-frequent value F and the second boundary value F2 to thereby output ‘1’ when the most-frequent value F is smaller than the second boundary value F2 while outputting ‘0’ otherwise. The third comparator 84 compares the most-frequent value F and the third boundary value F3 to thereby output ‘1’ when the most-frequent value F is smaller than the third boundary value F3 while outputting ‘0’ otherwise. The fourth comparator 86 compares the most-frequent value F and the fourth boundary value F4 to thereby output ‘1’ when the most-frequent value F is larger than the fourth boundary value F4 while outputting ‘0’ otherwise.
The logical sum operation array 100 logically sums the output values to apply it to the output part 96. Herein, the logical sum operation array 100 outputs values to be applied to a clock EN and an input D of the output part 96. To this end, the logical sum operation array 100 includes first and second AND gates 88 and 90 that logically sum the output values of the first and second comparators 80 and 82, a first OR gate 92 that logically sum the output values of the third and fourth comparators 84 and 86, and a second OR gate 94 that logically sums the output values of the second AND gate 90 and the first OR gate 92. An output signal of the first AND gate 88 is applied to the input D of the output part 96. An output signal of the second OR gate 94 is applied to the clock EN of the output part 96.
The output part 96 applies a control signal (i.e., a flag signal) of ‘1’ or ‘0’ to the back light controller 64 in correspondence with a value from the logical sum operation array 100. To this end, the output part 96 consists of a D flip-flop. The input D of the D flip-flop receives the output signal of the first AND gate 88 while the clock EN thereof receives the output signal of the second OR gate 94.
An operation procedure of the flag generator 62 will be described assuming that the most-frequency value F is positioned between the first boundary value F1 and the second boundary value F2. If the most-frequency value F is positioned between the first boundary value F1 and the second boundary value F2, then the first and second comparators 80 and 82 output signals of ‘1’ while the third and fourth comparators 84 and 86 output signals of ‘0’.
If the first and second comparators 80 and 82 output signals of ‘1’, then the first and second AND gates 88 and 90 output signals of ‘0’. Herein, the signal of ‘1’ outputted from the first AND gate 88 is applied to the input D of the output part 96. If the second AND gate 90 outputs a signal of ‘1’, then the second OR gate 94 outputs a signal of ‘1’ irrespectively of an output of the first OR gate 92. Herein, the signal of ‘1’ outputted from the second OR gate 94 is applied to the clock EN of the output part 96. Thus, if the most-frequency value F is positioned between the first boundary value F1 and the second boundary value F2, then the flag generator 62 applies a flag signal of ‘1’ to the back light controller 64.
If the most-frequent value F has a gray level less than the third boundary value F3, then the first and fourth comparators 80 and 86 output signals of ‘0’ while the second ‘and third comparators 82 and 84 output signals of ‘1’.
If the first comparator 80 outputs a signal of ‘0’, then the first and second AND gates 88 and 90 output signals of ‘0’ irrespectively of an output of the second comparator 82. Herein, the signal of ‘0’ outputted from the first AND gate 88 is applied to the input D of the output part 96. If the third comparator 80 outputs a signal of ‘1’, then the first OR gate 92 outputs a signal of ‘1’. On the other hand, if the first OR gate 92 outputs a signal of ‘1’, then the second OR gate 94 also outputs a signal of ‘1’. Herein, the signal of ‘1’ outputted from the second OR gate 94 is applied to the clock EN of the output part 96. Thus, the most-frequent value F has a gray level less than the third boundary value F3, then the flag generator 62 applies a flag signal of ‘0’ to the back light controller 64.
On the other hand, if the most-frequent value F has a gray level more than the fourth boundary value F4, then the first and fourth comparators 80 and 86 output signals of ‘1’ while the second and third comparators 82 and 84 output signals of ‘0’. Herein, the signal of ‘0’ outputted from the first AND gate 88 is applied to the input D of the output part 96. If the fourth comparator 86 outputs a signal of ‘1’, then the first OR gate 92 outputs a signal of ‘1’. On the other hand, if the first OR gate 92 outputs a signal of ‘1’, then the second OR gate 94 also outputs a signal of ‘1’. Herein, the signal of ‘1’ outputted from the second OR gate 94 is applied to the clock EN of the output part 96. Thus, the most-frequent value F has a gray level more than the fourth boundary value F4, then the flag generator 62 applies a flag signal of ‘0’ to the back light controller 64.
If the most-frequent value F has a gray level between the third boundary value F3 and the first boundary value F1, then the second comparator 82 outputs a signal of ‘1’ while the remaining comparators 80, 84 and 86 other than the second comparator 82 output signals of ‘0’.
If the first comparator 80 outputs a signal of ‘0’, then the first and second AND gates 88 and 90 output signals of ‘0’ irrespectively of an output of the second comparator 82. Herein, the signal of ‘0’ outputted from the first AND gate 88 is applied to the input D of the output part 96. If the third and fourth comparators 84 and 86 output signals of ‘0’, then the first and second OR gates 92 and 94 output signals of ‘0’. The signal of ‘0’ outputted from the second OR gate 94 is applied to the clock EN of the output part 96. Herein, as the signal of ‘0’ is inputted to the clock EN of the output part 96, the output part 96 does not generate an output. In other words, if the most-frequent value F has a gray level between the third boundary value F3 and the first boundary value F1, then the flag generator 62 maintains a previous flag signal (of ‘0’ or ‘1’)
On the other hand, if the most-frequent value F has a gray level between the second boundary value F2 and the fourth boundary value F4, then the first comparator 80 outputs a signal of ‘1’ while the remaining comparators 82, 84 and 86 other than the first comparator 80 output signals of ‘0’.
If the second comparator 82 outputs a signal of ‘0’, then the first and second AND gates 88 and 90 output signals of ‘0’ irrespectively of an output of the first comparator 80. Herein, the signal of ‘0’ outputted from the first AND gate 88 is applied to the input D of the output part 96. If the third and fourth comparators 84 and 86 output signals of ‘0’, then the first and second OR gates 92 and 94 output signals of ‘0’. The signal of ‘0’ outputted from the second OR gate 94 is applied to the clock EN of the output part 96. Herein, as the signal of ‘0’ is inputted to the clock EN of the output part 96, the output part 96 does not generate an output. In other words, if the most-frequent value F has a gray level between the second boundary value F2 and the fourth boundary value F4, then the flag generator 62 maintains a previous flag signal (of ‘0’ or ‘1’).
In other words, the present flag generator 62 applies a flag signal of ‘1’ to the back light controller 64 when the most-frequent value F is positioned between the first boundary value F1 and the second boundary value F2 while applying a flag signal of ‘0’ to the back light controller 64 when the most-frequent value F has a value less than the third boundary value F3 or a value more than the fourth boundary value F4. On the other hand, the flag generator 62 maintains the previous flag signal when the most-frequent value F is positioned between the third boundary value F3 and the first boundary value F1 or between the second boundary value F2 and the fourth boundary value F4.
The back light controller 64 divides gray levels into a plurality of areas as shown in
The digital to analog converter 66 converts a digital control signal into an analog control signal (i.e., a brightness control signal) Dimming to apply it to the inverter 36.
An operation procedure of the back light control 72 will be described in detail below.
First, the most-frequent value extractor 60 extracts a most-frequent value F from a histogram analyzed by the histogram analyzer 56 to apply it to the back light controller 64 and the flag generator 62. The flag generator 62 applies a flag signal corresponding to a gray level value having the most-frequent value applied thereto to the back light controller 64. Herein, the flag generator 62 sets at least one of gray level area maintaining the previous flag value, and maintains the previous flag value when the most-frequent value F is included in this area.
The back light controller 64 receives a flag signal from the flag generator 62. The back light controller 64 having received the flag signal checks whether or not the flag signal has been changed, and generates a brightness control signal to correspond to the most-frequent value F when the flag signal has been changed. On the other hand, the back light controller 64 generates a brightness control signal such that light having the previous brightness is kept irrespective of the most-frequent value F when the flag signal has not been changed (i.e., when the current flag signal is identical to the previous, flag signal).
The brightness control signal Dimming from the back light controller 64 is applied to the digital to analog converter 66. The digital to analog converter 66 converts a brightness control signal Dimming applied thereto into an analog signal to apply it to the inverter 36. Then, the inverter 36 controls the back light 38 in response to the brightness control signal Dimming, thereby applying light corresponding to the brightness control signal Dimming to the liquid crystal display panel 22.
In other words, the back light control 72 according to another embodiment of the present invention sets a plurality of gray level areas having changed brightness and applies the brightness control signal Dimming such that light having a different brightness for each area can be generated in correspondence with the most-frequent value F, thereby displaying a vivid image. That is to say, the brightness is controlled in accordance with the gray level area to which the most-frequent value F belongs, thereby displaying a picture having a distinct contrast on the liquid crystal display panel 22.
Furthermore, the back light controller according to another embodiment of the present invention generates a brightness control signal such that a gray level having the previous brightness can be displayed in at least one area of the plurality of gray level areas having changed brightness. Accordingly, brightness of the back light 38 is relatively insensitive to small changes in the most-frequent value F between frames, thereby displaying an image with a stable brightness on the liquid crystal display panel 22.
For instance, since the flag signal keeps the same value even though a gray level value having the most-frequent value F is alternates around the third boundary value F3 in
Alternatively, in the present invention, an average value extractor 102 may be included in the back light control 72 as shown in
Otherwise, the present-back light control 72 may include a most-frequent/average value extractor 104 as shown in
As mentioned above, the embodiment of the present invention shown in
The flag generator 62 and the back light controller 64 generate a brightness control signal using an average value or the most-frequent value F applied thereto. Since a detailed operation procedure of the flag generator 62 and the back light controller 64 has been described with reference to
As described above, according to the present invention, data is changed into brightness components to be arranged into a histogram for each frame and brightness of the back light is controlled with the aid of a most-frequent value and/or an average value extracted from the histogram, thereby displaying a vivid image. Furthermore, according to the present invention, a plurality of gray level areas having changed brightness components of the back light are established and control is preformed such that the previous brightness is kept at at least one area of these gray level areas, thereby displaying a stable brightness of image.
Although the present invention has been explained by the embodiments shown in the drawings described above, it should be understood to the ordinary skilled person in the art that the invention is not limited to the embodiments, but rather that various changes or modifications thereof are possible without departing from the spirit of the invention. Accordingly, the scope of the invention shall be determined only by the appended claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| P2003-81174 | Nov 2003 | KR | national |
