Claims
- 1. A semiconductor workpiece, comprising:a metal layer, wherein the metal layer has topical non-planarities extending from the metal layer; an inorganic dielectric ARC layer disposed directly on the metal layer and directly on the topical non-planarities extending from the metal layer, wherein said inorganic dielectric ARC layer functions as a hard mask, and wherein said inorganic dielectric ARC layer has a substantially uniform thickness over the topical non-planarities extending from the metal layer; and a photoresist layer disposed on the ARC layer opposite the metal layer.
- 2. The workpiece recited in claim 1 wherein the ARC layer comprises silicon oxynitride.
- 3. The workpiece recited in claim 2 wherein the ARC layer consists essentially of silicon oxynitride.
- 4. The workpiece recited in claim 1 wherein the ARC layer is deposited on the metal layer by chemical vapor deposition.
- 5. The workpiece recited in claim 4, wherein the ARC layer is deposited on the metal layer by plasma enhanced chemical vapor deposition.
- 6. The workpiece recited in claim 1 wherein the photoresist layer is between 0.1 to 2 microns thick.
- 7. The workpiece recited in claim 6 wherein the photoresist layer is 0.6 to 1.0 microns thick.
- 8. A metallic stack for a semiconductor interconnect, comprising:a metal layer, wherein the metal layer has topical non-planarities extending from the metal layer; an inorganic dielectric ARC layer disposed directly on the metal layer and directly on the topical non-planarities extending from the metal layer, wherein said inorganic dielectric ARC layer functions as a hard mask, and wherein said inorganic dielectric ARC layer has a substantially uniform thickness over the topical non-planarities extending from the metal layer; and a barrier layer disposed on the metal layer opposite the ARC layer.
- 9. The metallic stack recited in claim 8 wherein the ARC layer comprises silicon oxynitride.
- 10. The metallic stack recited in claim 9 wherein the ARC layer consists essentially of silicon oxynitride.
- 11. The metallic stack recited in claim 8 wherein the ARC layer is deposited on the metal layer by chemical vapor deposition.
- 12. The metallic stack recited in claim 11 wherein the ARC layer is deposited on the metal layer by plasma enhanced chemical vapor deposition.
- 13. The metallic stack recited in claim 8 wherein the stack is about 1,000 to 20,000 Angstroms thick.
- 14. The metallic stack recited in claim 13 wherein the stack is about 5,000 to 8,000 Angstroms thick.
- 15. A semiconductor device, comprising:an oxide layer formed on a wafer; and at least one microelectronic structure extending from the oxide layer and including: a barrier layer disposed on the oxide layer; a metal layer disposed on the barrier layer; an inorganic dielectric ARC layer disposed directly on the metal layer, wherein said inorganic dielectric ARC layer functions as a hard mask; and a residual photoresist layer disposed directly on said inorganic dielectric ARC layer.
- 16. The semiconductor device recited in claim 15 wherein the ARC layer consists essentially of silicon oxynitride.
- 17. The semiconductor device recited in claim 16 wherein the ARC layer is formed by plasma enhanced chemical vapor deposition.
CROSS-REFERENCE TO RELATED APPLICATION
This application is a divisional of copending U.S. utility application entitled, “Method and Apparatus for High-Resolution In-Situ Plasma Etching of Inorganic and Metal Films,” having Ser. No. 09/275,628, filed Mar. 24, 1999 now U.S. Pat. No. 6,291,361, which is entirely incorporated herein by reference.
US Referenced Citations (25)