Claims
- 1. A software apparatus, comprising:
a software tool adapted to function with at least one or more cells having one or more virtual buses, the one or more cells for an integrated circuit design, wherein the one or more virtual buses comprise:
a plurality of ports representing a common power signal, the plurality of ports including at least two power ports on a same layer, the at least two power ports separated by substantially insulating material in the same layer.
- 2. The apparatus of claim 1, wherein the common power signal includes a fixed voltage signal.
- 3. The apparatus of claim 1, wherein, after the at least two power ports are coupled together by one or more electrical paths, the plurality of ports representing the common power signal share the common power signal.
- 4. The apparatus of claim 1, wherein an integrated circuit of the integrated circuit design is formed by a CMOS process.
- 5. The apparatus of claim 1, wherein an integrated circuit of the integrated circuit design is formed by a Bi-CMOS process.
- 6. The apparatus of claim 1, wherein an integrated circuit of the integrated circuit is formed by a Bipolar process.
- 7. The apparatus of claim 1, wherein an integrated circuit of the integrated circuit design is formed by a Gallium-Arsenide process.
- 8. The apparatus of claim 1, wherein an integrated circuit of the integrated circuit design is formed by a Silicon-on-Insulator process.
- 9. The apparatus of claim 1, wherein the one or more cells includes at least one standard cell.
- 10. The apparatus of claim 1, wherein the one or more cells includes at least one gate array cell.
- 11. The apparatus of claim 1, wherein the one or more cells includes at least one analog cell.
- 12. The apparatus of claim 1, wherein the one or more cells includes at least one analog mixed signal cell.
- 13. The apparatus of claim 1, wherein the one or more cells includes at least one analog and digital cell.
- 14. The apparatus of claim 1, wherein the one or more cells includes at least one functional block cell.
- 15. A software apparatus, comprising:
a software tool adapted to function with at least one or more cells having one or more virtual buses, the one or more cells for an integrated circuit design, wherein the one or more virtual buses comprise:
a plurality of ports sharing a common power signal, the plurality of ports including at least two power ports on a same layer, the at least two power ports separated by substantially insulating material in the same layer, the at least two power ports coupled together via one or more electrical paths on one or more layers of metal.
- 16. The apparatus of claim 15, wherein the common power signal includes a fixed voltage signal.
- 17. The apparatus of claim 15, wherein an integrated circuit of the integrated circuit design is formed by a CMOS process.
- 18. The apparatus of claim 15, wherein an integrated circuit of the integrated circuit design is formed by a Bi-CMOS process.
- 19. The apparatus of claim 15, wherein an integrated circuit of the integrated circuit design is formed by a Bipolar process.
- 20. The apparatus of claim 15, wherein an integrated circuit of the integrated circuit design is formed by a Gallium-Arsenide process.
- 21. The apparatus of claim 15, wherein an integrated circuit of the integrated circuit design is formed by a Silicon-on-Insulator process.
- 22. The apparatus of claim 15, wherein the one or more cells includes at least one standard cell.
- 23. The apparatus of claim 15, wherein the one or more cells includes at least one gate array cell.
- 24. The apparatus of claim 15, wherein the one or more cells includes at least one analog cell.
- 25. The apparatus of claim 15, wherein the one or more cells includes at least one analog mixed signal cell.
- 26. The apparatus of claim 15, wherein the one or more cells includes at least one analog and digital cell.
- 27. The apparatus of claim 15, wherein the one or more cells includes at least one functional block cell.
- 28. A software apparatus, comprising:
a software tool adapted to function with at least one or more virtual tap cells for an integrated circuit design, comprising:
one or more electrical couplings to at least one of: one or more wells and one or more substrates, wherein at least one electrical coupling of the one or more electrical couplings is positioned entirely outside one or more hierarchies of the one or more virtual tap cells.
- 29. The apparatus of claim 28, wherein the at least one of the one or more taps is placed physically entirely in one of the one or more virtual tap cells.
- 30. The apparatus of claim 28, wherein the at least one of the one or more taps is placed physically partly in one of the one or more virtual tap cells.
- 31. The apparatus of claim 28, wherein the at least one of the one or more taps is placed physically partly in one of the one or more other cells.
- 32. The apparatus of claim 28, wherein the at least one electrical coupling is positioned physically on top of the one or more virtual tap cells.
- 33. The apparatus of claim 28, wherein the at least one electrical coupling is positioned physically between at least two of the one or more virtual tap cells.
- 34. The apparatus of claim 28, wherein an integrated circuit of the integrated circuit design is formed by a CMOS process.
- 35. The apparatus of claim 28, wherein an integrated circuit of the integrated circuit design is formed by a Bi-CMOS process.
- 36. The apparatus of claim 28, wherein an integrated circuit of the integrated circuit design is formed by a Bipolar process.
- 37. The apparatus of claim 28, wherein an integrated circuit of the integrated circuit design is formed by a Gallium-Arsenide process.
- 38. The apparatus of claim 28, wherein an integrated circuit of the integrated circuit design is formed by a Silicon-on-Insulator process.
- 39. The apparatus of claim 28, wherein the one or more cells includes at least one standard cell.
- 40. The apparatus of claim 28, wherein the one or more cells includes at least one gate array cell.
- 41. The apparatus of claim 28, wherein the one or more cells includes at least one analog cell.
- 42. The apparatus of claim 28, wherein the one or more cells includes at least one analog mixed signal cell.
- 43. The apparatus of claim 28, wherein the one or more cells includes at least one analog and digital cell.
- 44. The apparatus of claim 28, wherein the one or more cells includes at least one functional block cell.
- 45. A software apparatus, comprising:
a software tool adapted to function with at least one or more cells for an integrated circuit design adapted to have the software tool perform placement of one or more features of the integrated circuit design, the placement of at least one of the one or more features occurring primarily to place one or more electrical couplings to one or more wells.
- 46. The apparatus of claim 45, wherein the software tool includes a router.
- 47. The apparatus of claim 45, wherein an integrated circuit of the integrated circuit design is formed by a CMOS process.
- 48. The apparatus of claim 45, wherein an integrated circuit of the integrated circuit design is formed by a Bi-CMOS process.
- 49. The apparatus of claim 45, wherein an integrated circuit of the integrated circuit design is formed by a Bipolar process.
- 50. The apparatus of claim 45, wherein an integrated circuit of the integrated circuit design is formed by a Gallium-Arsenide process.
- 51. The apparatus of claim 45, wherein an integrated circuit of the integrated circuit design is formed by a Silicon on Insulator process.
- 52. The apparatus of claim 45, wherein the one or more cells includes at least one standard cell.
- 53. The apparatus of claim 45, wherein the one or more cells includes at least one gate array cell.
- 54. The apparatus of claim 45, wherein the one or more cells includes at least one analog cell.
- 55. The apparatus of claim 45, wherein the one or more cells includes at least one analog mixed signal cell.
- 56. The apparatus of claim 45, wherein the one or more cells includes at least one analog and digital cell.
- 57. The apparatus of claim 45, wherein the one or more cells includes at least one functional block cell.
- 58. A software apparatus, comprising:
a software tool adapted to function with at least one or more cells for an integrated circuit design adapted to have the software tool perform placement of one or more features of the integrated circuit design, the placement of at least one of the one or more features occurring at a granularity level of one or more electrical couplings to one or more wells.
- 59. The apparatus of claim 58, wherein the software tool includes a router.
- 60. The apparatus of claim 58, wherein an integrated circuit of the integrated circuit design is formed by a CMOS process.
- 61. The apparatus of claim 58, wherein an integrated circuit of the integrated circuit design is formed by a Bi-CMOS process.
- 62. The apparatus of claim 58, wherein an integrated circuit of the integrated circuit design is formed by a Bipolar process.
- 63. The apparatus of claim 58, wherein an integrated circuit of the integrated circuit design is formed by a Gallium-Arsenide process.
- 64. The apparatus of claim 58, wherein an integrated circuit of the integrated circuit design is formed by a Silicon on Insulator process.
- 65. The apparatus of claim 58, wherein the one or more cells includes at least one standard cell.
- 66. The apparatus of claim 58, wherein the one or more cells includes at least one gate array cell.
- 67. The apparatus of claim 58, wherein the one or more cells includes at least one analog cell.
- 68. The apparatus of claim 58, wherein the one or more cells includes at least one analog mixed signal cell.
- 69. The apparatus of claim 58, wherein the one or more cells includes at least one analog and digital cell.
- 70. The apparatus of claim 58, wherein the one or more cells includes at least one functional block cell.
- 71. A software apparatus, comprising:
a software tool adapted to function with at least one or more cells for an integrated circuit design adapted to have a software tool perform placement of one or more features of the integrated circuit design, the placement of at least one of the one or more features occurring primarily to place one or more electrical couplings to one or more substrates.
- 72. The apparatus of claim of 71, wherein the software tool includes a router.
- 73. The apparatus of claim 71, wherein an integrated circuit of the integrated circuit design is formed by a CMOS process.
- 74. The apparatus of claim 71, wherein an integrated circuit of the integrated circuit design is formed by a Bi-CMOS process.
- 75. The apparatus of claim 71, wherein an integrated circuit of the integrated circuit design is formed by a Bipolar process.
- 76. The apparatus of claim 71, wherein an integrated circuit of the integrated circuit design is formed by a Gallium-Arsenide process.
- 77. The apparatus of claim 71, wherein an integrated circuit of the integrated circuit design is formed by a Silicon-on-Insulator process.
- 78. The apparatus of claim 71, wherein the one or more cells includes at least one standard cell.
- 79. The apparatus of claim 71, wherein the one or more cells includes at least one gate array cell.
- 80. The apparatus of claim 71, wherein the one or more cells includes at least one analog cell.
- 81. The apparatus of claim 71, wherein the one or more cells includes at least one analog mixed signal cell.
- 82. The apparatus of claim 71, wherein the one or more cells includes at least one analog and digital cell.
- 83. The apparatus of claim 71, wherein the one or more cells includes at least one functional block cell.
- 84. A software apparatus, comprising:
a software tool adapted to function with at least one or more cells for an integrated circuit design adapted to have the software tool perform placement of one or more features of the integrated circuit design, the placement of at least one of the one or more features occurring at a granularity level of one or more electrical couplings to one or more substrates.
- 85. The apparatus of claim 84, wherein the software tool includes a router.
- 86. The apparatus of claim 84, wherein an integrated circuit of the integrated circuit design is formed by a CMOS process.
- 87. The apparatus of claim 84, wherein an integrated circuit of the integrated circuit design is formed by a Bi-CMOS process.
- 88. The apparatus of claim 84, wherein an integrated circuit of the integrated circuit design is formed by a Bipolar process.
- 89. The apparatus of claim 84, wherein an integrated circuit of the integrated circuit design is formed by a Gallium-Arsenide process.
- 90. The apparatus of claim 84, wherein an integrated circuit of the integrated circuit design is formed by a Silicon-on-Insulator process.
- 91. The apparatus of claim 84, wherein the one or more cells includes at least one standard cell.
- 92. The apparatus of claim 84, wherein the one or more cells includes at least one gate array cell.
- 93. The apparatus of claim 84, wherein the one or more cells includes at least one analog cell.
- 94. The apparatus of claim 84, wherein the one or more cells includes at least one analog mixed signal cell.
- 95. The apparatus of claim 84, wherein the one or more cells includes at least one analog and digital cell.
- 96. The apparatus of claim 84, wherein the one or more cells includes at least one functional block cell.
- 97. A software apparatus, comprising:
a software tool adapted to function with at least one or more cells for an integrated circuit design, the one or more cells having one or more ports, the one or more ports adapted to couple to one or more metal substantially octagonal via structures.
- 98. The apparatus of claim 97, wherein the one or more substantially octagonal via structures comprises a square via cut.
- 99. The apparatus of claim 97, wherein the one or more substantially octagonal via structures comprises a rectangular via cut.
- 100. The apparatus of claim 97, wherein an integrated circuit of the integrated circuit design is formed by a CMOS process.
- 101. The apparatus of claim 97, wherein an integrated circuit of the integrated circuit design is formed by a Bi-CMOS process.
- 102. The apparatus of claim 97, wherein an integrated circuit of the integrated circuit design is formed by a Bipolar process.
- 103. The apparatus of claim 97, wherein an integrated circuit of the integrated circuit design is formed by a Gallium Arsenide process.
- 104. The apparatus of claim 97, wherein an integrated circuit of the integrated circuit design is formed by a Silicon-on-Insulator process.
- 105. The apparatus of claim 97, wherein the one or more cells includes at least one standard cell.
- 106. The apparatus of claim 97, wherein the one or more cells includes at least one gate array cell.
- 107. The apparatus of claim 97, wherein the one or more cells includes at least one analog cell.
- 108. The apparatus of claim 97, wherein the one or more cells includes at least one analog mixed signal cell.
- 109. The apparatus of claim 97, wherein the one or more cells includes at least one analog and digital cell.
- 110. The apparatus of claim 97, wherein the one or more cells includes at least one functional block cell.
- 111. A software apparatus, comprising:
a software tool adapted to function with at least one or more cells for an integrated circuit design, comprising significant features including at least one of: signal ports, power ports, and one or more boundaries of the one or more cells, wherein the significant features are freely placed according to a minimum drawing resolution.
- 112. The apparatus of claim 111, wherein the minimum drawing resolution corresponds to a layout grid.
- 113. The apparatus of claim 111, wherein the significant features include signal ports.
- 114. The apparatus of claim 111, wherein the significant features include power ports.
- 115. The apparatus of claim 111, wherein the significant features include one or more boundaries of the one or more cells.
- 116. The apparatus of claim 111, wherein an integrated circuit of the integrated circuit design is formed by a CMOS process.
- 117. The apparatus of claim 111, wherein an integrated circuit of the integrated circuit design is formed by a Bi-CMOS process.
- 118. The apparatus of claim 111, wherein an integrated circuit of the integrated circuit design is formed by a Bipolar process.
- 119. The apparatus of claim 111, wherein an integrated circuit i of the integrated circuit design is formed by a Gallium-Arsenide process.
- 120. The apparatus of claim 111, wherein an integrated circuit i of the integrated circuit design s formed by a Silicon-on-Insulator process.
- 121. The apparatus of claim 111, wherein the one or more cells includes at least one standard cell.
- 122. The apparatus of claim 111, wherein the one or more cells includes at least one gate array cell.
- 123. The apparatus of claim 111, wherein the one or more cells includes at least one analog cell.
- 124. The apparatus of claim 111, wherein the one or more cells includes at least one analog mixed signal cell.
- 125. The apparatus of claim 111, wherein the one or more cells includes at least one analog and digital cell.
- 126. The apparatus of claim 111, wherein the one or more cells includes at least one functional block cell.
- 127. A software apparatus, comprising:
a software tool adapted to function with at least one or more arbitrarily shaped cells for an integrated circuit design, wherein the boundary of the arbitrarily shaped cells include vertices, the vertices adapted to be freely placed according to a minimum drawing resolution.
- 128. The apparatus of claim 127, wherein the minimum drawing resolution corresponds to a layout grid.
- 129. The apparatus of claim 127, wherein an integrated circuit of the integrated circuit design is formed by a CMOS process.
- 130. The apparatus of claim 127, wherein an integrated circuit of the integrated circuit design is formed by a Bi-CMOS process.
- 131. The apparatus of claim 127, wherein an integrated circuit of the integrated circuit design is formed by a Bipolar process.
- 132. The apparatus of claim 127, wherein an integrated circuit of the integrated circuit design is formed by a Gallium-Arsenide process.
- 133. The apparatus of claim 127, wherein an integrated circuit of the integrated circuit design is formed by a Silicon-on-Insulator process.
- 134. The apparatus of claim 127, wherein the one or more cells includes at least one standard cell.
- 135. The apparatus of claim 127, wherein the one or more cells includes at least one gate array cell.
- 136. The apparatus of claim 127, wherein the one or more cells includes at least one analog cell.
- 137. The apparatus of claim 127, wherein the one or more cells includes at least one analog mixed signal cell.
- 138. The apparatus of claim 127, wherein the one or more cells includes at least one analog and digital cell.
- 139. The apparatus of claim 127, wherein the one or more cells includes at least one functional block cell.
- 140. A software apparatus, comprising:
a software tool adapted to function with at least one or more cells for an integrated circuit design, at least one of the one or more cells including at least one of: one or more standard cells, and one or more gate array cells, wherein the one or more cells are designed to be substantially coupled by one or more routing wires freely placed according to a minimum drawing resolution.
- 141. The apparatus of claim 140, wherein the minimum drawing resolution corresponds to a layout grid.
- 142. The apparatus of claim 140, wherein an integrated circuit of the integrated circuit design is formed by a CMOS process.
- 143. The apparatus of claim 140, wherein an integrated circuit of the integrated circuit design is formed by a Bi-CMOS process.
- 144. The apparatus of claim 140, wherein the integrated circuit of the integrated circuit design is formed by a Bipolar process.
- 145. The apparatus of claim 140, wherein the integrated circuit of the integrated circuit design is formed by a Gallium-Arsenide process.
- 146. The apparatus of claim 140, wherein the integrated circuit of the integrated circuit design is formed by a Silicon-on-Insulator process.
- 147. The apparatus of claim 140, wherein the one or more cells includes at least one standard cell.
- 148. The apparatus of claim 140, wherein the one or more cells includes at least one gate array cell.
- 149. A software apparatus, comprising:
a software tool adapted to function with at least one or more cells for an integrated circuit design, the one or more cells having one or more ports clipped by an angle.
- 150. The apparatus of claim 149, wherein an integrated circuit of the integrated circuit design is formed by a CMOS process.
- 151. The apparatus of claim 149, wherein an integrated circuit of the integrated circuit design is formed by a Bi-CMOS process.
- 152. The apparatus of claim 149, wherein the integrated circuit of the integrated circuit design is formed by a Bipolar process.
- 153. The apparatus of claim 149, wherein the integrated circuit of the integrated circuit design is formed by a Gallium-Arsenide process.
- 154. The apparatus of claim 149, wherein the integrated circuit of the integrated circuit design is formed by a Silicon-on-Insulator process.
- 155. The apparatus of claim 149, wherein the one or more cells includes at least one standard cell
- 156. The apparatus of claim 149, wherein the one or more cells includes at least one gate array cell.
- 157. The apparatus of claim 149, wherein the one or more cells includes at least one analog cell.
- 158. The apparatus of claim 149, wherein the one or more cells includes at least one analog mixed signal cell.
- 159. The apparatus of claim 149, wherein the one or more cells includes at least one analog and digital cell.
- 160. The apparatus of claim 149, wherein the one or more cells includes at least one functional block cell.
- 161. The apparatus of claim 149, wherein the angle is about 45 degrees.
- 162. A software apparatus, comprising:
a software tool adapted to function with at least a first plurality of one or more cells for an integrated circuit design, the first plurality of one or more cells having a first plurality of one or more structures on one or more edges of the first plurality of one or more cells, wherein the first plurality of one or more cells is adapted to be positioned by a second plurality of one or more cells, the second plurality of one or more cells having a second plurality of one or more structures on one or more edges of the second plurality of one or more cells, such that at least one structure of the first plurality of one or more structures overlaps at least one structure of the second plurality of one or more structures.
- 163. The apparatus of claim 162, wherein an integrated circuit of the integrated circuit design is formed by a CMOS process.
- 164. The apparatus of claim 162, wherein an integrated circuit of the integrated circuit design is formed by a Bi-CMOS process.
- 165. The apparatus of claim 162, wherein an integrated circuit of the integrated circuit design is formed by a Bipolar process.
- 166. The apparatus of claim 162, wherein an integrated circuit of the integrated circuit design is formed by a Gallium-Arsenide process.
- 167. The apparatus of claim 162, wherein an integrated circuit of the integrated circuit design is formed by a Silicon-on-Insulator process.
- 168. The apparatus of claim 162, wherein the one or more cells includes at least one standard cell
- 169. The apparatus of claim 162, wherein the one or more cells includes at least one gate array cell.
- 170. The apparatus of claim 162, wherein the one or more cells includes at least one analog cell.
- 171. The apparatus of claim 162, wherein the one or more cells includes at least one analog mixed signal cell.
- 172. The apparatus of claim 162, wherein the one or more cells includes at least one analog and digital cell.
- 173. The apparatus of claim 162, wherein the one or more cells includes at least one functional block cell.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of U.S. Provisional Application No. 60/295,241, filed Jun. 1, 2001; U.S. Provisional Application No. 60/295,238, filed Jun. 1, 2001; and U.S. Provisional Application No. 60/295,134, filed Jun. 1, 2001. These applications are incorporated herein by reference.
Provisional Applications (3)
|
Number |
Date |
Country |
|
60295241 |
Jun 2001 |
US |
|
60295238 |
Jun 2001 |
US |
|
60295134 |
Jun 2001 |
US |